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Introduction to  導論

Microelectronic Fabrication
微電子製造

Course Overview 課程概述
Yao-Joe Yang 楊耀久

Integrated Circuits 集成電路

ANALOG TM TM ^(TM){ }^{\mathrm{TM}} ADXL-50 ARCHITECTURE
類比 TM TM ^(TM){ }^{\mathrm{TM}} ADXL-50 架構


5 mm 5 mm ∼5mm\sim 5 \mathrm{~mm}
  • Mass production example. all components were integrated in to a chip
    大規模生產範例。所有元件都整合到一個晶片中。

International Student Edition
國際學生版

Microelectronic CIRCUITS FIFTH EDITION
微電子電路 第五版


INTERNATIONAL SIXTH EDITION MICROELECTRONIC CIRCUITS
國際第六版微電子電路
OXFORD 牛津


SEDRA/SMITH

Microelectronic Circuits
微電子電路

seventhedition 第七版
OXFIVOsTr press OXFIVOsTr 出版社

Semiconductor Devices 半導體器件

  • Semiconductor industry is one of the most important industries in Taiwan
    半導體產業是台灣最重要的產業之一
  • Related product (e.g.) 相關產品(例如)
  • computer chips (CPU, chipset, memory …)
    電腦晶片(中央處理器、晶片組、記憶體……)
  • other ICs 其他集成電路
  • communication devices 通信設備
  • MEMS 微機電系統
  • Production can be classified into 3 levels
    生產可以分為三個層次
  • electronics design 電子設計
  • semiconductor fabrication
    半導體製造
  • IC package IC 封裝
History of Semiconductor Devices
半導體器件的歷史
  • 1890s 1890 年代
  • Mechanical tabulating machine
    機械計算機
  • Herman Hollerith rarr\rightarrow IBM
    赫爾曼·霍勒里斯 rarr\rightarrow IBM
  • 1900s - 1950s 1900 年代 - 1950 年代
  • Vacuum tubes 真空管
  • 1930s 1930 年代
  • Electromechanical computers
    電機機械計算機
  • V. Bush at MIT
    V. 布什在麻省理工學院
  • 1940s 1940 年代
  • ENIAC, the first electronic computer
    ENIAC,第一台電子計算機

History of Semiconductor Devices
半導體器件的歷史

  • Dec. 23, 1947 1947 年 12 月 23 日
  • The first transfer resistor (Transistor)
    第一個轉移電阻器(晶體管)
  • Bell Laboratory (AT&T rarr\rightarrow Lucent Tech rarr\rightarrow Alcatel Lucent)
    貝爾實驗室(美國電話電報公司 rarr\rightarrow 盧森特科技 rarr\rightarrow 阿爾卡特盧森特)
  • Shockley, Bardeen, Brattin, 1956 Nobel Prize in physics
    肖克利、巴丁、布拉廷,1956 年諾貝爾物理學獎
  • Discrete devices (1950s)
    離散裝置(1950 年代)
  • one device per chip
    每個晶片一個裝置
  • transistor radios 晶體管收音機
  • Integrated Circuits (ICs)
    集成電路 (ICs)
  • appeared in 1959, J. Kilby, TI, 2000 Nobel Prize in physics
    出現在 1959 年,J. Kilby,TI,2000 年諾貝爾物理學獎
  • 5 devices in the same element
    同一元素中的五個設備
  • wire individual elements in one
    將單個元素連接在一起

History of Semiconductor Devices
半導體器件的歷史

  • Planar technology 平面技術
  • Fairchild, N. Noyce & J. Horni
    費爾查德,N. 諾伊斯 & J. 霍尼
  • The method we used today
    我們今天使用的方法
  • Development of semiconductor industry
    半導體產業的發展
  • Schockly from Bell Lab to Palo Alto
    從貝爾實驗室到帕洛阿爾托的肖克利
  • the birth of “Silicon Valley”
    “矽谷”的誕生
  • Noyce, Moore, et. al rarr\rightarrow Intel
    諾伊斯、摩爾等人 rarr\rightarrow 英特爾
  • Moore’s Law (1964) 摩爾定律(1964)
  • Density of IC will double every 18 months
    集成電路的密度每 18 個月將翻倍
First Transistor, Bell Lab, 1947
第一個晶體管,貝爾實驗室,1947 年
Photo courtesy: 照片由以下提供:
AT&T Archive AT&T 檔案
First Transistor and Its Inventors
第一個晶體管及其發明者

John Bardeen, William Shockley and Walter Brattain
約翰·巴丁、威廉·肖克利和沃爾特·布拉廷

Photo courtesy: Lucent Technologies Inc.
照片由:盧森特科技公司提供。
First IC Device Made by Jack Kilby of Texas Instrument in 1958
第一個集成電路裝置由德州儀器的傑克·基爾比於 1958 年製造

Photo courtesy: Texas Instruments
照片來源:德州儀器
First Silicon IC Chip Made by Robert Noyce of Fairchild Camera in 1961
第一個矽集成電路晶片由費爾柴德相機的羅伯特·諾伊斯於 1961 年製造

Photo courtesy: Fairchild Semiconductor International
照片來源:Fairchild Semiconductor International

Moore's Law, Intel's Version
摩爾定律,英特爾的版本

History of Semiconductor Devices
半導體器件的歷史

  • ENIAC 1947
  • size 大小
  • weight 重量
    30 × 50 ft 2 30 × 50 ft 2 30 xx50ft^(2)30 \times 50 \mathrm{ft}^{2}
  • vacuum tubes 18,000 真空管 18,000
  • resistor 電阻器
70,000
  • capacitor 電容器
10,000
  • switches 開關
6000
  • power 權力
150,000 W 150,000 瓦
  • Cost (1940) 成本 (1940)
    $400,000
  • Same function can be achieved by a 1.5 × 1.5 cm 2 1.5 × 1.5 cm 2 1.5 xx1.5cm^(2)1.5 \times 1.5 \mathrm{~cm}^{2} die in mid 1970s!
    在 1970 年代中期,可以通過一個 1.5 × 1.5 cm 2 1.5 × 1.5 cm 2 1.5 xx1.5cm^(2)1.5 \times 1.5 \mathrm{~cm}^{2} 模具實現相同的功能!

IC Industries IC 產業

  • Raw material supplier 原材料供應商
  • wafers, chemicals 晶圓,化學品
  • IC circuitry design 集成電路設計
  • Design house 設計公司
  • IC fabrication 集成電路製造
  • E.g., TSMC, UMI for fab only
    例如,台積電,僅限於晶圓廠的 UMI
  • E.g., Intel, TI, Lucent for both design and fabrication
    例如,英特爾、德州儀器、盧森特用於設計和製造。
  • Equipment suppliers of IC fabrication/characterization
    IC 製造/表徵的設備供應商
  • CVD system, lithography, CMP
    CVD 系統、光刻、化學機械平坦化
  • E.g., Applied Materials, KLA-Tencor, Nikon
    例如,應用材料公司、KLA-Tencor、尼康

Semiconductor Devices 半導體器件

  • Resistor 電阻器
  • diode 二極體
  • transistor 晶體管
  • capacitor 電容器
  • An overall idea on how a IC chip was fabricated
    IC 晶片製造的整體概念
  • Certain depth on each important fabrication step
    每個重要製造步驟的特定深度
  • The role of a non-electrical engineering background person in semiconductor industries or related research projects
    非電機工程背景的人在半導體產業或相關研究項目中的角色

Courses after this introductory material
這些入門材料之後的課程

  • Semiconductor fabrication related courses
    半導體製造相關課程
  • MEMS related courses MEMS 相關課程
  • nanosystems related courses
    納米系統相關課程
  • semiconductor processes 半導體製程

Microelectronics Devices
微電子裝置

Yao-Joe Yang 楊耀久

Outline 大綱
  • Basic semiconductor physics
    基本半導體物理學
  • Semiconductor devices 半導體裝置
  • Resistors 電阻器
  • Capacitors 電容器
  • P-N diodes P-N 二極體
  • BJT/MOSFET
  • Solid materials may be classified as follows:
    固體材料可以分類如下:
  • Amorphous 無定形
  • no ordered atomic arrangement
    無序的原子排列
  • Polycrystalline 多晶體
  • short range atomic order usually in small crystalline grains (10 Å - few μ m μ m mum\mu \mathrm{m} )
    短程原子序通常存在於小的晶粒中(10 Å - 幾個 μ m μ m mum\mu \mathrm{m}
  • Crystalline 晶體的
  • long range, ordered, atomic arrangement, repeating unit cell
    長程、有序、原子排列、重複單元格
  • All important semiconductor devices are based on crystalline materials (Si especially) because of their reproducible and predictable electrical properties
    所有重要的半導體器件都是基於晶體材料(特別是矽),因為它們具有可重複和可預測的電氣特性
Amorphous Structure 無定形結構
Polycrystalline Structure
多晶結構

Single Crystal Structure 單晶結構
  • Group IV and Group III-V compounds
    第四組和第三組-第五族化合物
  • Silicon(Si), Germanium(Ge), Gallium arsenide (GaAs)
    矽(Si)、鍺(Ge)、砷化鎵(GaAs)
  • Covalent bond, no free electrons
    共價鍵,無自由電子
  • their energy gaps ( 1 eV 1 eV ∼1eV\sim 1 \mathrm{eV} ) are not too high
    它們的能隙( 1 eV 1 eV ∼1eV\sim 1 \mathrm{eV} )並不太高
  • free electrons are generated under light and thermal agitation
    自由電子是在光和熱擾動下產生的
  • after electrons escape, “holes” are formed and can be treated as “positive” electrons
    在電子逃逸後,形成了“空穴”,可以視為“正”電子
  • these electrons and holes provides certain electrical conductivity
    這些電子和空穴提供了某種電導率
  • the conductivity becomes higher as temperature increases
    導電性隨著溫度的升高而增加

Terminology 術語

  • Intrinsic semiconductor: undoped semiconductor
    內在半導體:未摻雜半導體
  • electrical properties are native to the material
    電氣性質是材料的固有特性
  • extrinsic semiconductor: doped semiconductor
    外部半導體:摻雜半導體
  • electrical properties controlled by the added impurity
    由添加的雜質控制的電性質
  • donor 捐贈者
  • impurity atom that increases the electron concentration
    增加電子濃度的雜質原子
  • group V 群體 V
  • acceptor 受體
  • impurity atom that increases the hole concentration
    增加孔濃度的雜質原子
  • group III 第三組

Terminology 術語

  • n-type material: n 型材料:
  • semiconductor containing more electrons than holes in thermal equilibrium
    在熱平衡中,含有比孔洞更多電子的半導體
  • p-type material: p 型材料:
  • semiconductor containing more holes than electrons in therma equilibrium
    在熱平衡中,含有比電子更多孔洞的半導體
  • majority carrier: 多數載流子:
  • in n-type material: electrons
    在 n 型材料中:電子
  • in p-type material: holes
    在 p 型材料中:孔洞
  • minority carrier: 少數載流子:
  • in n-type material: holes
    在 n 型材料中:孔洞
  • in p-type material: electrons
    在 p 型材料中:電子

Intrinsic Silicon 內部矽

  • Perfect covalent bond 完美的共價鍵
  • Some bonds will be free at temperature T, create free electrons and holes
    某些鍵結在溫度 T 下會自由,產生自由電子和空穴
  • concentration of free electrons/hole is a function of temperature
    自由電子/孔的濃度是溫度的函數
n i = 3.9 × 10 16 T 3 / 2 e 0.605 eV / kT cm 3 n i ( 300 K ) = 1.5 × 10 10 cm 3 n i = 3.9 × 10 16 T 3 / 2 e 0.605 eV / kT cm 3 n i ( 300 K ) = 1.5 × 10 10 cm 3 {:[n_(i)=3.9 xx10^(16)T^(3//2)e^(-0.605eV//kT)cm^(-3)],[n_(i)(300K)=1.5 xx10^(10)cm^(-3)]:}\begin{aligned} & n_{i}=3.9 \times 10^{16} T^{3 / 2} e^{-0.605 \mathrm{eV} / \mathrm{kT}} \mathrm{~cm}^{-3} \\ & n_{i}(300 \mathrm{~K})=1.5 \times 10^{10} \mathrm{~cm}^{-3} \end{aligned}
  • law of mass action
    質量作用定律
n p = n i 2 n p = n i 2 np=n_(i)^(2)n p=n_{i}^{2}

Properties of Crystalline Silicon
晶體矽的特性

  • Crystal structure: 晶體結構:
  • diamond or double FCC 鑽石或雙面心齊晶格
    5 × 10 22 cm 3 ( 5 × 10 22 cm 3 ( -5xx10^(22)cm^(-3)(-5 \times 10^{22} \mathrm{~cm}^{-3}( density = 2.33 ) = 2.33 ) =2.33)=2.33)  5 × 10 22 cm 3 ( 5 × 10 22 cm 3 ( -5xx10^(22)cm^(-3)(-5 \times 10^{22} \mathrm{~cm}^{-3}( 密度 = 2.33 ) = 2.33 ) =2.33)=2.33)
  • Cubic structure 立方結構
  • 3 material constants 三個材料常數
  • E: 132 - 188 Gpa
  • v: 0.07 0.28 0.07 0.28 0.07-0.280.07-0.28
  • Energy gap: 1.1 eV
    能隙:1.1 eV
  • valance band to conduction band
    價帶到導帶
  • Dielectric constant: 11.7
    介電常數:11.7
  • Resistivity of pure silicon at RT = 2.3 × 10 5 Ω . cm RT = 2.3 × 10 5 Ω . cm RT=2.3 xx10^(5)Omega.cm\mathrm{RT}=2.3 \times 10^{5} \Omega . \mathrm{cm}
    純矽在 RT = 2.3 × 10 5 Ω . cm RT = 2.3 × 10 5 Ω . cm RT=2.3 xx10^(5)Omega.cm\mathrm{RT}=2.3 \times 10^{5} \Omega . \mathrm{cm} 的電阻率

Crystalline Silicon 晶體矽

  • Other mechanical properties
    其他機械性質
  • expansion coefficient 2.6 μ m / mK 2.6 μ m / mK 2.6 mum//mK2.6 \mu \mathrm{~m} / \mathrm{mK}
    擴展係數 2.6 μ m / mK 2.6 μ m / mK 2.6 mum//mK2.6 \mu \mathrm{~m} / \mathrm{mK}
  • melting point 1412 C 1412 C 1412^(@)C1412^{\circ} \mathrm{C} 熔點 1412 C 1412 C 1412^(@)C1412^{\circ} \mathrm{C}
  • fracture toughness 1 MPa m 1 MPa m ∼1MPasqrt()m\sim 1 \mathrm{MPa} \sqrt{ } \mathrm{m} 斷裂韌性 1 MPa m 1 MPa m ∼1MPasqrt()m\sim 1 \mathrm{MPa} \sqrt{ } \mathrm{m}
  • brittle-ductile transition point 550 C 550 C ∼550^(@)C\sim 550{ }^{\circ} \mathrm{C}
    脆性-延展性轉變點 550 C 550 C ∼550^(@)C\sim 550{ }^{\circ} \mathrm{C}
  • Strength strongly depends on surface quality
    強度在很大程度上依賴於表面質量
  • Poly silicon has similar elastic constant and mechanical properties as crystalline silicon. However, residual strength, toughness, and electrical properties are quite different
    多晶矽的彈性常數和機械性能與晶體矽相似。然而,殘餘強度、韌性和電氣性能卻有很大不同。

Extrinsic Semiconductors
外部半導體

  • In all important electronic devices, dopant are purposely added to control the electronic properties
    在所有重要的電子設備中,故意添加摻雜劑以控制電子特性
  • n-type semiconductor n 型半導體
  • add phosphorus or arsenic to provide excess electron carriers
    添加磷或砷以提供過量的電子載體
  • p-type semiconductor p 型半導體
  • add boron, gallium, or indium into silicon to provide additional vacancies or holes
    在矽中添加硼、鎵或銦以提供額外的空位或孔洞
  • The mass-action law is still valid
    質量作用定律仍然有效
n p = n i 2 n p = n i 2 np=n_(i)^(2)n p=n_{i}^{2}

Doping 禁藥使用

  • All semiconductor devices are fabricated LOCALLY introducing controlled number of n - and p -type dopant
    所有半導體設備都是在本地製造的,並引入受控數量的 n 型和 p 型摻雜劑

Semiconductor Conductivity
半導體導電性

  • The conductivity ( ( Ω . cm ) 1 ) ( Ω . cm ) 1 ((Omega.cm)^(-1))\left((\Omega . \mathrm{cm})^{-1}\right) is determined by the mobility and concentration of both electrons and holes
    導電率 ( ( Ω . cm ) 1 ) ( Ω . cm ) 1 ((Omega.cm)^(-1))\left((\Omega . \mathrm{cm})^{-1}\right) 由電子和空穴的遷移率及濃度決定
σ = q μ n n + q μ p p σ = q μ n n + q μ p p sigma=qmu_(n)n+qmu_(p)p\sigma=q \mu_{n} n+q \mu_{p} p
  • where μ μ mu\mu is the mobility, for silicon
    其中 μ μ mu\mu 是矽的遷移率

    μ n = 1350 cm 2 / V . s μ n = 1350 cm 2 / V . s -mu_(n)=1350cm^(2)//V.s-\mu_{\mathrm{n}}=1350 \mathrm{~cm}^{2} / \mathrm{V} . \mathrm{s}
    μ p = 480 cm 2 / V . s μ p = 480 cm 2 / V . s -mu_(p)=480cm^(2)//V.s-\mu_{p}=480 \mathrm{~cm}^{2} / \mathrm{V} . \mathrm{s}
    q = 1.609 × 10 19 C q = 1.609 × 10 19 C -q=1.609 xx10^(-19)C-\mathrm{q}=1.609 \times 10^{-19} \mathrm{C}
  • temperature decreases, conductivity increases
    溫度降低,導電性增加

Resistivity Vs. Doping Concentration
電阻率與摻雜濃度

  • Resistivity = 1/conductivity
    電阻率 = 1/導電率

Semiconductor Device Overview
半導體器件概述

  • VLSI are consisted by many transistors, capacitors, diodes, and resistors. However, the transistor fabrication can cover the other three
    VLSI 由許多晶體管、電容器、二極體和電阻器組成。然而,晶體管的製造可以涵蓋其他三者。
  • One need to know the basic definition, working principle, and fabrication routes for these basic elements
    需要了解這些基本元素的基本定義、工作原理和製造途徑

Resistors 電阻器

  • A resistor can be defined as a device in which the applied electric potential and measured current exhibit a certain relationship, i.e., V = f ( I ) V = f ( I ) V=f(I)V=f(I)
    電阻器可以定義為一種裝置,其中施加的電位和測量的電流之間顯示出某種關係,即 V = f ( I ) V = f ( I ) V=f(I)V=f(I)
  • For linear device, we have V = RI V = RI V=RI\mathrm{V}=\mathrm{RI}, where R is called the resistance of the resistor
    對於線性元件,我們有 V = RI V = RI V=RI\mathrm{V}=\mathrm{RI} ,其中 R 被稱為電阻器的電阻
  • Consider a resistor with length L L LL and crosssectional dimension W and d, R can be expressed as
    考慮一個長度為 L L LL 且橫截面尺寸為 W 和 d 的電阻器,R 可以表示為
R = ρ L W d = ρ d L W R = ρ L W d = ρ d L W R=rho(L)/(Wd)=(rho )/(d)(L)/(W)R=\rho \frac{L}{W d}=\frac{\rho}{d} \frac{L}{W}
d

Diodes 二極體

  • A diode is a device made of p-n junction
    二極體是一種由 p-n 接面製成的裝置
  • Can be used for rectification
    可以用於整治
  • Mathematical model of diodes at forward bias
    正向偏壓下二極體的數學模型
I D = I S ( e V D / η V T 1 ) V T = T 11600 I D = I S e V D / η V T 1 V T = T 11600 {:[I_(D)=I_(S)(e^(V_(D)//etaV_(T))-1)],[V_(T)=(T)/( 11600)]:}\begin{aligned} & I_{D}=I_{S}\left(e^{V_{D} / \eta V_{T}}-1\right) \\ & V_{T}=\frac{T}{11600} \end{aligned}
  • η 2 η 2 eta∼2\eta \sim 2 for silicon  η 2 η 2 eta∼2\eta \sim 2 用於矽
  • Forward bias 正向偏壓
  • reduce the junction barrier and eliminate the depletion zone
    降低接面障礙並消除耗盡區域
  • Reverse bias 反向偏壓
  • enhance the junction barrier and increase the depletion zone
    增強接面障礙並增加耗盡區域

Capacitors 電容器

  • Capacitor is a device in which the charge and electric potential can be defined, i.e., V = f ( Q ) V = f ( Q ) V=f(Q)V=f(Q).
    電容器是一種可以定義電荷和電位的裝置,即 V = f ( Q ) V = f ( Q ) V=f(Q)V=f(Q)
  • In linear element, we can express the above relationship as Q = CV Q = CV Q=CV\mathrm{Q}=\mathrm{CV}. Where C is the capacitance of the capacitor.
    在線性元件中,我們可以將上述關係表示為 Q = CV Q = CV Q=CV\mathrm{Q}=\mathrm{CV} 。其中 C 是電容器的電容。
  • For parallel plate, 對於平行板,
  • C = ε A / d C = ε A / d C=epsiA//d\mathrm{C}=\varepsilon \mathrm{A} / \mathrm{d}.
  • Where ε ε epsi\varepsilon is the dielectric constant of dielectric, A is the overlapped area and d d dd is the separation of two parallel plates.
    其中 ε ε epsi\varepsilon 是介電材料的介電常數,A 是重疊面積,而 d d dd 是兩個平行板之間的距離。

Transistors 晶體管

  • Transistors are widely used for switching and amplification
    晶體管廣泛用於開關和放大
  • replace vacuum tubes 更換真空管
  • Two major transistors 兩個主要的晶體管
  • Bipolar Junction Transistor (BJT)
    雙極接面晶體管 (BJT)
  • collector, emitter, base
    集電極、發射極、基極
  • current controlled 當前控制
  • Field Effect Transistor (FET)
    場效應晶體管 (FET)
  • source, drain, gate 源極、漏極、閘極
  • voltage controlled 電壓控制
Bipolar Junction Transistors (BJT)
雙極接面晶體管 (BJT)

Fig. 4.1 A simplified structure of the non transistor.
圖 4.1 簡化的非晶體管結構。


p型基板 p 型基板
(a) npn
23

Field Effect Transistors (FET)
場效應晶體管 (FET)

  • FET is the most popular transistor at this moment
    FET 是目前最受歡迎的晶體管
  • incorporate with MOS process
    結合 MOS 過程
  • Can be divided into 可以分為

    two catalog 兩個目錄
  • MOSFET
  • depletion 耗竭
  • enhancement 增強
  • JFET

Symbols of FET 場效應晶體管的符號

  • FETs are unipolar devices
    場效應晶體管是單極裝置
  • for switch operation, usually we use NMOS or CMOS technology to further reduce power consumption and increase the device density
    在開關操作中,通常我們使用 NMOS 或 CMOS 技術來進一步降低功耗並增加設備密度

CMOS IC CMOS 集成電路


From Basic Elements to a IC Chips
從基本元素到集成電路晶片

  • Analog 類比
  • basic devices (transistors, resistors…) to OPAMP
    基本元件(晶體管、電阻器……)到運算放大器
  • OPAMP to analog circuit
    運算放大器至類比電路
  • The designer may start from basic devices
    設計師可以從基本設備開始
  • Digital 數位
  • basic devices to basic logic elements, e.g., NAND gate
    基本設備到基本邏輯元件,例如,NAND 閘
  • from basic logic element to logic devices, e.g., FlipFlop
    從基本邏輯元件到邏輯裝置,例如,觸發器
  • from logic device to logic circuit
    從邏輯裝置到邏輯電路
  • e.g., register, memory, adder, …
    例如,寄存器、記憶體、加法器……

Fab Cost 製造成本

  • Fab cost is very high, about $ 15 B $ 15 B $15 B\$ 15 B to 20B
    晶圓廠成本非常高,大約在 $ 15 B $ 15 B $15 B\$ 15 B 到 200 億之間
  • Clean room 潔淨室
  • Equipment, usually > > >> few millions per tool
    設備,通常每台工具約 > > >> 幾百萬
  • Materials, high purity, ultra high purity
    材料,高純度,超高純度
  • Facilities 設施
  • People, training and pay
    人員、訓練與薪酬

Wafer Yield 晶圓良率

Y W = Wafers good Wafers total Y W =  Wafers  good   Wafers  total  Y_(W)=(" Wafers "_("good "))/(" Wafers "_("total "))Y_{W}=\frac{\text { Wafers }_{\text {good }}}{\text { Wafers }_{\text {total }}}
Y D = Dies good Dies total Y D =  Dies  good   Dies  total  Y_(D)=(" Dies "_("good "))/(" Dies "_("total "))Y_{D}=\frac{\text { Dies }_{\text {good }}}{\text { Dies }_{\text {total }}}

Packaging Yield 包裝產率

Y C = Chips good Chips total Y C =  Chips  good   Chips  total  Y_(C)=(" Chips "_("good "))/(" Chips "_("total "))Y_{C}=\frac{\text { Chips }_{\text {good }}}{\text { Chips }_{\text {total }}}

Overall Yield 整體產量

Y T = Y W × Y D × Y C Y T = Y W × Y D × Y C Y_(T)=Y_(W)xxY_(D)xxY_(C)Y_{T}=Y_{W} \times Y_{D} \times Y_{C}
Overall Yield determines whether a fab is making profit or losing money
整體產量決定了一個晶圓廠是否在盈利或虧損
Compare beams a and b with geometric similarity but with different absolute size: δ a / L a δ b L b = L a L b δ a / L a δ b L b = L a L b (delta_(a)//L_(a))/(delta_(b)L_(b))=(L_(a))/(L_(b))\frac{\delta_{a} / L_{a}}{\delta_{b} L_{b}}=\frac{L_{a}}{L_{b}}
比較具有幾何相似性但絕對大小不同的梁 a 和 b: δ a / L a δ b L b = L a L b δ a / L a δ b L b = L a L b (delta_(a)//L_(a))/(delta_(b)L_(b))=(L_(a))/(L_(b))\frac{\delta_{a} / L_{a}}{\delta_{b} L_{b}}=\frac{L_{a}}{L_{b}}

The beam in upper picture: 56 56 56^('')56^{\prime \prime} long, 1 / 2 1 / 2 1//2^('')1 / 2^{\prime \prime} diameter The beam in lower picture: 7 7 7^('')7^{\prime \prime} long, 1 / 16 1 / 16 1//16^('')1 / 16^{\prime \prime} diameter (same material, same aspect ratio – isometry)
上圖中的梁: 56 56 56^('')56^{\prime \prime} 長, 1 / 2 1 / 2 1//2^('')1 / 2^{\prime \prime} 直徑 下圖中的梁: 7 7 7^('')7^{\prime \prime} 長, 1 / 16 1 / 16 1//16^('')1 / 16^{\prime \prime} 直徑(相同材料,相同長寬比 - 等距)
The size difference in the example is 8 times.
範例中的大小差異為 8 倍。

The relative deformation of a 300 μ m 300 μ m 300 mum300 \mu \mathrm{~m}-long beam (typical size for microbeams) would be 1/5000 that of the 56" long beam.
一根長度為 300 μ m 300 μ m 300 mum300 \mu \mathrm{~m} 的梁(微梁的典型尺寸)的相對變形將是 56 英寸長的梁的 1/5000。

=> In microscale, structures appear stiffer against inertia forces.
在微觀尺度上,結構對慣性力顯得更為剛性。

Inertia force is generally insignificant for micro-devices.
慣性力對於微型裝置通常是微不足道的。

(proof-mass for accelerometers; strong against shock)
(加速度計的質量證明;抗震性強)
Long microbeams suspended over silicon wafer by only 1-2 μ m μ m mum\mu \mathrm{m} (typical surface-micromachined devices) do not sag to touch the surface:
長微束僅以 1-2 μ m μ m mum\mu \mathrm{m} 懸浮於矽晶圓上(典型的表面微機械裝置)不會下垂觸及表面:

Resonant microstructure (Tang et al, Sensors and Actuators '89)
共振微結構(唐等,傳感器與執行器 '89)

On-wafer microgripper (Kim et al., J.MEMS '92)
晶圓上微型夾具(Kim et al., J.MEMS '92)

What is suspended structures
懸掛結構是什麼

Locomotion 運動學

e.g. blue whale swims at Re 10 8 Re 10 8 Re∼10^(8)\operatorname{Re} \sim 10^{8} large fish swims at Re 10 5 Re 10 5 Re∼10^(5)\operatorname{Re} \sim 10^{5}
例如,藍鯨在 Re 10 8 Re 10 8 Re∼10^(8)\operatorname{Re} \sim 10^{8} 游泳,大魚在 Re 10 5 Re 10 5 Re∼10^(5)\operatorname{Re} \sim 10^{5} 游泳。

large bird flies at Re 10 4 Re 10 4 Re∼10^(4)\operatorname{Re} \sim 10^{4}
大型鳥類在 Re 10 4 Re 10 4 Re∼10^(4)\operatorname{Re} \sim 10^{4} 飛行

bacteria swims at Re 10 6 Re 10 6 Re∼10^(-6)\operatorname{Re} \sim 10^{-6}
細菌在 Re 10 6 Re 10 6 Re∼10^(-6)\operatorname{Re} \sim 10^{-6} 游泳

(based on its length and speed)
(根據其長度和速度)

World lifting records 世界舉重紀錄


Common nails produced 普通釘的生產
Crystal Growth 晶體生長

Semiconductor Materials 半導體材料

  • Single crystal 單晶
    > > >> will be discussed in this section
    本節將討論 > > >>

    > > >> no grain boundary  > > >> 無晶界
    > > >> almost all atoms occupy well defined positions
    幾乎所有原子都佔據明確的位置

    > > >> E.g., substrate of Si and GaAs
    例如,矽和砷化鎵的基材
  • Amorphous 無定形
    > > >> no long range order
    > > >> 無長程有序

    > > >> E.g., Oxide 例如,氧化物
  • Polycrystalline 多晶體
    > > >> small single crystal randomly oriented
    > > >> 小型單晶隨機取向

    > > >> E.g., CVD Silicon 例如,CVD 矽

Crystal structure 晶體結構

  • Body centered cube (BCC)
    體心立方晶格 (BCC)
  • Face centered cube (FCC)
    面心立方體 (FCC)
  • Diamond structure : Si crystal
    鑽石結構:矽晶體

Diamond structure 鑽石結構
Simple cube 簡單立方體
Body centered cube Face centered cube
體心立方體 面心立方體

Tetrahedral bonding of silicon atoms
矽原子的四面體鍵合

Crystallography 結晶學

  • The Miller index 米勒指數
  • Mechanical properties of silicon is orientation dependent
    矽的機械性質依賴於取向


100
111
Miller Indices 米勒指數

Crystal Growth 晶體生長

  • 98% of total devices use single crystal Si
    98% 的總設備使用單晶矽
  • CZ Growth (Czochralski Growth)
    CZ 生長(Czochralski 生長)

    > 85 % > 85 % > 85%>85 \% of total semiconductor product
    > 85 % > 85 % > 85%>85 \% 的總半導體產品

    > > >> DRAM 、SRAM 、ASIC  > > >> 動態隨機存取記憶體 (DRAM)、靜態隨機存取記憶體 (SRAM)、應用特定積體電路 (ASIC)
    > > >> Large size wafer (ingot)
    大型晶圓(單晶棒)
  • FZ Growth (Float Zone Growth)
    FZ 成長(浮區成長)

    > > >> for extremely high purity wafer
    > > >> 用於極高純度的晶圓

    > 15 % > 15 % > 15%>15 \% of total semiconductor product
    > 15 % > 15 % > 15%>15 \% 的總半導體產品

    > > >> High power devices 高功率裝置

Czochralski Growth Czochralski 生長

  • The most important fabrication process to grow single crystal silicon substrate
    生長單晶矽基板的最重要製造過程
  • Pre-process 前處理
    > > >> Starting from raw material to form metallurgical-grade Si
    從原材料開始形成冶金級矽
  • SiO 2 + 2 C ( 2000 C ) Si + 2 CO SiO 2 + 2 C 2000 C Si + 2 CO SiO_(2)+2Crarr(2000^(@)C)Si+2COuarr\mathrm{SiO}_{2}+2 \mathrm{C} \rightarrow\left(2000^{\circ} \mathrm{C}\right) \mathrm{Si}+2 \mathrm{CO} \uparrow
    > > >> Metallurgical-grade Si to form Trichlorosilane (gas)
    冶金級矽形成三氯矽烷(氣體)
  • Si + nHCl ( 300 C ) SiHCl 3 + MCl x Si + nHCl 300 C SiHCl 3 + MCl x Si+nHClrarr(300^(@)C)SiHCl_(3)+MCl_(x)\mathrm{Si}+\mathrm{nHCl} \rightarrow\left(300^{\circ} \mathrm{C}\right) \mathrm{SiHCl}_{3}+\mathrm{MCl}_{\mathrm{x}}
    > > >> Trichlorosilane to form polysilicon
    三氯硅烷形成多晶矽
  • 2 SiHCl 3 + 2 H 2 2 Si + 6 HCl 2 SiHCl 3 + 2 H 2 2 Si + 6 HCl 2SiHCl_(3)+2H_(2)rarr2Si+6HCl2 \mathrm{SiHCl}_{3}+2 \mathrm{H}_{2} \rightarrow 2 \mathrm{Si}+6 \mathrm{HCl}
    > > >> Ready for CZ growth
    > > >> 準備好迎接 CZ 增長

Crystal Pulling: CZ method
晶體拉拔:CZ 方法

Graphite Crucible 石墨坩埚
Single Crystal Silicon Seed
單晶矽種子

Quartz Crucible 石英坩埚
<敇 
Single Crystal silicon Ingot
單晶矽錠

Czochralski Growth Czochralski 生長

  • Polysilicon were melted within a crucible
    多晶矽在坩埚內熔化
  • A seed was then introduced into melted silicon
    一顆種子隨後被引入熔融矽中
  • The seed were then rotated and pulled up with carefully control to reduced the thermal gradients
    種子隨後被旋轉並小心地拉起,以減少熱梯度
  • Large diameter silicon ingot can be fabricated by this method
    這種方法可以製造大直徑的矽單晶圓
  • Dislocation free silicon
    無位錯矽
  • Major impurity in CZ silicon is oxygen
    CZ 矽中的主要雜質是氧

    > > >> mainly from crucible
    > > >> 主要來自熔爐

Czochralski Growth Sequence
Czochralski 生長序列

CZ Crystal Pulling CZ 晶體拉拔

Source: http://www.fullman.com/semiconductors/_crystalgrowing.htm
來源:http://www.fullman.com/semiconductors/_crystalgrowing.htm

Czochralski Growth Equipment
Czochralski 生長設備

CZ Silicon Ingots CZ 矽晶圓
Float Zone Growth 浮區生長
  • For extremely high purity of silicon
    對於極高純度的矽

    > > >> carrier concentration can be 3 order of magnitude lower than that grown by CZ method
    > > >> 載流子濃度可以比通過 CZ 方法生長的低三個數量級
  • power devices, devices for terahertz applications or detector applications
    功率裝置、太赫茲應用裝置或探測器應用裝置

    > > >> no crucible (for oxygen)
    > > >> 無熔爐(用於氧氣)
  • Difficulty of introducing a uniform concentration of dopant
    引入均勻濃度摻雜物的難度

    > > >> core doping: use doped polysilicon
    > > >> 核心摻雜:使用摻雜多晶矽

    > > >> pill doping:  > > >> 藥丸興奮劑:
    > > >> gas doping: dopant gases were injected into melten ring
    > > >> 氣體摻雜:摻雜氣體被注入熔融環中

    > > >> neutron doping:  > > >> 中子摻雜:
Floating Zone Method 浮區法

Comparison of the Two Methods
兩種方法的比較

  • CZ method is more popular
    CZ 方法更受歡迎

    > > >> Cheaper  > > >> 更便宜
    > > >> Larger wafer size (300 mm in production)
    > > >> 更大的晶圓尺寸(300 毫米在生產中)

    > > >> Reusable materials 可重複使用的材料
  • Floating Zone 浮動區域
    > > >> Pure silicon crystal (no crucible)
    > > >> 純矽晶體(無坩埚)

    > > >> More expensive, smaller wafer size ( 150 mm )
    更昂貴,晶圓尺寸較小(150 毫米)

    > > >> Mainly for power devices.
    主要用於功率設備。

Wafering 晶圓切割

  • Ingot inspection: undersize, wrong resistivity, wrong orientation, 50 % 50 % ∼50%\sim 50 \% rejected
    鋼錠檢查:尺寸不足、電阻率錯誤、方向錯誤, 50 % 50 % ∼50%\sim 50 \% 被拒絕
  • Shaping of ingot: make it round
    鑄錠成形:使其圓形
  • Introducing flats: major or minor flat
    引入降音:大降音或小降音
  • Sawing: to form wafers
    鋸切:形成晶圓
  • Laser marked: wafer ID
    雷射標記:晶圓識別碼
  • Lapping/ grinding: right thickness
    磨削/研磨:適當的厚度
  • Shaping edge: smooth edge
    成形邊緣:平滑邊緣
  • Chemical-Mechanical polishing: smooth surface Another 50% material were lost during wafering
    化學機械拋光:光滑表面 在晶圓加工過程中又損失了 50%的材料


    C) CHECK CHARACTERS C) 檢查字符

Ingot Polishing, Flat, or Notch
錠材拋光、平面或缺口

Flat, 150 mm and smaller
平面,150 毫米及以下

Notch, 200 mm and larger
凹槽,200 毫米及以上

Wafer Orientation 晶圓取向

  • Major flat 主要平面
    > > >> indicate the (110) direction
    > > >> 表示 (110) 方向
  • Minor flat 小平面
    > > >> combining with major flat to determine the wafer and doping type
    > > >> 結合主要平面以確定晶圓和摻雜類型

Orientation flat 方向平面
(110) plane (110) 平面

Orientation flat on (110) plane
在 (110) 平面上的取向平坦

Oxygen in Silicon 矽中的氧

  • Can be as high as 10 18 cm 3 10 18 cm 3 10^(18)cm^(-3)10^{18} \mathrm{~cm}^{-3} in CZ silicon
    在 CZ 矽中可以高達 10 18 cm 3 10 18 cm 3 10^(18)cm^(-3)10^{18} \mathrm{~cm}^{-3}

    > > >> come from crucible erosion
    > > >> 來自熔爐侵蝕
  • Problem of oxygen in silicon
    矽中的氧問題

    > > >> quality of thin gate oxide
    > > >> 薄閘氧化層的品質

    > > >> may cause device failure by excessive leakage current
    > > >> 可能因過度漏電流而導致設備故障
  • Gate oxide quality 閘極氧化層質量
    > > >> the most important issue to control the device performance
    > > >> 控制裝置性能的最重要問題

    > > >> oxide leakage current
    > > >> 氧化物漏電流

    > > >> breakdown voltage  > > >> 突穿電壓
  • both can be degradation by contamination
    兩者都可以因污染而降解

Part 4:
Overview of Wafer Fabrication
第四部分:晶圓製造概述

Yao-Joe Yang 楊耀久

Basic Wafer Fabrication Operations
基本晶圓製造操作

  • Layering rarr\rightarrow Part 6, Part 7
    分層 rarr\rightarrow 第 6 部分,第 7 部分

    > > >> form thin layer/film structures
    > > >> 形成薄層/薄膜結構
  • oxidation, CVD, sputtering, epitaxy …
    氧化、化學氣相沉積、濺射、外延 …
  • Patterning (pattern transfer) rarr\rightarrow Part 5
    圖案化(圖案轉移) rarr\rightarrow 第五部分

    > > >> trim layer/film to desired device size
    > > >> 修剪層/薄膜至所需的設備大小
  • lithography, etching … 平版印刷,蝕刻 …
  • Doping rarr\rightarrow Part 8 禁藥 rarr\rightarrow 第 8 部分
    > > >> adjust layer/film/substrate electrical properties
    > > >> 調整層/薄膜/基材的電性質
  • ion implementation, diffusion
    離子實施,擴散
  • Heat treatment rarr\rightarrow Part 8
    熱處理 rarr\rightarrow 第 8 部分

    > > >> partially recover the damage after certain processes
    > > >> 在某些過程後部分恢復損害
  • RTP (rapid thermal process), annealing
    RTP(快速熱處理),退火

Layering 分層

  • Adding (uniform) thin layers to wafer surfaces
    在晶圓表面添加(均勻)薄層
  • Methods 方法
    > > >> Growing:  > > >> 成長:
  • oxidation (grow silicon oxide: SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} )
    氧化(生長矽氧化物: SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2}
  • nitridation (grow silicon nitride: Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} )
    氮化(生長氮化矽: Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4}

    > > >> Deposition  > > >> 沉積
  • epitaxy 外延生長
  • chemical vapor deposition
    化學氣相沉積
  • physical vapor deposition
    物理氣相沉積

Patterning 圖案化

  • A series of steps that remove unwanted patterns from substrate surface layers
    一系列去除基材表面層中不需要圖案的步驟

    > > >> Patterns are defined by photo-masks
    > > >> 圖案由光罩定義
Also known as: Photomasking, masking, lithography, photo-lithography, μ μ mu\mu-lithography
也稱為:光掩模、掩模、光刻、光刻技術、 μ μ mu\mu -刻蝕

Doping 禁藥使用

  • Implant specific amount dopant in wafers
    在晶圓中植入特定量的摻雜劑

    > > >> modify electrical/mechanical properties of the material
    > > >> 修改材料的電氣/機械性質
  • ion implantation or thermal diffusion
    離子植入或熱擴散

    > > >> ion implantation  > > >> 離子植入
    *\cdot room temperature physical “bombardment” process > > >> thermal diffusion
    *\cdot 室溫物理“轟擊”過程 > > >> 熱擴散
  • high temperature process
    高溫過程
  • purpose 目的
    > > >> create either n- or p-type pockets in semiconductor
    > > >> 在半導體中創建 n 型或 p 型孔

Heat Treatment 熱處理

  • Operations in which the wafer is simply heated & cooled to achieve specific results
    操作中,晶圓僅被加熱和冷卻以達成特定結果

    > > >> e.g., annealing after ion implantation
    例如,離子植入後的退火

    > > >> e.g., annealing of PECVD oxide
    例如,PECVD 氧化物的退火
  • From ME point of view
    從我的角度來看

    > > >> Definition of fundamental steps: Layering and Etching
    基本步驟的定義:分層與蝕刻
  • Layering: a material being deposited (added) on a structure
    分層:在結構上沉積(添加)材料
  • Etching: a material being etched (removed) by an etchant
    蝕刻:一種被蝕刻劑蝕刻(去除)的材料
  • Etching must come with an Etching Mask (otherwise, nonsense)
    蝕刻必須配有蝕刻面具(否則,毫無意義)
  • Etching masks prevent material from being etched by etchants.
    蝕刻掩模防止材料被蝕刻劑蝕刻。
  • Etching masks are usually “defined” by photo-masks using lithography techniques.
    蝕刻掩模通常是通過使用光刻技術的光掩模來“定義”的。

    > > >> Lithography is a combination of many steps.
    光刻是一個由多個步驟組成的過程。

    > > >> Patterning rarr\rightarrow Lithography + Etching
    > > >> 圖案化 rarr\rightarrow 光刻 + 蝕刻
  • Summary: Layering and Patterning rarr\rightarrow create 3D micro structures
    摘要:分層和圖案化 rarr\rightarrow 創造 3D 微結構

Etching (with mask) 蝕刻(使用掩模)

  • Layer 1 is etched by an etchant
    第一層由蝕刻劑蝕刻而成
  • Pattern is defined by photo-mask (etching mask is not shown)
    圖案由光罩定義(蝕刻掩模未顯示)

Layering 分層

  • Three types of Layering (deposition or growing):
    三種層疊(沉積或生長)方式:
  • Conformal 共形
  • Planar 平面
  • Stack (not traditional IC process)
    堆疊(非傳統集成電路製程)

Conformal 共形

Planar 平面

Stack 堆疊
(not traditional IC process)
(非傳統集成電路製程)

Part 5:
Pattern Transfer (Patterning)
第五部分:圖案轉移(圖案化)

Yao-Joe Yang 楊耀久

Patterning 圖案化

  • Patterns transferred from photo-masks to thin-films on a planar substrate via lithographic process
    通過光刻工藝將圖案從光罩轉移到平面基板上的薄膜上
  • Step 1: 步驟 1:
Transfer patterns of photo-masks to photoresist (etching-mask) by lithography techniques,
通過光刻技術將光掩模的轉移圖案到光刻膠(蝕刻掩模)上,
  • Step 2: 步驟二:
Use etchants to etch unwanted portion of material defined by etching-masks.
使用蝕刻劑蝕刻由蝕刻掩模定義的材料中不需要的部分。

Example 2: 範例 2:
Patterning 圖案化
Example 2: 範例 2:
Starting Material 起始材料
Example 2: 範例 2:
Spin-coating PR 旋轉塗佈光敏樹脂

Example 2: 範例 2:
Gate Mask Exposure 閘門遮罩曝光
Example 2: 範例 2:
Development 發展
Example 2: 範例 2:
Etch Polysilicon (not finished yet)
刻蝕多晶矽(尚未完成)


Example 2: 範例 2:
Strip Photoresist 去除光阻

Patterning 圖案化

  • Summary of a typical patterning procedure
    典型圖案化程序的摘要
  • Spin coating photoresist (PR) on a wafer
    在晶圓上旋塗光刻膠(PR)
  • Mask alignment with the wafer using an aligner
    使用對準機將掩模與晶圓對準
  • Exposure of PR PR 的暴露
  • Development (remove unwanted PR)
    發展(移除不必要的公關)
  • With the remained PR as etching masks, etch the wafer
    利用剩餘的光刻膠作為蝕刻掩模,對晶圓進行蝕刻
  • Striping the remaining PR from the wafer
    去除晶圓上剩餘的光阻

Part 5-1: 第五部分-1:

Lithography 石版印刷

Pattern Transfer (Patterning)
圖案轉移(圖案化)

Types of lithography systems:
光刻系統的類型:
  • Optical 光學
  • X-ray X 光
  • electron beam writer (non-traditional, no masks)
    電子束寫入器(非傳統,無掩模)
Two-dimensional pattern transfer:
二維圖案轉移:
  • limited tolerance for non-planar topography on wafer
    對晶圓上非平面地形的容忍度有限
2-D pattern transfer imposes constraints on process design
二維圖案轉移對工藝設計施加了限制

The position control of the lithography systems need 10 times better than the achieved electronic resolution level.
光刻系統的定位控制需要比實現的電子解析度水平好十倍。

rarr\rightarrow semiconductor industry strongly depends on precision machine design.
rarr\rightarrow 半導體產業強烈依賴精密機械設計。

Lithography Basic Steps 光刻基本步驟

  • Wafer clean 晶圓清洗
  • Dehydration bake 脫水烘焙
  • Spin coating primer and PR
    旋轉塗佈底漆和光刻膠
  • Soft bake 軟烘焙
  • Alignment and exposure 對齊與曝光
  • Development 發展
  • Pattern inspection 圖樣檢查
  • Hard bake 硬烘焙
PR coating J PR 塗層 J
Development 發展

Optical Lithography 光學光刻術

- Optical Lithography - 光學微影技術

Photo-masks 光罩
  • Interface between designers and devices
    設計師與設備之間的介面
  • Designers layout design (mask) on computers (2D patterns)
    設計師在電腦上進行佈局設計(掩模)(2D 圖案)
  • photo-masks 光罩
  • Photo-masks: opaque patterns (chromium) on transparent glass (fused silica)
    光罩:透明玻璃(熔融二氧化矽)上的不透明圖案(鉻)
Masks 面具

Photoresist 光阻

- Photoresist (PR) 光阻 (PR)

Optical resists: photosensitive polymers
光學抗蝕劑:光敏聚合物

> PR > PR > PR>\mathrm{PR} is coated on the whole substrate surface using spincoater
> PR > PR > PR>\mathrm{PR} 使用旋轉塗佈機均勻塗覆於整個基材表面

Positive PR: 正面公關:
  • can be removed by specific solution if it is exposed
    如果暴露在特定溶液中,可以被去除
  • most popular for IC process
    最受歡迎的集成電路製程
  • preferred for the pattern in which removed area < reserved area
    偏好於移除區域 < 保留區域的模式
Negative PR: 負面公關:
  • can be removed by specific
    可以被特定移除

    solution if it is NOT exposed
    解決方案如果未被暴露


    exposure 暴露
DEVELOPED 發展中
not good for feature size < 3 um
不適用於特徵尺寸 < 3 微米
  • preferred for the pattern in which
    偏好於該模式中

    removed area > reserved area
    移除區域 > 保留區域

Photoresist Spin Coating
光阻旋塗

Photoresist Spin Coating
光阻旋塗

To vacuum 抽真空
pump 
Coater / HMDS 塗佈機 / HMDS

Coating of Photoresists 光刻膠的塗佈

  • Spinning coating 旋轉塗層
    > > >> Final thickness of photoresist is a function of rotating speed.
    光刻膠的最終厚度是旋轉速度的函數。

    Thickness 1 ω 1 ω prop(1)/(sqrtomega)\propto \frac{1}{\sqrt{\omega}} 厚度 1 ω 1 ω prop(1)/(sqrtomega)\propto \frac{1}{\sqrt{\omega}}
    > > >> Relationship has been calibrated and formed a look up table
    > > >> 關係已經被校準並形成了一個查詢表

Photoresist Baking 光刻膠烘烤

  • Pre-bake (soft-bake) 預烤(軟烤)
    > > >> After PR coating, before exposure
    在光刻膠塗佈後,曝光之前

    > > >> Removing residual solvent and increasing adhesion
    去除殘留溶劑並增加附著力

    > > >> e.g., 90 120 C 90 120 C 90^(@)-120^(@)C90^{\circ}-120^{\circ} \mathrm{C} for 1 min ( 1 min ( 1min(1 \mathrm{~min}( hot plate) 30 min 30 min ∼30min\sim 30 \mathrm{~min} (oven)
    > > >> 例如, 90 120 C 90 120 C 90^(@)-120^(@)C90^{\circ}-120^{\circ} \mathrm{C} 用於 1 min ( 1 min ( 1min(1 \mathrm{~min}( 熱板) 30 min 30 min ∼30min\sim 30 \mathrm{~min} (烤箱)
  • Post-exposure bake 後曝光烘烤
    > > >> After exposure, before developing
    > > >> 曝光後,發展之前
  • Hard-bake 硬烘
    > > >> After PR developing
    > > >> 在公關發展之後

    > > >> Further reduce the solvent concentration
    進一步降低溶劑濃度

    > > >> Increase resistance to etchant and ions. I.e., selectivity
    > > >> 增加對蝕刻劑和離子的抵抗力。即,選擇性

    > > >> e.g., 100 130 C 100 130 C 100^(@)-130^(@)C100^{\circ}-130^{\circ} \mathrm{C} for 2 min ( 2 min ( 2min(2 \mathrm{~min}( hot plate) 30 min 30 min ∼30min\sim 30 \mathrm{~min} (oven)
    > > >> 例如, 100 130 C 100 130 C 100^(@)-130^(@)C100^{\circ}-130^{\circ} \mathrm{C} 用於 2 min ( 2 min ( 2min(2 \mathrm{~min}( 熱板) 30 min 30 min ∼30min\sim 30 \mathrm{~min} (烤箱)

Photoresist Removing 光阻去除

  • After exposure, PR is usually removed in NaOH or KOH based solution
    在曝光後,光阻通常在氫氧化鈉或氫氧化鉀的溶液中去除
  • PR stripping PR 剝離
    > > >> After etching, we need to remove PR.
    在蝕刻後,我們需要去除光刻膠。
  • Organic stripper (phenol-based)
    有機剝離劑(基於酚類)
  • Oxidizing-type stripper ( H 2 O 2 ) H 2 O 2 (H_(2)O_(2))\left(\mathrm{H}_{2} \mathrm{O}_{2}\right)
    氧化型剝離劑 ( H 2 O 2 ) H 2 O 2 (H_(2)O_(2))\left(\mathrm{H}_{2} \mathrm{O}_{2}\right)
  • Oxide plasma 氧化物等離子體

Aligners 隱形矯正器

  • Alignment and exposure systems
    對齊與曝光系統
A microscopic system which:
一個微觀系統,該系統:
  • Align the photo-mask and the substrate
    對準光罩和基板
  • Expose PR 暴露公關
Also called: 也稱為:
  • Printers or scanners 印表機或掃描器
    > > >> Contact printer  > > >> 聯絡印刷機
  • High resolution ( 1 μ m 1 μ m <= 1mum\leq 1 \mu \mathrm{~m} )
    高解析度 ( 1 μ m 1 μ m <= 1mum\leq 1 \mu \mathrm{~m} )
  • Mask deterioration 面具劣化
Proximity printer 近距離印表機
  • 10 - 25 μ m 25 μ m 25 mum25 \mu \mathrm{~m} gap rarr\rightarrow longer mask life
    10 - 25 μ m 25 μ m 25 mum25 \mu \mathrm{~m} 間隙 rarr\rightarrow 更長的口罩壽命
  • Diffraction effect 2 2 rarr2\rightarrow 2 - 4 μ m 4 μ m 4mum4 \mu \mathrm{~m} resolution
    衍射效應 2 2 rarr2\rightarrow 2 - 4 μ m 4 μ m 4mum4 \mu \mathrm{~m} 解析度
Projection printer 投影印表機
  • Image of mask usually reduced
    面具的影像通常會被縮小
  • Scanning or stepping of small field ( 1cm)
    小範圍掃描或步進(1 公分)
  • VLSI standard ( 0.25 μ m 0.25 μ m 0.25 mum0.25 \mu \mathrm{~m} possible with deepUV source)
    VLSI 標準( 0.25 μ m 0.25 μ m 0.25 mum0.25 \mu \mathrm{~m} 可能與深紫外光源一起使用)

Alignment and Exposure Tools
對齊與曝光工具

  • Contact printer 接觸式印刷機
  • Proximity printer 近距離印表機
  • Projection printer 投影印表機
  • Stepper/Scanner 步進器/掃描器

Contact Printer 接觸式印刷機

  • Simple equipment 簡單設備
  • Use before mid-70s 在 70 年代中期之前使用
  • Resolution: capable for sub-micron
    解析度:能夠達到亞微米級
  • Direct mask-wafer contact, limited mask lifetime
    直接掩模-晶圓接觸,有限的掩模壽命
  • Particles 粒子

Contact Printer 接觸式印刷機

Contact Printing 接觸印刷

Proximity Printer 近距離印表機

  • 10 μ m 10 μ m ∼10 mum\sim 10 \mu \mathrm{~m} from wafer surface  10 μ m 10 μ m ∼10 mum\sim 10 \mu \mathrm{~m} 從晶圓表面
  • No direct contact 無直接接觸
  • Longer mask lifetime 更長的口罩壽命
  • Resolution: > 3 μ m 3 μ m 3mum3 \mu \mathrm{~m} 解析度:> 3 μ m 3 μ m 3mum3 \mu \mathrm{~m}
Proximity Printer 近距離印表機
Proximity Printing 近距離印刷
  • Works like an overhead projector
    像投影機的作品
  • Mask to wafer, 1:1
    掩模至晶圓,1:1
  • Resolution to about 1 μ m 1 μ m 1mum1 \mu \mathrm{~m}
    關於 1 μ m 1 μ m 1mum1 \mu \mathrm{~m} 的解決方案

Projection System 投影系統

Scanning Projection System
掃描投影系統

Stepper 步進器

  • Most popular used photolithography tool in the advanced IC fabs for high-throughput production
    在高通量生產的先進集成電路製造廠中,最常用的光刻工具
  • Reduction of image gives high resolution
    影像縮小可提高解析度
  • Sub-micron and beyond 亞微米及更小尺寸
  • Very expensive 非常昂貴
Step-&-Repeat Alignment/Exposure
步進重複對準/曝光

Step&Repeat Alignment System
步進重複對準系統

Lithography 石版印刷
Karl Suss Contact Aligner
卡爾·蘇斯接觸式對準機


stepper 步進器

DUV 深紫外線 (DUV)


Exposure Light Source 曝光光源

  • Short wavelength 短波長
  • High intensity 高強度
  • Stable 穩定
  • High-pressure mercury lamp
    高壓汞燈
  • Excimer laser 氦氖激光
Photolithography Light Sources
光刻光源
Name 名稱 Wavelength (nm) 波長(納米)

應用特徵尺寸 ( μ m ) ( μ m ) (mu m)(\boldsymbol{\mu m})
Application
feature size ( μ m ) ( μ m ) (mu m)(\boldsymbol{\mu m})
Application feature size (mu m)| Application | | :---: | | feature size $(\boldsymbol{\mu m})$ |
Mercury Lamp 汞燈 G-line G 線 436 0.50
H-line H 線 405
I-line I 線 365 0.35 to 0.25 0.35 到 0.25
Excimer Laser 準分子激光 XeF 351
XeCl 308
KrF ( DUV ) KrF ( DUV ) KrF(DUV)\mathrm{KrF}(\mathrm{DUV}) 248 0.25 to 0.080 0.25 到 0.080
ArF ( DUV ) ArF ( DUV ) ArF(DUV)\mathrm{ArF}(\mathrm{DUV}) 193 0.18 to 0.038 0.18 到 0.038
CO 2 CO 2 CO_(2)\mathrm{CO}_{2} Laser +Sn  CO 2 CO 2 CO_(2)\mathrm{CO}_{2} 雷射 +Sn EUV 13.5 < 0.014 < 0.014 < 0.014<0.014
Name Wavelength (nm) "Application feature size (mu m)" Mercury Lamp G-line 436 0.50 H-line 405 I-line 365 0.35 to 0.25 Excimer Laser XeF 351 XeCl 308 KrF(DUV) 248 0.25 to 0.080 ArF(DUV) 193 0.18 to 0.038 CO_(2) Laser +Sn EUV 13.5 < 0.014| | Name | Wavelength (nm) | Application <br> feature size $(\boldsymbol{\mu m})$ | | :---: | :---: | :---: | :---: | | Mercury Lamp | G-line | 436 | 0.50 | | | H-line | 405 | | | | I-line | 365 | 0.35 to 0.25 | | Excimer Laser | XeF | 351 | | | | XeCl | 308 | | | | $\mathrm{KrF}(\mathrm{DUV})$ | 248 | 0.25 to 0.080 | | | $\mathrm{ArF}(\mathrm{DUV})$ | 193 | 0.18 to 0.038 | | $\mathrm{CO}_{2}$ Laser +Sn | EUV | 13.5 | $<0.014$ |
Part 5-2: 第五部分-2:
Etching 蝕刻

Introduction to Etching 蝕刻入門

  • Etching is a process to selectively remove materials using chemical reactions
    蝕刻是一種通過化學反應選擇性去除材料的過程

    > > >> Wet and Dry  > > >> 濕與乾
  • Classified by chemical reaction
    根據化學反應分類

    > > >> Isotropic and anisotropic
    各向同性與各向異性
  • Classified by topology 根據拓撲分類
  • Etching is usually involved in the lithography cycle as a major step
    蝕刻通常作為平版印刷過程中的一個主要步驟

Performance Index 績效指標

  • Etch rate 蝕刻速率
    > > >> Usually represented as μ m / min μ m / min mum//min\mu \mathrm{m} / \mathrm{min}
    > > >> 通常表示為 μ m / min μ m / min mum//min\mu \mathrm{m} / \mathrm{min}
  • Selectivity 選擇性
    > > >> defined as the ratio between the etch rate of two materials subject to a particular etchant. Especially one is the thin film (or substrate); the other one is the mask material.
    > > >> 定義為在特定蝕刻劑作用下,兩種材料的蝕刻速率之比。特別是其中一種是薄膜(或基材);另一種是掩模材料。

    > > >> High selectivity is desired
    高選擇性是所期望的
  • Aspect ratio 長寬比
    > > >> Degree of anisotropy
    各向異性程度
  • Uniformity 均勻性

Wet Etching 濕蝕刻

  • Remove materials by wet chemistry
    通過濕化學去除材料
  • Basic mechanisms 基本機制
    > > >> Reactant transport to surface
    反應物運輸至表面
  • Surface reaction 表面反應
    > > >> Reaction product removal from surface
    > > >> 反應產物從表面去除
  • Advantages 優勢
    > > >> High selectivity and inexpensive
    高選擇性且價格低廉
  • Disadvantages 劣勢
Isotropic, loss of resolution through undercut
各向同性,因切割而導致的解析度損失

Temperature/agitation sensitivity
溫度/攪動敏感性

> > >> Surface tension, bubble formation, wetting, solution degradation
表面張力、氣泡形成、潤濕、溶液降解

Waste disposal 廢物處理
  • Replaced by dry etching (plasma etching) after 1980 in IC process
    在 1980 年後,IC 製程中被乾蝕刻(等離子體蝕刻)取代

Wet Oxide Etch 濕氧化物蝕刻

  • Typical reaction formula
    典型反應公式
SiO 2 ( s ) + 6 HF ( aq ) H 2 ( g ) + SiF 6 ( g ) + 2 H 2 O ( 1 ) SiO 2 ( s ) + 6 HF ( aq ) H 2 ( g ) + SiF 6 ( g ) + 2 H 2 O ( 1 ) SiO_(2(s))+6HF_((aq))rarrH_(2(g))+SiF_(6(g))+2H_(2)O_((1))\mathrm{SiO}_{2(\mathrm{~s})}+6 \mathrm{HF}_{(\mathrm{aq})} \rightarrow \mathrm{H}_{2(\mathrm{~g})}+\mathrm{SiF}_{6(\mathrm{~g})}+2 \mathrm{H}_{2} \mathrm{O}_{(1)}
  • NH 4 F NH 4 F NH_(4)F\mathrm{NH}_{4} \mathrm{~F} is usually added into HF as the buffer agent. We called buffered oxide etch (BOE)
    NH 4 F NH 4 F NH_(4)F\mathrm{NH}_{4} \mathrm{~F} 通常被添加到氫氟酸中作為緩衝劑。我們稱之為緩衝氧化物蝕刻 (BOE)。
  • Etch rate is 0.5 μ m / min 0.5 μ m / min ∼0.5 mum//min\sim 0.5 \mu \mathrm{~m} / \mathrm{min}. Depends on temperature, concentration, and type of oxide
    蝕刻速率為 0.5 μ m / min 0.5 μ m / min ∼0.5 mum//min\sim 0.5 \mu \mathrm{~m} / \mathrm{min} 。取決於溫度、濃度和氧化物的類型。

    > > >> Dry oxide has lowest etch rate
    > > >> 干氧化物的蝕刻速率最低

    > > >> CVD oxide has much high etch rate
    CVD 氧化物的蝕刻速率非常高

Application of Wet Oxide Etch
濕氧化物蝕刻的應用

  • Creation of oxide masks 氧化物掩模的製作
    > > >> For subsequent applications in diffusion and ion implantation
    > > >> 用於隨後的擴散和離子植入應用
  • Removal of oxide masks 去除氧化物掩模
    > > >> After doping steps  > > >> 掺杂步骤后
  • Spacer layer for surface micromachining
    表面微機械加工的間隔層

    > > >> Micro beams 微束
    > > >> Micro motors 微型馬達

Wet Silicon Etch 濕矽蝕刻

  • Chemistry of silicon etching
    矽蝕刻的化學性質

    > > >> Formation of NO 2 NO 2 NO_(2)\mathrm{NO}_{2} from nitric acid
    從硝酸形成 NO 2 NO 2 NO_(2)\mathrm{NO}_{2}
4 HNO 3 4 NO 2 + 2 H 2 O + O 2 4 HNO 3 4 NO 2 + 2 H 2 O + O 2 4HNO_(3)rarr4NO_(2)+2H_(2)O+O_(2)4 \mathrm{HNO}_{3} \rightarrow 4 \mathrm{NO}_{2}+2 \mathrm{H}_{2} \mathrm{O}+\mathrm{O}_{2}
> > >> Oxidation of silicon by NO 2 NO 2 NO_(2)\mathrm{NO}_{2}
> > >> 矽的氧化由 NO 2 NO 2 NO_(2)\mathrm{NO}_{2}
2 NO 2 + Si SiO 2 + 2 NO 2 NO 2 + Si SiO 2 + 2 NO 2NO_(2)+SirarrSiO_(2)+2NO2 \mathrm{NO}_{2}+\mathrm{Si} \rightarrow \mathrm{SiO}_{2}+2 \mathrm{NO}
> > >> Etching of SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2}  > > >> 蝕刻版畫 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2}
SiO 2 + 6 HF H 2 SiF 6 + 2 H 2 O SiO 2 + 6 HF H 2 SiF 6 + 2 H 2 O SiO_(2)+6HFrarrH_(2)SiF_(6)+2H_(2)O\mathrm{SiO}_{2}+6 \mathrm{HF} \rightarrow \mathrm{H}_{2} \mathrm{SiF}_{6}+2 \mathrm{H}_{2} \mathrm{O}
Overall Reaction 整體反應
4 HNO 3 + 2 Si + 12 HF 4 NO + 6 H 2 O + O 2 + 2 H 2 SiF 6 4 HNO 3 + 2 Si + 12 HF 4 NO + 6 H 2 O + O 2 + 2 H 2 SiF 6 4HNO_(3)+2Si+12HFrarr4NO+6H_(2)O+O_(2)+2H_(2)SiF_(6)4 \mathrm{HNO}_{3}+2 \mathrm{Si}+12 \mathrm{HF} \rightarrow 4 \mathrm{NO}+6 \mathrm{H}_{2} \mathrm{O}+\mathrm{O}_{2}+2 \mathrm{H}_{2} \mathrm{SiF}_{6}

Iso-etch Curves for Si Wet Etching
矽濕蝕刻的等蝕刻曲線

At room temperature 在室溫下

Wet Metal Etch - Aluminum
濕法金屬蝕刻 - 鋁

  • Wet etch of aluminum or aluminum alloy films is generally done in heated solutions ( 35 45 C ) 35 45 C (35-45^(@)C)\left(35-45^{\circ} \mathrm{C}\right) of Phosphoric acid ( H 3 PO 4 ) H 3 PO 4 (H_(3)PO_(4))\left(\mathrm{H}_{3} \mathrm{PO}_{4}\right), Acetic acid ( Ch 3 COOH ) Ch 3 COOH (Ch_(3)COOH)\left(\mathrm{Ch}_{3} \mathrm{COOH}\right), and Nitric acid ( HNO 3 ) HNO 3 (HNO_(3))\left(\mathrm{HNO}_{3}\right) and water (PAN).
    鋁或鋁合金薄膜的濕蝕刻通常在加熱的溶液中進行,該溶液由磷酸、醋酸、硝酸和水(PAN)組成。

    > 80 % P , 5 % A , 5 % N , 10 % > 80 % P , 5 % A , 5 % N , 10 % > 80%P,5%A,5%N,10%>80 \% \mathrm{P}, 5 \% \mathrm{~A}, 5 \% \mathrm{~N}, 10 \% water  > 80 % P , 5 % A , 5 % N , 10 % > 80 % P , 5 % A , 5 % N , 10 % > 80%P,5%A,5%N,10%>80 \% \mathrm{P}, 5 \% \mathrm{~A}, 5 \% \mathrm{~N}, 10 \%
    > 1000 3000 / min > 1000 3000 / min > 1000-3000"Å"//min>1000-3000 \AA / \mathrm{min}
    > HNO 3 > HNO 3 > HNO_(3)>\mathrm{HNO}_{3} acts as the oxidizer to form Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3}
    > HNO 3 > HNO 3 > HNO_(3)>\mathrm{HNO}_{3} 作為氧化劑形成 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3}

    > H 3 PO 4 > H 3 PO 4 > H_(3)PO_(4)>\mathrm{H}_{3} \mathrm{PO}_{4} acts as the etchant for Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3}
    > H 3 PO 4 > H 3 PO 4 > H_(3)PO_(4)>\mathrm{H}_{3} \mathrm{PO}_{4} 作為 Al 2 O 3 Al 2 O 3 Al_(2)O_(3)\mathrm{Al}_{2} \mathrm{O}_{3} 的蝕刻劑

    > H 2 > H 2 > H_(2)>\mathrm{H}_{2} bubble is a annoying problem
    > H 2 > H 2 > H_(2)>\mathrm{H}_{2} 泡沫是一個令人困擾的問題
  • No longer used for advanced IC process
    不再用於先進的集成電路製程

Dry Etching Techniques 乾蝕刻技術

  • Physical bombardment (sputtering)
    物理轟擊(濺射)

    > > >> Ion milling, sputter etching
    > > >> 離子銑磨,濺射蝕刻
  • Chemical reaction 化學反應
    > > >> Pure plasma etching
    > > >> 純等離子體蝕刻

    > > >> Dry equivalent of wet chemistry (e.g., SF6 etching for silicon)
    > > >> 濕化學的乾等效(例如,硫六氟化物蝕刻矽)
  • Combination of physical and chemical mechanisms
    物理與化學機制的結合

    > > >> Plasma etching: with bombardment
    等離子體蝕刻:伴隨轟擊

    > > >> Reactive ion etching (RIE)
    反應離子蝕刻 (RIE)

Dry Etching of Silicon
矽的乾蝕刻

  • Chlorine based plasmas result in better anisotropy than Fluorine based plasma.
    氯基等離子體的各向異性優於氟基等離子體。
  • Fluorine based plasmas have higher etch rate
    氟基等離子體具有更高的蝕刻速率
  • For polysilicon only 僅限多晶矽
    > Cl 2 > Cl 2 > Cl_(2)>\mathrm{Cl}_{2} and SF 6 SF 6 SF_(6)\mathrm{SF}_{6}  > Cl 2 > Cl 2 > Cl_(2)>\mathrm{Cl}_{2} SF 6 SF 6 SF_(6)\mathrm{SF}_{6}
  • For polysilicon on oxide 對於氧化物上的多晶矽
    > > >> Need high selectivity over oxide
    需要對氧化物具有高選擇性

    > CCl 4 > CCl 4 > CCl_(4)>\mathrm{CCl}_{4} are usually selected
    > CCl 4 > CCl 4 > CCl_(4)>\mathrm{CCl}_{4} 通常被選擇

Dry Etching of Oxide
氧化物的乾蝕刻

  • Fluorocarbon based plasmas are usually used for oxide etch
    氟碳基等離子體通常用於氧化物蝕刻

    > CF 4 , CHF 3 , C 2 F 6 , C 3 F 8 > CF 4 , CHF 3 , C 2 F 6 , C 3 F 8 > CF_(4),CHF_(3),C_(2)F_(6),C_(3)F_(8)>\mathrm{CF}_{4}, \mathrm{CHF}_{3}, \mathrm{C}_{2} \mathrm{~F}_{6}, \mathrm{C}_{3} \mathrm{~F}_{8}
    > CF > CF > CF>\mathrm{CF} based molecules was dissociated into many unstable species, radicals, and atoms. They react with oxide to form volatile species
    > CF > CF > CF>\mathrm{CF} 基於分子被解離成許多不穩定的物種、自由基和原子。它們與氧化物反應形成揮發性物種。
Reactive Ion Etch 反應離子蝕刻
  • Utilize ion 利用離子
    bombardment to create 轟炸以創造
    high degree of anisotropy
    高程度的各向異性

    – RIE EXAMPLE: SiO 2 / Si ( CF 4 / H 2 ) SiO 2 / Si CF 4 / H 2 SiO_(2)//Si(CF_(4)//H_(2))\mathrm{SiO}_{2} / \mathrm{Si}\left(\mathrm{CF}_{4} / \mathrm{H}_{2}\right)
    – RIE 範例: SiO 2 / Si ( CF 4 / H 2 ) SiO 2 / Si CF 4 / H 2 SiO_(2)//Si(CF_(4)//H_(2))\mathrm{SiO}_{2} / \mathrm{Si}\left(\mathrm{CF}_{4} / \mathrm{H}_{2}\right)


    – Anisotropic (directional)
    – 各向異性(方向性)

    – Selectivity relatively low
    – 選擇性相對較低

14
Why Dry Etching 為什麼選擇乾蝕刻
  • Better profile control: minimal undercut
    更好的輪廓控制:最小的倒角
  • Don’t need a vast array of chemicals to selectively etch Film_A but not Film_B, at the expense of lower selectivity
    不需要大量化學品來選擇性地蝕刻 Film_A 而不蝕刻 Film_B,這是以較低的選擇性為代價的
  • More versatile, controllable, modular
    更具多功能性、可控性、模組化

Dry Etch Station 乾蝕刻站
Etching Cluster Tool 蝕刻叢集工具

Loading Effect 載入效應

  • Etch rate varies with number of wafers (or total area for etching) in a single run
    蝕刻速率隨著單次處理的晶圓數量(或總蝕刻面積)而變化
  • area uarr\uparrow, etch rate darr\downarrow
    區域 uarr\uparrow ,蝕刻速率 darr\downarrow
  • It also related to the mass transportation
    它也與大眾交通有關
  • Bullseye effect: edges have a higher etch rate
    靶心效應:邊緣的蝕刻速率較高
Yao-Joe Yang 楊耀久

Types of Thin films
薄膜的類型

  • Physical vapor deposition (PVD)
    物理氣相沉積 (PVD)

    > > >> Evaporation  > > >> 蒸發
    > > >> Sputtering 濺射
  • Chemical vapor deposition (CVD)
    化學氣相沉積 (CVD)

    > > >> LPCVD (low pressure)
    低壓化學氣相沉積 (LPCVD)

    > > >> PECVD (plasma enhanced)
    > > >> PECVD(等離子體增強化)

    > > >> APCVD (ambient pressure)
    > > >> APCVD(常壓化學氣相沉積)
  • Epitaxial growth 外延生長

PVD 物理氣相沉積 (PVD)

  • Deposit film by physical methods
    通過物理方法沉積薄膜
Thermal evaporation 熱蒸發
  • Procedure: 程序:
  • Material source is heated to sublimation temperature
    材料源被加熱至升華溫度
  • Vapor of the material is transported to target rarr\rightarrow deposition
    材料的蒸氣被運輸到目標 rarr\rightarrow 沉積處
  • In high vacuum (mean free path = 50 m = 50 m =50m=50 \mathrm{~m} )
    在高真空中(平均自由程 = 50 m = 50 m =50m=50 \mathrm{~m}
  • Deposition is by “line-of-sight”
    沉積是通過“視線”進行的

    > > >> Sputtering 濺射
  • Procedure: 程序:
  • Material atoms are removed from target by momentum transfer
    材料原子透過動量轉移從目標中移除

    » Gas molecules are ionized in a glow discharge
    氣體分子在輝光放電中被電離

    " ions strike target and remove mainly neutral atoms
    "離子撞擊目標並主要去除中性原子"
  • Atoms condense on the substrate rarr\rightarrow deposition
    原子在基材上凝聚 rarr\rightarrow 沉積
  • Easy to deposit alloys
    易於沉積的合金

Thermal Evaporator 熱蒸發器

Electron Beam Evaporator
電子束蒸發器

Types of Evaporation 蒸發的類型

  • Filament evaporation 纖維蒸發
    > > >> major problems  > > >> 主要問題
  • high contamination level
    高污染水平
  • hard to form composite films
    難以形成複合薄膜
  • Electron-beam evaporation
    電子束蒸發

    > > >> using high density electron beam to evaporate metals
    > > >> 使用高密度電子束蒸發金屬

    > > >> dual E-beams with dual target can be used to co-evaporate composite materials
    > > >> 雙電子束與雙靶可以用來共同蒸發複合材料

    > > >> major problem: radiation damage
    主要問題:輻射損傷


    (a)

    (b)

Step Coverage 步驟覆蓋率

  • A primary limitation of evaporation
    蒸發的一個主要限制

    > > >> material beams are non-divergent
    > > >> 材料樑是非發散的
  • Need wafer rotation to improve step coverage
    需要晶圓旋轉以改善步進覆蓋率
  • Performance index 績效指標
    > > >> AR (step height/step diameter)
    > > >> AR (步高/步直徑)

    > > >> OK for AR < 0.5 AR < 0.5 AR < 0.5\mathrm{AR}<0.5  > > >> 可以用於 AR < 0.5 AR < 0.5 AR < 0.5\mathrm{AR}<0.5
    > > >> marginal 0.5 < AR < 1 0.5 < AR < 1 0.5 < AR < 10.5<\mathrm{AR}<1  > > >> 邊際 0.5 < AR < 1 0.5 < AR < 1 0.5 < AR < 10.5<\mathrm{AR}<1
    > > >> poor if A R > 1 A R > 1 AR > 1A R>1  > > >> 如果 A R > 1 A R > 1 AR > 1A R>1 貧窮

Evaporator 蒸發器

Sputtering 濺射

  • The major PVD method in silicon technology
    矽技術中的主要物理氣相沉積方法
  • Using ion bombardment to introduce mass transfer
    利用離子轟擊引入質量傳遞
  • Low temperature process 低溫過程
    > > >> can deposit virtually any materials,
    > > >> 可以幾乎沉積任何材料,
  • metals 金屬
  • ceramics 陶瓷
  • organic materials 有機材料
    > > >> can deposit composite film (alloy) with controllable composition
    > > >> 可以沉積具有可控成分的複合薄膜(合金)
  • Major disadvantage rarr\rightarrow substrate damage
    主要缺點 rarr\rightarrow 基材損壞

Sputtering 濺射

  • Argon (Ar) atoms is usually used as the ion source
    氬(Ar)原子通常用作離子源

    > > >> Inert  > > >> 惰性
    > > >> Relatively heavy 相對較重
    > > >> Abundance  > > >> 豐富性
  • about 1 % 1 % 1%1 \% in atmosphere
    關於 1 % 1 % 1%1 \% 在大氣中
  • low cost 低成本

Sputtering 濺射

Momentum transfer will dislodge surface atoms off
動量轉移將使表面原子脫落
DC Diode Sputtering 直流二極體濺射

Sputter 濺射

Sputtering vs. Evaporator
濺射與蒸發器

  • Sputtering 濺射
Purer film 更純淨的薄膜
> > >> Better uniformity 更好的均勻性
> > >> Single wafer, better process control
> > >> 單晶圓,更佳的製程控制

> > >> Larger size wafer  > > >> 更大尺寸的晶圓
> > >> Low temperature 低溫
Versatile in materials 多功能材料
  • Evaporator 蒸發器
More impurities 更多雜質
> > >> Batch process  > > >> 批次處理
> > >> Cheaper tool  > > >> 更便宜的工具
Less substrate damage 較少的基材損傷

Introduction to CVD CVD 簡介

  • Form thin films by thermal decomposition and/or reaction of gaseous compounds
    通過熱分解和/或氣體化合物反應形成薄膜
> Poly-Si, SiO 2 , Si 3 N 4 >  Poly-Si,  SiO 2 , Si 3 N 4 > " Poly-Si, "SiO_(2),Si_(3)N_(4)>\text { Poly-Si, } \mathrm{SiO}_{2}, \mathrm{Si}_{3} \mathrm{~N}_{4}
  • High temperature process 高溫過程
    > > >> Can be performed at various pressure and with assistance of plasma
    > > >> 可以在不同的壓力下進行,並且可以借助等離子體的協助
Usually at viscous flow regime (not very low pressure)
通常在黏性流動範圍內(不是非常低的壓力)

  • APCVD
    > > >> high deposition rate, poor uniformity, high contamination level, 250 450 C 250 450 C 250-450^(@)C250-450^{\circ} \mathrm{C}
    > > >> 高沉積速率,差的均勻性,高污染水平, 250 450 C 250 450 C 250-450^(@)C250-450^{\circ} \mathrm{C}

    > > >> for dielectrics  > > >> 用於介電材料
  • LPCVD 低壓化學氣相沉積 (LPCVD)
    > > >> low deposition rate, high uniformity, 575 650 C 575 650 C 575-650^(@)C575-650^{\circ} \mathrm{C}
    > > >> 低沉積速率,高均勻性, 575 650 C 575 650 C 575-650^(@)C575-650^{\circ} \mathrm{C}

    > > >> for polysilicon, nitride or oxide
    > > >> 用於多晶矽、氮化物或氧化物
  • PECVD
    > > >> for low deposition temperature
    > > >> 以低沉積溫度

    > > >> e.g, oxide and nitride (insulator)
    例如,氧化物和氮化物(絕緣體)

    > > >> quality is poor  > > >> 的質量很差

CVD Reaction Chambers CVD 反應室

LPCVD System LPCVD 系統

CVD -- Polysilicon CVD -- 多晶矽

  • Application: 應用:
    > > >> gate of MOSFET, surface micromachining
    > > >> MOSFET 的閘極,表面微機電加工
  • Usually deposited in a LPCVD chamber
    通常沉積在低壓化學氣相沉積(LPCVD)腔體中
SiH 4 ( 600 C ) Si + 2 H 2 SiH 4 600 C Si + 2 H 2 SiH_(4)rarr(600^(@)C)Si+2H_(2)\mathrm{SiH}_{4} \rightarrow\left(600^{\circ} \mathrm{C}\right) \mathrm{Si}+2 \mathrm{H}_{2}
  • Pressure: 25 - 150 KPa
    壓力:25 - 150 KPa
  • deposition rate 0.01 0.02 μ m / min 0.01 0.02 μ m / min ∼0.01-0.02 mum//min\sim 0.01-0.02 \mu \mathrm{~m} / \mathrm{min} 沉積速率 0.01 0.02 μ m / min 0.01 0.02 μ m / min ∼0.01-0.02 mum//min\sim 0.01-0.02 \mu \mathrm{~m} / \mathrm{min}
  • Doping (Jaeger, p118) 禁藥(Jaeger,第 118 頁)
    > > >> In situ doping 原位摻雜
  • Add dopant gases during deposition
    在沉積過程中添加摻雜氣體

    > > >> thermal diffusion  > > >> 熱擴散
  • performed right after deposition
    沉積後立即進行

CVD -- Silicon Nitride
CVD -- 硅氮化物

  • Application: 應用:
    > > >> masks to prevent oxidation for LOCOS process
    > > >> 面具以防止 LOCOS 過程中的氧化

    > > >> final passivation barrier for moisture and sodium contamination
    > > >> 最終鈍化屏障以防潮濕和鈉污染
  • APCVD
3 SiH 4 + 4 NH 3 Si 3 N 4 + 12 H 2 3 SiH 4 + 4 NH 3 Si 3 N 4 + 12 H 2 3SiH_(4)+4NH_(3)rarrSi_(3)N_(4)+12H_(2)3 \mathrm{SiH}_{4}+4 \mathrm{NH}_{3} \rightarrow \mathrm{Si}_{3} \mathrm{~N}_{4}+12 \mathrm{H}_{2}

- LPCVD

3 SiCl 2 H 2 + 4 NH 3 Si 3 N 4 + 6 HCl + 6 H 2 3 SiCl 2 H 2 + 4 NH 3 Si 3 N 4 + 6 HCl + 6 H 2 3SiCl_(2)H_(2)+4NH_(3)rarrSi_(3)N_(4)+6HCl+6H_(2)3 \mathrm{SiCl}_{2} \mathrm{H}_{2}+4 \mathrm{NH}_{3} \rightarrow \mathrm{Si}_{3} \mathrm{~N}_{4}+6 \mathrm{HCl}+6 \mathrm{H}_{2}

CVD -- Oxide CVD -- 氧化物

  • Silane based 矽烷基
SiH 4 + O 2 ( 300 500 C ) SiO 2 + 2 H 2 SiH 4 + O 2 300 500 C SiO 2 + 2 H 2 SiH_(4)+O_(2)rarr(300-500^(@)C)SiO_(2)+2H_(2)\mathrm{SiH}_{4}+\mathrm{O}_{2} \rightarrow\left(300-500^{\circ} \mathrm{C}\right) \mathrm{SiO}_{2}+2 \mathrm{H}_{2}
  • PSG 巴黎聖日耳曼足球俱樂部
4 PH 3 + 5 O 2 2 P 2 O 5 + 6 H 2 4 PH 3 + 5 O 2 2 P 2 O 5 + 6 H 2 4PH_(3)+5O_(2)rarr2P_(2)O_(5)+6H_(2)4 \mathrm{PH}_{3}+5 \mathrm{O}_{2} \rightarrow 2 \mathrm{P}_{2} \mathrm{O}_{5}+6 \mathrm{H}_{2}
  • TEOS (tetraethylorthosilicate)
    四乙氧基矽烷 (TEOS)

    (LPCVD 650-700 C C ^(@)C{ }^{\circ} \mathrm{C} ) (PECVD 350 C 350 C 350^(@)C350^{\circ} \mathrm{C} )
Si ( OC 2 H 5 ) 4 SiO 2 + by product Si OC 2 H 5 4 SiO 2 +  by product  Si(OC_(2)H_(5))_(4)rarrSiO_(2)+" by product "\mathrm{Si}\left(\mathrm{OC}_{2} \mathrm{H}_{5}\right)_{4} \rightarrow \mathrm{SiO}_{2}+\text { by product }
  • Silane based PECVD 矽烷基 PECVD
SiH 4 ( g ) + 2 N 2 O ( g ) Δ RF SiO 2 ( s ) + 2 N 2 ( g ) + 2 H 2 ( g ) SiH 4 ( g ) + 2 N 2 O ( g ) Δ RF SiO 2 ( s ) + 2 N 2 ( g ) + 2 H 2 ( g ) SiH_(4(g))+2N_(2)O_((g))rarr_("Delta")^("RF")SiO_(2(s))+2N_(2(g))+2H_(2(g))\mathrm{SiH}_{4(\mathrm{~g})}+2 \mathrm{~N}_{2} \mathrm{O}_{(\mathrm{g})} \xrightarrow[\Delta]{\mathrm{RF}} \mathrm{SiO}_{2(\mathrm{~s})}+2 \mathrm{~N}_{2(\mathrm{~g})}+2 \mathrm{H}_{2(\mathrm{~g})}

PSG and BPSG PSG 和 BPSG

  • Phosphosilicate glass (PSG)
    磷矽酸鹽玻璃 (PSG)

    > > >> reducing stress  > > >> 減輕壓力
    > > >> improve step coverage
    > > >> 改善步驟覆蓋率

    > > >> flow at high temperature (1000-1100 C C ^(@)C{ }^{\circ} \mathrm{C} ) to create smooth surface
    在高溫(1000-1100 C C ^(@)C{ }^{\circ} \mathrm{C} )下進行 > > >> 流動以創造光滑表面
  • Borophosphosilicate glass (BPSG)
    硼磷矽酸鹽玻璃 (BPSG)

    > > >> flow temperature is reduced to 700 C 700 C 700^(@)C700^{\circ} \mathrm{C}
    > > >> 流量溫度降低至 700 C 700 C 700^(@)C700^{\circ} \mathrm{C}

    > > >> for isolation and surface planarization
    > > >> 用於隔離和表面平面化


    (a) 0 % P 0 % P 0%P0 \% \mathrm{P}

    © 4.6 % 4.6 % 4.6%4.6 \%

    (b) 2.2 % 2.2 % 2.2%2.2 \%

    1100 C 1100 C 1100^(@)C1100{ }^{\circ} \mathrm{C} for 20 min .
    1100 C 1100 C 1100^(@)C1100{ }^{\circ} \mathrm{C} 20 分鐘。


FI : Factory Interface FI : 工廠介面
SWLL A/B : Single Wafer Load-lock
SWLL A/B : 單晶圓負載鎖定

CH E/F : Degas
CH E/F : 德加

CH CID : PVD or Pre-clean
CH CID : PVD 或預清潔

CH A/B : Cool down or pass through CH 1/2/3/4/5 : PVD or CVD ( Higher
CH A/B : 冷卻或通過 CH 1/2/3/4/5 : PVD 或 CVD ( 更高
Vacuum Level ) 真空水平
http://www.appliedmaterials.com/products/

ALD (atomic layer deposition)
原子層沉積 (ALD)

  • Basic Principle 基本原則

ALD (atomic layer deposition)
原子層沉積 (ALD)

  • Scheme of ALD of Al2O3
    ALD 鋁氧化物 (Al2O3) 的方案

Activation of the molecule layer
分子層的活化

ALD (atomic layer deposition)
原子層沉積 (ALD)

  • Can be considered as a CVD process
    可以被視為化學氣相沉積過程
  • High quality thin film
    高品質薄膜
  • Excellent step coverage 優秀的步進覆蓋率
  • Slow process rarr\rightarrow low deposition rate
    緩慢過程 rarr\rightarrow 低沉積率
  • Limitation of materials 材料的限制
    (few metals and dielectrics)
    (少數金屬和電介質)
  • Surface reaction only 表面反應僅限於
    > > >> digital growth, layer by layer
    > > >> 數位增長,逐層展開

Transistor Roadmap 晶體管路線圖

CVD vs ALD CVD 與 ALD

CVD TiN

TiCl 4 & NH 3 TiCl 4 & NH 3 TiCl_(4)&NH_(3)\mathrm{TiCl}_{4} \& \mathrm{NH}_{3} simultaneously  TiCl 4 & NH 3 TiCl 4 & NH 3 TiCl_(4)&NH_(3)\mathrm{TiCl}_{4} \& \mathrm{NH}_{3} 同時
Time rarr\rightarrow 時間 rarr\rightarrow
  • Surface & gas phase reaction
    表面與氣相反應
  • Continuous growth 持續增長

ALD TiN

TiCl 4 TiCl 4 TiCl_(4)\mathrm{TiCl}_{4} & NH 3 NH 3 NH_(3)\mathrm{NH}_{3} separately  TiCl 4 TiCl 4 TiCl_(4)\mathrm{TiCl}_{4} NH 3 NH 3 NH_(3)\mathrm{NH}_{3} 分別

  • Surface reaction only 表面反應僅限於
  • Digital growth, layer by layer
    數位增長,層層遞進

Thin Film Material Properties
薄膜材料特性

  • Chemical 化學
    > > >> in many situation, the composition is non-stoichiometric
    在許多情況下,組成是非化學計量的
  • Material structures 材料結構
    > > >> columnar grain for polycrystalline materials
    > > >> 多晶材料的柱狀晶粒
  • Electrical 電氣
Conductivity/resistivity 導電性/電阻率
> > >> Dielectric constant
介電常數

> > >> breakdown voltage  > > >> 突穿電壓
  • Mechanical 機械
    > > >> Dimension  > > >> 維度
    > > >> Stiffness  > > >> 剛度
    > > >> residual stress  > > >> 殘餘應力

Residual Stress 殘餘應力

  • Residual stress 殘餘應力
    > > >> stress of the thin film under no external loading
    在無外部載荷下薄膜的 > > >> 應力

    > > >> A major mechanical problem in thin film materials
    薄膜材料中的一個主要機械問題
  • Problem associated with residual stress
    與殘餘應力相關的問題

    > > >> structural integrity
    結構完整性

    > > >> change of geometry, causing difficulty for subsequent processes
    > > >> 幾何變化,導致後續過程的困難

    > > >> natural frequency shift of MEMS structures
    > > >> MEMS 結構的自然頻率偏移
  • Major sources 主要來源
    > > >> mismatch in thermal mechanical properties
    > > >> 在熱機械性質上的不匹配

    > > >> grain growth, impurity, phase transformation, etc
    > > >> 顆粒生長、雜質、相變化等

Part 7 第七部分

Oxidation 氧化
Yao-Joe Yang 楊耀久

Oxidation Process 氧化過程

  • One of the thin-film processes
    薄膜製程之一
  • For thermal oxidation of silicon
    矽的熱氧化

    > > >> Dry oxidation 乾氧化
  • Si + O 2 SiO 2 Si + O 2 SiO 2 Si+O_(2)rarrSiO_(2)\mathrm{Si}+\mathrm{O}_{2} \rightarrow \mathrm{SiO}_{2}
    > > >> Wet oxidation 濕氧化
  • Si + 2 H 2 O SiO 2 + 2 H 2 Si + 2 H 2 O SiO 2 + 2 H 2 Si+2H_(2)OrarrSiO_(2)+2H_(2)\mathrm{Si}+2 \mathrm{H}_{2} \mathrm{O} \rightarrow \mathrm{SiO}_{2}+2 \mathrm{H}_{2}

Application of Oxide 氧化物的應用

  • Insulator 絕緣體
    > > >> between interconnection
    > > >> 之間的互連
  • Dielectric 介電體
    > > >> gate oxide for MOS capacitors and FET
    > > >> 閘氧化層用於 MOS 電容器和場效應晶體管
  • Masks 面具
    > > >> for ion implantation or etching
    > > >> 用於離子植入或蝕刻
  • Protective layer 保護層
    > > >> to avoid IC damage
    > > >> 以避免集成電路損壞

Modeling of oxidation process
氧化過程的建模

  • Microscopically, the oxidation process is a combination of transportation and surface reaction > > >> Oxygen must be transported into silicon/oxide interafce prior to the reaction
    在微觀上,氧化過程是運輸和表面反應的結合 > > >> 氧氣必須在反應之前被運輸到矽/氧化物界面
  • Ideally, 46 % 46 % 46%46 \% volume of silicon were converted into 100 % 100 % 100%100 \% oxide during oxidation
    理想情況下, 46 % 46 % 46%46 \% 立方體的矽在氧化過程中轉化為 100 % 100 % 100%100 \% 氧化物

    > > >> actual ratio depends on the quality of oxide
    > > >> 實際比率取決於氧化物的質量


    -Volume increases during oxidation
    -氧化過程中體積增加

    0.46 Si 1 0.46 Si 1 *0.46Sirarr1\cdot 0.46 \mathrm{Si} \rightarrow 1 oxide  0.46 Si 1 0.46 Si 1 *0.46Sirarr1\cdot 0.46 \mathrm{Si} \rightarrow 1 氧化物

Deal-Grove Model 迪爾-格羅夫模型

  • Growth rate 增長率
R = J N 1 = d t o x d t = H k s P g N 1 [ 1 + k s h + k a t o x D ] R = J N 1 = d t o x d t = H k s P g N 1 1 + k s h + k a t o x D R=(J)/(N_(1))=(dt_(ox))/(dt)=(Hk_(s)P_(g))/(N_(1)[1+(k_(s))/(h)+(k_(a)t_(ox))/(D)])R=\frac{J}{N_{1}}=\frac{d t_{o x}}{d t}=\frac{H k_{s} P_{g}}{N_{1}\left[1+\frac{k_{s}}{h}+\frac{k_{a} t_{o x}}{D}\right]}
  • Deal-Grove equation 迪爾-格羅夫方程
t o x 2 + A t o x = B ( t + τ ) t o x 2 + A t o x = B ( t + τ ) t_(ox)^(2)+At_(ox)=B(t+tau)t_{o x}^{2}+A t_{o x}=B(t+\tau)
  • where 哪裡
    > B / A > B / A > B//A>B / A : linear rate coefficient
    > B / A > B / A > B//A>B / A : 線性速率係數

    > > >> B: parabolic rate coefficient
    > > >> B: 拋物線速率係數

    > τ > τ > tau>\tau : contribution for initial oxide thickness
    > τ > τ > tau>\tau : 初始氧化層厚度的貢獻
τ = t t x 0 2 + A t o x 0 B τ = t t x 0 2 + A t o x 0 B tau=(t_(tx-0)^(2)+At_(ox-0))/(B)\tau=\frac{t_{t x-0}^{2}+A t_{o x-0}}{B}
> t o x 0 > t o x 0 > t_(ox_(-)0)>t_{o x_{-} 0} : initial oxide thickness
> t o x 0 > t o x 0 > t_(ox_(-)0)>t_{o x_{-} 0} : 初始氧化層厚度

Linear and Parabolic Rate Coefficients
線性與拋物線速率係數

  • For sufficiently thin oxide (linear regime)
    對於足夠薄的氧化物(線性區域)
t o x B A ( t + τ ) t o x B A ( t + τ ) t_(ox)~~(B)/(A)(t+tau)t_{o x} \approx \frac{B}{A}(t+\tau)
  • for sufficiently thick oxide (parabolic regime)
    對於足夠厚的氧化物(拋物線區域)
t o x 2 B ( t + τ ) t o x 2 B ( t + τ ) t_(ox)^(2)~~B(t+tau)t_{o x}^{2} \approx B(t+\tau)
The τ τ tau\tau parameter is used to compensate for the rapid growth regime for thin oxides. (After Deal and Grove.)
τ τ tau\tau 參數用於補償薄氧化物的快速增長模式。(根據 Deal 和 Grove。)

Oxidation Equipment 氧化設備


Oxide Quality 氧化物質量

  • Wet oxide 濕氧化物
    > > >> relative quick process, maximum thickness \sim a few μ m μ m mum\mu \mathrm{m}
    > > >> 相對快速的過程,最大厚度 \sim 幾個 μ m μ m mum\mu \mathrm{m}

    > > >> Mainly for the insulating or masking purpose
    > > >> 主要用於絕緣或遮蔽目的
  • Dry oxide 乾氧化物
    > > >> slow process, higher density, maximum thickness 1000 1000 ∼1000"Å"\sim 1000 \AA
    > > >> 緩慢過程,更高密度,最大厚度 1000 1000 ∼1000"Å"\sim 1000 \AA

    > > >> higher breakdown voltage ( 5 10 MV / cm 5 10 MV / cm ∼5-10MV//cm\sim 5-10 \mathrm{MV} / \mathrm{cm} )
    > > >> 較高的擊穿電壓 ( {{1 }} )

    > > >> used as dielectric for capacitors and MOSFET
    > > >> 用作電容器和 MOSFET 的介電材料
  • high quality gate oxide is critical for microelectronics
    高品質的閘極氧化層對微電子學至關重要

Part 8
Ion Implantation
第八部分 離子植入

Yao-Joe Yang 楊耀久

Introduction 引言

  • Ion implantation is a technology to change the electrical properties by “shooting” high energy impurity (donors/acceptors) into semiconductor substrates
    離子植入是一種通過將高能雜質(施主/受主)“射入”半導體基板來改變電性質的技術
  • advantages over diffusion process
    擴散過程的優勢

    > > >> low temperature process
    > > >> 低溫過程

    > > >> wide variety of masks
    各式各樣的面具

    > > >> minimize the movement of impurity by diffusion
    > > >> 透過擴散最小化雜質的運動

Implantation Technologies
植入技術

  • Ion inplanter is a high-voltage particle accelerator producing a high velocity beam of impurity. It can be divided into the following parts:
    離子植入機是一種高電壓粒子加速器,產生高速度的雜質束。它可以分為以下幾個部分:

    > > >> Ion source  > > >> 離子源
    > > >> Mass spectrometer 質量分析儀
    > > >> High-voltage accelerator
    高壓加速器

    > > >> Scanning system  > > >> 掃描系統
    > > >> Target chamber  > > >> 目標腔體

Ion Implantation Systems
離子植入系統

  • Usually it is quite “big” and “expansive”
    通常它是相當“龐大”和“廣闊”的

Starting material 起始材料

Ion Implantation 離子植入


Ion Implantation System 離子植入系統

Ion Mask Materials 離子面具材料

  • Typical mask materials 典型的口罩材料
Oxide, nitride: all temperature
氧化物、氮化物:所有溫度

Aluminum, PR: low temperature
鋁,PR:低溫
  • Silicon nitride is a more effective barrier than oxide > Only 85% required (Jaeger, p97)
    氮化矽是一種比氧化物更有效的屏障 > 只需 85%(Jaeger,第 97 頁)
  • PR is less effective
    公關的效果較差
Need 180% over oxide thickness
需要 180%的氧化物厚度

Channeling 引導

  • In crystalline substrate, at certain angle, the implanted ions can travel longer than expected before they were finally loss their momentum
    在晶體基板中,於特定角度下,植入的離子可以比預期更長時間地運行,直到它們最終失去動量

    > > >> Result in deeper junction
    > > >> 在更深的接合處的結果

    > > >> Somewhat it is not desirable because it make things uncontrollable
    某種程度上這是不可取的,因為它使事情變得無法控制
  • It will be resolved by a 7 7 7^(@)7^{\circ} tilting for (100) silicon
    將通過對(100)矽的 7 7 7^(@)7^{\circ} 傾斜來解決

Channeling 引導

§ Micromachining rarr\rightarrow two major catagories:
§ 微加工 rarr\rightarrow 兩大類別:

Bulk micromachining 大規模微加工
Surface micromachining 表面微加工
I. Surface micromachining:
一. 表面微加工:
  • Built by thin films
    由薄膜構成
  • Higher device density 更高的設備密度
  • Cheaper 更便宜
  • residual stress problem 殘餘應力問題
  • Easier to be integrated with circuitry
    更容易與電路整合
  • Inferior mechanical performance
    劣質的機械性能

    II. Bulk micromachining:
    II. 大規模微加工:
  • Shaped by etching a large single crystal substrate.
    通過蝕刻大型單晶基板來成形。
  • Thin films are used for isolation or for transduction functions.
    薄膜用於隔離或轉換功能。
  • Bigger 更大
  • Waste of material 物料浪費
  • Well-defined material properties.
    明確定義的材料性質。
  • Better mechanical performance, robust structures
    更好的機械性能,穩健的結構

§ Surface Micromachining
§ 表面微加工

I. Basic processes 一. 基本過程
  • deposit a spacer layer (sacrificial layer) on substrate (oxide).
    在基材(氧化物)上沉積一層間隔層(犧牲層)。

  • Etch base window. (MASK 1)
    蝕刻基底窗口。(掩模 1)

  • microstructure layer deposition on the spacer layer
    微結構層沉積在間隔層上

  • pattern microstructure layer (MASK 2)
    圖案微結構層 (MASK 2)

  • remove the spacer layer to form the freestanding microstructure.
    去除間隔層以形成獨立的微結構。


    II. Advantages/limitations
    II. 優勢/限制
  • Advantage 優勢
  • Precise dimension control
    精確的尺寸控制
  • Variety of material/etchant combinations. Allow creative ideas
    材料/蝕刻劑組合的多樣性。允許創意想法。
  • Economy 經濟
  • Limitation 限制
  • Thin film residual stress may affect the device performance
    薄膜殘餘應力可能影響裝置性能
  • SAC etching might be time consuming
    SAC 蝕刻可能會耗時

    III. Materials III. 材料
Structural Layer 結構層 SAC layer SAC 層 etchant 蝕刻劑
Polysilicon 多晶矽 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} BOE , HF BOE , HF BOE,HF\mathrm{BOE}, \mathrm{HF}
Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} Si  KOH / H 2 O KOH / H 2 O KOH//H_(2)O\mathrm{KOH} / \mathrm{H}_{2} \mathrm{O}
Polyimide 聚酰亞胺 Al 人工智慧 PAN
Ni  Al 人工智慧 PAN
Structural Layer SAC layer etchant Polysilicon SiO_(2) BOE,HF Si_(3)N_(4) Si KOH//H_(2)O Polyimide Al PAN Ni Al PAN| Structural Layer | SAC layer | etchant | | :---: | :---: | :---: | | Polysilicon | $\mathrm{SiO}_{2}$ | $\mathrm{BOE}, \mathrm{HF}$ | | $\mathrm{Si}_{3} \mathrm{~N}_{4}$ | Si | $\mathrm{KOH} / \mathrm{H}_{2} \mathrm{O}$ | | Polyimide | Al | PAN | | Ni | Al | PAN |
PAN: Phosphoric acid (H3PO4), Acetic acid ( Ch 3 COOH ) ( Ch 3 COOH ) (Ch3COOH)(\mathrm{Ch} 3 \mathrm{COOH}), and Nitric acid ( HNO 3 ) HNO 3 (HNO_(3))\left(\mathrm{HNO}_{3}\right) and water.
PAN:磷酸(H3PO4)、醋酸 ( Ch 3 COOH ) ( Ch 3 COOH ) (Ch3COOH)(\mathrm{Ch} 3 \mathrm{COOH}) 、硝酸 ( HNO 3 ) HNO 3 (HNO_(3))\left(\mathrm{HNO}_{3}\right) 和水。

IV. MUMPS Process (ANOTHER PPT)
IV. MUMPS 過程(另一個 PPT)

§ Bulk Micromachining § 大規模微機械加工

I. Wet isotropic etching of silicon
I. 矽的濕等向蝕刻
  • Typical chemistry of silicon etching
    典型的矽蝕刻化學反應

    (i) oxidation of silicon to Si + 2 Si + 2 Si^(+2)\mathrm{Si}^{+2} by strong oxidizing agents
    (i) 硅在強氧化劑作用下氧化至 Si + 2 Si + 2 Si^(+2)\mathrm{Si}^{+2}
Si 2 e + Si + 2 Si 2 e + Si + 2 Sirarr2e^(-)+Si^(+2)\mathrm{Si} \rightarrow 2 \mathrm{e}^{-}+\mathrm{Si}^{+2}
(ii) Attachment of hydroxyl groups ( OH ) ( OH ) (OH)(\mathrm{OH})
(ii) 羥基的附著 ( OH ) ( OH ) (OH)(\mathrm{OH})
Si + 2 + 2 ( OH ) Si ( OH ) 2 Si + 2 + 2 ( OH ) Si ( OH ) 2 Si^(+2)+2(OH)^(-)rarrSi(OH)_(2)\mathrm{Si}^{+2}+2(\mathrm{OH})^{-} \rightarrow \mathrm{Si}(\mathrm{OH})_{2}
(iii) reaction of Si ( OH ) 2 Si ( OH ) 2 Si(OH)_(2)\mathrm{Si}(\mathrm{OH})_{2} with HF
(iii) Si ( OH ) 2 Si ( OH ) 2 Si(OH)_(2)\mathrm{Si}(\mathrm{OH})_{2} 與 HF 的反應
Si ( OH ) 2 + 6 HF H 2 SiF 6 + 2 H 2 O + H 2 Si ( OH ) 2 + 6 HF H 2 SiF 6 + 2 H 2 O + H 2 Si(OH)_(2)+6HFrarrH_(2)SiF_(6)+2H_(2)O+H_(2)\mathrm{Si}(\mathrm{OH})_{2}+6 \mathrm{HF} \rightarrow \mathrm{H}_{2} \mathrm{SiF}_{6}+2 \mathrm{H}_{2} \mathrm{O}+\mathrm{H}_{2}
  • No spatial orientation dependence
    無空間方向依賴性
  • The most common isotropic etchant
    最常見的各向同性蝕刻劑
  • rarr\rightarrow mixtures of HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3} and HF diluted in water and/or acetic acid
    rarr\rightarrow 與 HF 稀釋於水和/或醋酸的 HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3} 混合物
  • the oxidizing agent HNO 2 HNO 2 HNO_(2)\mathrm{HNO}_{2} and ( OH ) ( OH ) (OH)^(-)(\mathrm{OH})^{-}ion are supplied by HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3}, when it combines with water and small amount of HNO 2 HNO 2 HNO_(2)\mathrm{HNO}_{2} HNO 2 + HNO 3 + H 2 O 2 HNO 2 + 2 OH + 2 H + HNO 2 + HNO 3 + H 2 O 2 HNO 2 + 2 OH + 2 H + HNO_(2)+HNO_(3)+H_(2)Orarr2HNO_(2)+2OH^(-)+2H^(+)\mathrm{HNO}_{2}+\mathrm{HNO}_{3}+\mathrm{H}_{2} \mathrm{O} \rightarrow 2 \mathrm{HNO}_{2}+2 \mathrm{OH}^{-}+2 \mathrm{H}^{+}
    氧化劑 HNO 2 HNO 2 HNO_(2)\mathrm{HNO}_{2} ( OH ) ( OH ) (OH)^(-)(\mathrm{OH})^{-} 離子由 HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3} 提供,當它與水和少量的 HNO 2 HNO 2 HNO_(2)\mathrm{HNO}_{2} HNO 2 + HNO 3 + H 2 O 2 HNO 2 + 2 OH + 2 H + HNO 2 + HNO 3 + H 2 O 2 HNO 2 + 2 OH + 2 H + HNO_(2)+HNO_(3)+H_(2)Orarr2HNO_(2)+2OH^(-)+2H^(+)\mathrm{HNO}_{2}+\mathrm{HNO}_{3}+\mathrm{H}_{2} \mathrm{O} \rightarrow 2 \mathrm{HNO}_{2}+2 \mathrm{OH}^{-}+2 \mathrm{H}^{+} 結合時
  • Note: The regeneration of HNO 2 HNO 2 HNO_(2)rarr\mathrm{HNO}_{2} \rightarrow auto-catalytic reaction
    注意: HNO 2 HNO 2 HNO_(2)rarr\mathrm{HNO}_{2} \rightarrow 自催化反應的再生
  • Overall reaction 整體反應
Si + HNO 3 + 6 HF > H 2 SiF 6 + HNO 2 + 2 H 2 + H 2 O Si + HNO 3 + 6 HF > H 2 SiF 6 + HNO 2 + 2 H 2 + H 2 O Si+HNO_(3)+6HFquad-- > H_(2)SiF_(6)+HNO_(2)+2H_(2)+H_(2)O\mathrm{Si}+\mathrm{HNO}_{3}+6 \mathrm{HF} \quad-->\mathrm{H}_{2} \mathrm{SiF}_{6}+\mathrm{HNO}_{2}+2 \mathrm{H}_{2}+\mathrm{H}_{2} \mathrm{O}

(a)

(b)
Isotropic etching (a) without and (b) with stirring
各向同性蝕刻 (a) 無攪拌及 (b) 有攪拌

(i) Etch rate have been measured for silicon etching as a function of concentration of its constituents, and plotted on isoetch curves.
(i) 硅蝕刻的蝕刻速率已根據其成分的濃度進行測量,並繪製在等蝕刻曲線上。

(ii) Increasing the HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3} concentration move the reaction toward the diffusion limited case where etching can be controlled by stirring
(ii) 增加 HNO 3 HNO 3 HNO_(3)\mathrm{HNO}_{3} 濃度使反應朝向擴散限制情況移動,在此情況下,蝕刻可以通過搖動來控制

(iii) Increasing the HF concentration or temperature, increases the surface reaction rate.
(iii) 增加氫氟酸濃度或溫度會提高表面反應速率。

(iv) Reaction rate limited is likely to result in rough surface. As a result, it enhances the defect area.
反應速率受限可能導致表面粗糙。因此,它會增加缺陷區域。

(v) For transport limited reaction, a smoother surface will be resulted.
對於運輸限制反應,將產生更光滑的表面。
  • Electro-Chemical Etching
    電化學蝕刻
  • Apply external electrical source to drive the chemical reaction by supplying oxidizing agent to the silicon surface.
    施加外部電源以通過向矽表面提供氧化劑來驅動化學反應。
  • Etchants: HF / H 2 O HF / H 2 O HF//H_(2)O\mathrm{HF} / \mathrm{H}_{2} \mathrm{O} or NH 4 F / H 2 O NH 4 F / H 2 O NH_(4)F//H_(2)O\mathrm{NH}_{4} \mathrm{~F} / \mathrm{H}_{2} \mathrm{O} solutions.
    刻蝕劑: HF / H 2 O HF / H 2 O HF//H_(2)O\mathrm{HF} / \mathrm{H}_{2} \mathrm{O} NH 4 F / H 2 O NH 4 F / H 2 O NH_(4)F//H_(2)O\mathrm{NH}_{4} \mathrm{~F} / \mathrm{H}_{2} \mathrm{O} 溶液。
  • primarily for polishing surfaces.
    主要用於拋光表面。

    (vi) the etching rate increases with current density rarr\rightarrow high spots on the surface are more rapidly etched.
    (vi) 蝕刻速率隨著電流密度增加而增加,表面的高點被蝕刻得更快。

    (vii) The typical current densities 100 100 ∼100\sim 100 mA / cm 2 mA / cm 2 mA//cm^(2)\mathrm{mA} / \mathrm{cm}^{2}
    (七)典型的電流密度 100 100 ∼100\sim 100 mA / cm 2 mA / cm 2 mA//cm^(2)\mathrm{mA} / \mathrm{cm}^{2}

    (viii) heavily doped (low resistivity) substrates can be selectively removed
    (八)重摻雜(低電阻率)基板可以被選擇性去除


Typical current densities 100 mA / cm 2 100 mA / cm 2 ∼100mA//cm^(2)\sim 100 \mathrm{~mA} / \mathrm{cm}^{2}
典型電流密度 100 mA / cm 2 100 mA / cm 2 ∼100mA//cm^(2)\sim 100 \mathrm{~mA} / \mathrm{cm}^{2}

  • Porous silicon 多孔矽
  • Discover by Uhlir in 1956
    由烏赫爾於 1956 年發現

    (i) high aspect ratio pores.
    (i)高長寬比孔隙。

    (ii) interesting physics, ref. Madou, pp. 229-232 (2nd 2 nd 2 nd  2^("nd ")2^{\text {nd }} )
    有趣的物理學,參見 Madou,第 229-232 頁 (第 2 2 nd 2 nd  2^("nd ")2^{\text {nd }} )

  • Electrochemical etching at
    電化學蝕刻於

    (i) High HF concentrations
    (i) 高濃度的高頻電場

    (ii) Low etch current
    (ii) 低蝕刻電流
  • Diameter range 20A to microns; Oriented in < 100 > < 100 > < 100 ><100> direction
    直徑範圍 20A 至微米;定向於 < 100 > < 100 > < 100 ><100> 方向
  • Aspect ratio (length/diameter) maintained over millimeter distances
    在毫米距離內保持的長度與直徑比(長度/直徑)
  • Application: Permeable membrane.
    應用:可滲透膜。
  • Highly reactant: oxidizes and etches at high rates
    高反應性:以高速度氧化和蝕刻
  • Porosity varies directly with current density
    孔隙率與電流密度成正比
  • Pore formation in n-type requires illumination.
    n 型材料中的孔隙形成需要照明。
  • Operation in dark provides preferential etching of p-type regions.
    在黑暗中操作可對 p 型區域提供優先刻蝕。

    II. Dry isotropic etching of silicon
    II. 矽的乾式各向同性蝕刻
  • Plasma Etching 等離子體蝕刻
  • Use glow discharge to create a chemically-reactive species from non-reactive gas.
    使用輝光放電從非反應性氣體中產生化學反應性物質。
  • Example: SF 6 SF 6 SF_(6)\mathrm{SF}_{6} or CF 4 CF 4 CF_(4)\mathrm{CF}_{4} plasma etching of Si using oxide or resist masks
    範例: SF 6 SF 6 SF_(6)\mathrm{SF}_{6} CF 4 CF 4 CF_(4)\mathrm{CF}_{4} 使用氧化物或抗蝕劑掩模對矽進行等離子體蝕刻
  • Dry Etching 乾蝕刻
  • Fluorine-based gases 氟基氣體
  • Example: 2 XeF 2 + Si = 2 Xe + SiF 4 2 XeF 2 + Si = 2 Xe + SiF 4 2XeF_(2)+Si=2Xe+SiF_(4)2 \mathrm{XeF}_{2}+\mathrm{Si}=2 \mathrm{Xe}+\mathrm{SiF}_{4} 範例: 2 XeF 2 + Si = 2 Xe + SiF 4 2 XeF 2 + Si = 2 Xe + SiF 4 2XeF_(2)+Si=2Xe+SiF_(4)2 \mathrm{XeF}_{2}+\mathrm{Si}=2 \mathrm{Xe}+\mathrm{SiF}_{4}
  • Room temperature etching
    室溫蝕刻
  • highly exothermic deleterious moisture effect; rough surface
    高度放熱的有害濕氣效應;粗糙表面

    III. Wet anisotropic etching of silicon
    III. 矽的濕性各向異性蝕刻
  • The most typical etchant of this type of etching: KOH solution
    這種類型蝕刻的最典型蝕刻劑:氫氧化鉀溶液
  • Crystallographic effects
    晶體學效應
  • Etch rate of { 111 } { 111 } {111}\{111\} plane is much slower than all other planes. rarr\rightarrow etch rate ratios as high as 1000 .
    { 111 } { 111 } {111}\{111\} 平面的蝕刻速率遠低於所有其他平面。 rarr\rightarrow 的蝕刻速率比率高達 1000。
  • The { 111 } { 111 } {111}\{111\} planes rarr\rightarrow the highest density of atoms / cm 2 / cm 2 //cm^(2)/ \mathrm{cm}^{2}
    這些 { 111 } { 111 } {111}\{111\} 平面 rarr\rightarrow 具有最高的原子密度 / cm 2 / cm 2 //cm^(2)/ \mathrm{cm}^{2}

    3 3 rarr3\rightarrow 3 bonds are below { 111 } { 111 } {111}\{111\} plane.
    3 3 rarr3\rightarrow 3 鍵結位於 { 111 } { 111 } {111}\{111\} 平面以下。
  • etching along the planes at the angle defined by the surface intersection with the (111) surface.
    在與(111)表面交叉的角度上,沿著平面進行蝕刻。

100

110

(1,1,1)

( 1 , 0 , 0 ) ( 1 , 0 , 0 ) (1,0,0)(1,0,0)
21

- Commonly used etchants
- 常用的蝕刻劑

  • Alkaline hydroxide ( KOH ) ( KOH ) (KOH)(\mathrm{KOH}) and water
    氫氧化物 ( KOH ) ( KOH ) (KOH)(\mathrm{KOH}) 和水

    (i) Example: KOH and NaOH
    (i)範例:KOH 和 NaOH

    (ii) (+): High etch rate ratio (100)/(111) (high selectivity)
    (ii) (+): 高蝕刻速率比 (100)/(111) (高選擇性)

    (iii) (-): Relatively high SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} etch rate, alkali contamination
    (iii) (-): 相對較高的 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 蝕刻速率,鹼性污染
  • Ethylene-Diamine-Pyrocatechol/ H 2 O H 2 O H_(2)O\mathrm{H}_{2} \mathrm{O} (EDP)
    乙烯二胺-吡咯卡特醇/ H 2 O H 2 O H_(2)O\mathrm{H}_{2} \mathrm{O} (EDP)

    (i) (+): High selectivity rarr\rightarrow variety of etch mask material
    (i)(+):高選擇性 rarr\rightarrow 種刻蝕掩模材料

    (ii) (-): Optically dense
    (ii) (-): 光學密度

    (iii) SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} is good mask
    (iii) SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 是良好的口罩
  • Hydrazine-water ( N 2 H 4 : H 2 O ) N 2 H 4 : H 2 O (N_(2)H_(4):H_(2)O)\left(\mathrm{N}_{2} \mathrm{H}_{4}: \mathrm{H}_{2} \mathrm{O}\right) 肼-水 ( N 2 H 4 : H 2 O ) N 2 H 4 : H 2 O (N_(2)H_(4):H_(2)O)\left(\mathrm{N}_{2} \mathrm{H}_{4}: \mathrm{H}_{2} \mathrm{O}\right)
    (i) (+): Low SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} etch rate
    (i) (+): 低 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 蝕刻速率

    (ii) (-): Low etch rate ratio (100)/(111), gas is explosive
    (ii) (-): 低蝕刻速率比 (100)/(111),氣體具有爆炸性
  • Etch Masks: 蝕刻掩模:
  • Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} etch rate in most anisotropic etchants is virtually zero.
    在大多數各向異性蝕刻劑中, Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 蝕刻速率幾乎為零。
  • SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} etch rate is dependent on etch conditions.
    SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} 蝕刻速率取決於蝕刻條件。
 蝕刻劑(稀釋劑)
ETCHANT
(Diluent)
ETCHANT (Diluent)| ETCHANT | | :--- | | (Diluent) |
 典型食譜
TYPICAL
RECIPE
TYPICAL RECIPE| TYPICAL | | :--- | | RECIPE |
TEMP.
C C ^(@)C{ }^{\circ} \mathrm{C}
TEMP. ^(@)C| TEMP. | | :--- | | ${ }^{\circ} \mathrm{C}$ |
ETCH RATE μ m / min μ m / min mum//min\mu \mathrm{m} / \mathrm{min} 蝕刻速率 μ m / min μ m / min mum//min\mu \mathrm{m} / \mathrm{min}

蝕刻速率比 (100)/(111)
ETCH RATE RATIO
(100)/(111)
ETCH RATE RATIO (100)/(111)| ETCH RATE RATIO | | :--- | | (100)/(111) |
MASK (etch rate)  MASK   (etch rate)  {:[" MASK "],[" (etch rate) "]:}\begin{aligned} & \text { MASK } \\ & \text { (etch rate) } \end{aligned}
 氫氧化鉀 (水)
KOH
(Water)
KOH (Water)| KOH | | :--- | | (Water) |
44 gr 100 ml
44 克 100 毫升
85 1.4 400:1 Si 3 N 4 SiO 2 ( 14 / min ) Si 3 N 4 SiO 2 ( 14 / min ) {:[Si_(3)N_(4)],[SiO_(2)(14"Å"//min)]:}\begin{aligned} & \mathrm{Si}_{3} \mathrm{~N}_{4} \\ & \mathrm{SiO}_{2}(14 \AA / \mathrm{min}) \end{aligned}
NaOH (Water) 氫氧化鈉(水) 10 gr 100 ml 10 gr 100 ml {:[10gr],[100ml]:}\begin{aligned} & 10 \mathrm{gr} \\ & 100 \mathrm{ml} \end{aligned} 65 0.25-1.0 >300:1 Si 3 N 4 SiO 2 ( 7 A / min ) Si 3 N 4 SiO 2 ( 7 A / min ) {:[Si_(3)N_(4)],[SiO_(2)(7A//min)]:}\begin{aligned} & \mathrm{Si}_{3} \mathrm{~N}_{4} \\ & \mathrm{SiO}_{2}(7 \mathrm{~A} / \mathrm{min}) \end{aligned}
Ethylene diamine Pyrocatecho (Water)
乙烯二胺焦香豆醇(水)

750 毫升 120 克 240 毫升
750 ml
120 gr
240 ml
750 ml 120 gr 240 ml| 750 ml | | :--- | | 120 gr | | 240 ml |
115 1.25 35:1
SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} (2 A/min)
Si 3 N 4 ( 1 / m i n ) Si 3 N 4 ( 1 / m i n ) Si_(3)N_(4)(1"Å"//min)\mathrm{Si}_{3} \mathrm{~N}_{4}(1 \AA / m i n)
Ta , Au , Cr , Ag , Cu Ta , Au , Cr , Ag , Cu Ta,Au,Cr,Ag,Cu\mathrm{Ta}, \mathrm{Au}, \mathrm{Cr}, \mathrm{Ag}, \mathrm{Cu}
SiO_(2) (2 A/min) Si_(3)N_(4)(1"Å"//min) Ta,Au,Cr,Ag,Cu| $\mathrm{SiO}_{2}$ (2 A/min) | | :--- | | $\mathrm{Si}_{3} \mathrm{~N}_{4}(1 \AA / m i n)$ | | $\mathrm{Ta}, \mathrm{Au}, \mathrm{Cr}, \mathrm{Ag}, \mathrm{Cu}$ |
N 2 H 4 (Water) N 2 H 4  (Water)  {:[N_(2)H_(4)],[" (Water) "]:}\begin{aligned} & \mathrm{N}_{2} \mathrm{H}_{4} \\ & \text { (Water) } \end{aligned} 100 ml 100 ml
100 毫升 100 毫升
100 2.0 10:1 SiO 2 SiO 2 SiO_(2)\mathrm{SiO}_{2} (<2A/min)
"ETCHANT (Diluent)" "TYPICAL RECIPE" "TEMP. ^(@)C" ETCH RATE mum//min "ETCH RATE RATIO (100)/(111)" " MASK (etch rate) " "KOH (Water)" 44 gr 100 ml 85 1.4 400:1 "Si_(3)N_(4) SiO_(2)(14Å//min)" NaOH (Water) "10gr 100ml" 65 0.25-1.0 >300:1 "Si_(3)N_(4) SiO_(2)(7A//min)" Ethylene diamine Pyrocatecho (Water) "750 ml 120 gr 240 ml" 115 1.25 35:1 "SiO_(2) (2 A/min) Si_(3)N_(4)(1"Å"//min) Ta,Au,Cr,Ag,Cu" "N_(2)H_(4) (Water) " 100 ml 100 ml 100 2.0 10:1 SiO_(2) (<2A/min)| ETCHANT <br> (Diluent) | TYPICAL <br> RECIPE | TEMP. <br> ${ }^{\circ} \mathrm{C}$ | ETCH RATE $\mu \mathrm{m} / \mathrm{min}$ | ETCH RATE RATIO <br> (100)/(111) | $\begin{aligned} & \text { MASK } \\ & \text { (etch rate) } \end{aligned}$ | | :---: | :---: | :---: | :---: | :---: | :---: | | KOH <br> (Water) | 44 gr 100 ml | 85 | 1.4 | 400:1 | $\begin{aligned} & \mathrm{Si}_{3} \mathrm{~N}_{4} \\ & \mathrm{SiO}_{2}(14 \AA / \mathrm{min}) \end{aligned}$ | | NaOH (Water) | $\begin{aligned} & 10 \mathrm{gr} \\ & 100 \mathrm{ml} \end{aligned}$ | 65 | 0.25-1.0 | >300:1 | $\begin{aligned} & \mathrm{Si}_{3} \mathrm{~N}_{4} \\ & \mathrm{SiO}_{2}(7 \mathrm{~A} / \mathrm{min}) \end{aligned}$ | | Ethylene diamine Pyrocatecho (Water) | 750 ml <br> 120 gr <br> 240 ml | 115 | 1.25 | 35:1 | $\mathrm{SiO}_{2}$ (2 A/min) <br> $\mathrm{Si}_{3} \mathrm{~N}_{4}(1 \AA / m i n)$ <br> $\mathrm{Ta}, \mathrm{Au}, \mathrm{Cr}, \mathrm{Ag}, \mathrm{Cu}$ | | $\begin{aligned} & \mathrm{N}_{2} \mathrm{H}_{4} \\ & \text { (Water) } \end{aligned}$ | 100 ml 100 ml | 100 | 2.0 | 10:1 | $\mathrm{SiO}_{2}$ (<2A/min) |
  • More on crystalline orientation effect:
    更多關於晶體取向效應的內容:
  • KOH etch through a “rectangular hole”
    KOH 蝕刻通過一個「矩形孔」


Formation of micro cantilever beam
微型懸臂梁的形成
  • For (100) wafer, arbitrary-shape mask pattern results in a rectangular etch pit (long etch time).
    對於 (100) 晶圓,任意形狀的掩模圖案會導致矩形蝕刻坑(長蝕刻時間)。

  • Occurrence of undercutting depends on orientation of wafer
    切割下陷的發生取決於晶圓的方向

  • (110) oriented silicon will produce vertical etched surface
    (110) 取向矽將產生垂直蝕刻表面

29
IV. Etch-stop methods for silicon etching
IV. 硅蝕刻的刻蝕停止方法
  • methods of controlling the depth of etching for geometry and profile control.
    控制幾何形狀和輪廓的蝕刻深度的方法。
  • three types: 三種類型:
  1. Timed 定時
  2. Chemical 化學
  3. Electrochechanical 電機機械
  • Timed 定時
  • require precise control of
    需要精確控制的

    (i) Sample thickness (i)樣本厚度
    (ii) Etch-rate (and therefore etchant concentration)
    (二) 蝕刻速率(因此也包括蝕刻劑濃度)
  • Etch rate control requires monitoring and stabilizing of:
    蝕刻速率控制需要監測和穩定:

    (i) Etchant composition (i) 蝕刻劑組成
    (ii) Etchant aging. e.g., total amount of material etched (loading effect)
    (二) 蚀刻劑老化。例如,蚀刻的材料总量(负载效应)

    (iii) Etchant temperature
    (iii) 蝕刻劑溫度

    (iv) Diffusion effects (stirring)
    (四)擴散效應(搖動)

    (v) Light (v)光
    (vi) Surface preparation of sample
    (六)樣本的表面準備
  • Chemical 化學
  • etch-rates modified by changing the composition of the material, e.g. silicon nitride diaphragm on silicon
    通過改變材料的組成來修改蝕刻速率,例如在矽上使用氮化矽隔膜。

  • etch-stop on silicon is achieved by changing doping concentration (i) n on n + n + n+\mathrm{n}+ (or p on p + p + p+\mathrm{p}+ ) for isotropic etching ( HF : HNO 3 : CH 3 COOH HF : HNO 3 : CH 3 COOH HF:HNO_(3):CH_(3)COOH\mathrm{HF}: \mathrm{HNO}_{3}: \mathrm{CH}_{3} \mathrm{COOH} ): Etch rate of heavily doped ( > 10 17 cm 3 > 10 17 cm 3 > 10^(17)cm^(-3)>10^{17} \mathrm{~cm}^{-3} ) silicon 150 X 150 X ∼150X\sim 150 \mathrm{X} faster than lightly doped silicon.
    在矽上實現蝕刻停止是通過改變摻雜濃度 (i) n 在 n + n + n+\mathrm{n}+ (或 p 在 p + p + p+\mathrm{p}+ ) 以進行各向同性蝕刻 ( HF : HNO 3 : CH 3 COOH HF : HNO 3 : CH 3 COOH HF:HNO_(3):CH_(3)COOH\mathrm{HF}: \mathrm{HNO}_{3}: \mathrm{CH}_{3} \mathrm{COOH} ):重摻雜 ( > 10 17 cm 3 > 10 17 cm 3 > 10^(17)cm^(-3)>10^{17} \mathrm{~cm}^{-3} ) 矽的蝕刻速率 150 X 150 X ∼150X\sim 150 \mathrm{X} 快於輕摻雜矽。
32
(ii) p + + p + + p++\mathrm{p++} on p ( p ( p(\mathrm{p}( or n ) ) )) for anisotropic etching.
(ii) p + + p + + p++\mathrm{p++} p ( p ( p(\mathrm{p}( 上或 n ) ) )) 用於各向異性蝕刻。

■ boron concentrations > 5 × 10 19 cm 3 > 5 × 10 19 cm 3 > 5xx10^(19)cm^(-3)>5 \times 10^{19} \mathrm{~cm}^{-3}
■ 硼濃度 > 5 × 10 19 cm 3 > 5 × 10 19 cm 3 > 5xx10^(19)cm^(-3)>5 \times 10^{19} \mathrm{~cm}^{-3}

rarr\rightarrow etch-stop for anisotropic etchants
rarr\rightarrow 蝕刻停止劑用於各向異性蝕刻劑

■ High boron concentration
■ 高硼濃度

rarr\rightarrow bad for material properties (for mechanical and electronic).
rarr\rightarrow 對材料性質(機械和電子)有不良影響。
  • Electrochemical Etch-Stop rarr\rightarrow p-n Junction Etch-Stop
    電化學蝕刻停止 rarr\rightarrow p-n 接面蝕刻停止
  • p-n diode configuration rarr\rightarrow anodizing current blocked by the diode rarr\rightarrow etch p-type substrate only
    p-n 二極體配置 rarr\rightarrow 被二極體阻擋的陽極氧化電流 rarr\rightarrow 僅蝕刻 p 型基板
  • As the n-layer exposes, its surface anodizes rarr\rightarrow passivation layer forms and etching stops.
    隨著 n 層的暴露,其表面陽極氧化 rarr\rightarrow 鈍化層形成並且蝕刻停止。
  • Membrane thickness is determined by the epi-layer
    膜厚度由表層決定
  • Large applied voltage results in large reverse diode (p-n junction) leakage current rarr\rightarrow form passivation
    大應用電壓導致大反向二極體(p-n 結)漏電流 rarr\rightarrow 形成鈍化

    layer before etch through p-Si.
    在蝕刻 p-Si 之前的層。

  • issues need to be considered for P-N junction etch-stop
    在 P-N 接面蝕刻停止過程中需要考慮的問題

    (i) Effect of light (light can accelerate the etch process)
    (i) 光的影響(光可以加速蝕刻過程)

    (ii) Resistive loss changes potential
    (二) 電阻損失改變潛力

    (iii) Electrical contact to alter the electric potential
    (iii) 電接觸以改變電位




    V. Wafer Bonding V. 晶圓鍵合
  • Types of wafer bonding
    晶圓鍵合的類型
  • Fusion bonding (direct bonding)
    融合鍵合(直接鍵合)

    (i) Silicon-silicon bonds
    矽-矽鍵

    (ii) Process (二)過程
    (1) Cleaning and hydration of the wafer surface
    (1) 晶圓表面的清潔與水合作用

    (2) fusion at high temperature ( 1000 C 1000 C ∼1000^(@)C\sim 1000^{\circ} \mathrm{C} )
    (2) 高溫熔合 ( 1000 C 1000 C ∼1000^(@)C\sim 1000^{\circ} \mathrm{C} )

    (iii) Advantages: (iii) 優勢:
    (1) All single crystal silicon, thermal match
    (1) 所有單晶矽,熱匹配

    (2) High strength (2) 高強度
    (3) No intermediate layers
    (3) 無中介層

    (4) Hermetic sealing (4) 密封封閉
    (5) Self-packaged (5) 自我包裝
  • Anodic bonding 陽極鍵合
    (i) Silicon (=anode) to Pyrex glass (=cathode)
    (一) 矽 (=陽極) 與鋼化玻璃 (=陰極)

    (ii) 200 C 500 C , 500 V 1000 V 200 C 500 C , 500 V 1000 V 200^(@)C∼500^(@)C,500V∼1000V200^{\circ} \mathrm{C} \sim 500^{\circ} \mathrm{C}, 500 \mathrm{~V} \sim 1000 \mathrm{~V}
    (iii) high field and high temperature on interface rarr\rightarrow sodium in glass drifts rarr\rightarrow pulls two surface together rarr\rightarrow bond.
    (iii) 高場和高溫對界面 rarr\rightarrow 鈉在玻璃中的漂移 rarr\rightarrow 使兩個表面相互吸引 rarr\rightarrow 鍵結。

    (iv) Hermetic sealing (四)密封封閉
    (v) Need good thermal match for silicon and glass (Pyrex 7740 )
    (v) 需要良好的熱匹配以適應矽和玻璃(Pyrex 7740)
  • Gold eutectic bonding 金共晶鍵合
    (i) Silicon to silicon; silicon to other materials
    (i)矽對矽;矽對其他材料

    (ii) Silicon and gold alloy has a eutectic temperature 316 C 316 C ∼316^(@)C\sim 316{ }^{\circ} \mathrm{C}.
    (ii) 矽和金合金的共晶溫度為 316 C 316 C ∼316^(@)C\sim 316{ }^{\circ} \mathrm{C}

    (iii) Low temperature bond, less thermal budget
    (iii) 低溫鍵合,較少的熱預算

    (iv) Strength is not as good as fusion bond
    (iv) 強度不如熔接接頭
  • Glass frit or solder bonding
    玻璃粉或焊接粘合
  • Process 過程
  • Process sequence for fusion bond
    融合接合的過程順序

    (i) Surface hydration (i) 表面水合
    rarr\rightarrow rinse, NH 4 OH , H 2 SO 4 : H 2 O 2 , HNO 3 NH 4 OH , H 2 SO 4 : H 2 O 2 , HNO 3 NH_(4)OH,H_(2)SO_(4):H_(2)O_(2),HNO_(3)\mathrm{NH}_{4} \mathrm{OH}, \mathrm{H}_{2} \mathrm{SO}_{4}: \mathrm{H}_{2} \mathrm{O}_{2}, \mathrm{HNO}_{3}  rarr\rightarrow 漱口, NH 4 OH , H 2 SO 4 : H 2 O 2 , HNO 3 NH 4 OH , H 2 SO 4 : H 2 O 2 , HNO 3 NH_(4)OH,H_(2)SO_(4):H_(2)O_(2),HNO_(3)\mathrm{NH}_{4} \mathrm{OH}, \mathrm{H}_{2} \mathrm{SO}_{4}: \mathrm{H}_{2} \mathrm{O}_{2}, \mathrm{HNO}_{3}
    (i) Press polished surface together. Particles must be avoided on contact surface.
    (i)將拋光表面壓合在一起。接觸表面必須避免顆粒。

    (ii) High temperature anneal (strength increases with temperature)
    (ii) 高溫退火(強度隨溫度增加)
  • Important parameters 重要參數
    (i) Surface roughness (must less than 1 nano meter)
    表面粗糙度(必須小於 1 納米)

    (ii) Wafer bow (二) 晶圓翹曲
    (iii) For bonding of patterned wafers, cavity pressure is important
    (iii) 對於圖案化晶圓的粘合,腔體壓力是重要的
  • CVD film can be bonded if the are polished smooth.
    CVD 薄膜可以在表面被拋光平滑後進行粘合。
  • Inspection Methods: 檢查方法:
    (i) IR imaging, X-ray topography, Ultrasonic
    (i) 紅外成像、X 射線拓撲學、超聲波

    (ii) Bond strength testing
    (ii) 鍵合強度測試

    VI. Other bulk micromachining
    六. 其他大規模微加工
  • Dissolved wafer process 溶解晶圓製程

    (wafer dissolved in EDP)
    (在 EDP 中溶解的晶圓)
41
  • DRIE (Deep RIE) - The Bosch Process
    DRIE(深度 RIE)- 博世工藝
  • ICP (Inductively Coupled Plasma)
    感應耦合等離子體 (ICP)
  • Patented process by the Bosch Company
    博世公司專利工藝
  • Time-multiplexed glow-discharge of a silicon isotropic etch gas ( SF 6 ) SF 6 (SF_(6))\left(\mathrm{SF}_{6}\right) with a polymer (passivation) forming gas ( C 4 F 6 ) C 4 F 6 (C_(4)F_(6))\left(\mathrm{C}_{4} \mathrm{~F}_{6}\right).
    時間多工的矽各向同性蝕刻氣體 ( SF 6 ) SF 6 (SF_(6))\left(\mathrm{SF}_{6}\right) 與聚合物(鈍化)形成氣體 ( C 4 F 6 ) C 4 F 6 (C_(4)F_(6))\left(\mathrm{C}_{4} \mathrm{~F}_{6}\right) 的輝光放電。

Pattern mask and isotropic etch r 30 sec r 30 sec r-30secr-30 \mathrm{sec}
圖案掩模和各向同性蝕刻 r 30 sec r 30 sec r-30secr-30 \mathrm{sec}



  • Lift-off Process 起飛過程
  • Very common for metal film patterning
    金屬薄膜圖案化非常常見
  • Good for patterning the film whose residual is difficult to be etched thoroughly
    適合於圖案化那些殘留物難以徹底蝕刻的薄膜
  • Need good stencil patterns for successful lift-off
    需要良好的模板圖案以實現成功的脫落

Introduction to MUMPS  MUMPS 簡介

Yao-Joe Yang 楊耀久

Multi-User MEMS Processes (MUMPs TM TM  ^("TM "){ }^{\text {TM }} )
多用戶微機電系統製程 (MUMPs TM TM  ^("TM "){ }^{\text {TM }} )

  • commercial MEMS foundry program by (CMC Microsystems / MEMSCap)
    商業 MEMS 鑄造計劃(CMC 微系統 / MEMSCap)
■surface micromachining fabrication process
■表面微機械加工製造過程

ㅁ cost-effective, proof-of-concept
具成本效益的概念驗證

םhttp://www.memsrus.com/cronos/svcsmumps.html
抱歉,我無法訪問或翻譯網頁內容。請提供具體的文本,我將為您進行翻譯。

Three-layer-polysilicon surface process
三層多晶矽表面處理工藝

Figure 1.1. Cross sectional view showing all 7 layers of the MUMPsTTM process (not to scale).
圖 1.1. 橫截面圖顯示 MUMPsTTM 過程的所有 7 層(不按比例)。

-Three-layer-polysilicon surface process.
三層多晶矽表面處理。

ㅁ polysilicon is used as the structural material (3 layers)
多晶矽被用作結構材料(3 層)
ㅁ oxide (PSG) is used as the sacrificial layer (2 layers)
氧化物 (PSG) 被用作犧牲層 (2 層)
  • Silicon nitride is used as electrical isolation (1 layer)
    氮化矽用作電氣隔離(1 層)
  • Metal is used as metal contact for wire bonding (1 layer)
    金屬用作線焊接的金屬接觸(1 層)

Wicro Illotor Falurication Precess
微克伊洛托爾法盧里卡申過程

MIT/RTET Micro Motor (Eirca 1989]
麻省理工學院/RTET 微型馬達(約 1989 年)


Figure 1.4. Reactive ion etching (RIE) is used to remove the unwanted polysilicon. After the etch, the photoresist is chemically stripped in a solvent bath. This method of patterning the wafers with photoresist, etching and stripping the remaining photoresist is used repeatedly in the MUMPs TTM TTM  ^("TTM "){ }^{\text {TTM }} process
圖 1.4. 反應離子蝕刻(RIE)用於去除不需要的多晶矽。蝕刻後,光刻膠在溶劑浴中進行化學去除。這種使用光刻膠對晶圓進行圖案化、蝕刻及去除剩餘光刻膠的方法在 MUMPs TTM TTM  ^("TTM "){ }^{\text {TTM }} 過程中反覆使用。


Figure 1.8. A blanket 2.0 um layer of un-doped polysilicon is deposited by LPCVD followed by the deposition of 200 nm PSG and a 1050 C / 1 1050 C / 1 1050^(@)C//11050^{\circ} \mathrm{C} / 1 hour anneal. The anneal serves to both dope the polysilicon and reduce its residual stress
圖 1.8。通過低壓化學氣相沉積(LPCVD)沉積一層 2.0 微米的未摻雜多晶矽,隨後沉積 200 奈米的磷掺雜玻璃(PSG)並進行 1050 C / 1 1050 C / 1 1050^(@)C//11050^{\circ} \mathrm{C} / 1 小時的退火。退火的作用是對多晶矽進行摻雜並減少其殘餘應力。


to create a hard mask and then Poly 1 is etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed.
創建一個硬掩模,然後通過反應離子蝕刻(RIE)蝕刻 Poly 1。在蝕刻完成後,去除光刻膠和 PSG 硬掩模。

Figure 1.10. The Second Oxide layer, 0.75 μ m 0.75 μ m 0.75 mum0.75 \mu \mathrm{~m} of PSG, is deposited on the wafer. This layer is patterned twice to allow contact to both Poly 1 and substrate layers
圖 1.10。第二氧化層 0.75 μ m 0.75 μ m 0.75 mum0.75 \mu \mathrm{~m} 的 PSG 被沉積在晶圓上。此層被圖案化兩次,以便與 Poly 1 和基板層接觸。

Figure 1.11. The wafer is coated with photoresist and the fith level (POLY1_POLY2_VIA) is lithographically patterned. The unwanted Second Oxide is RIE etched, stopping on Poly 1 , and the photoresist is stripped.
圖 1.11。晶圓上塗覆了光刻膠,並且第五層 (POLY1_POLY2_VIA) 進行了光刻圖案化。多餘的第二氧化層經過 RIE 蝕刻,停止於 Poly 1,然後去除光刻膠。

The wafer is re-coated with photoresist and the sixth level (ANCHOR2) is lithographically patterned. The Second and
晶圓重新塗覆光刻膠,並對第六層(ANCHOR2)進行光刻圖案化。第二層和

First Oxides are RIE etched, stopping on either Nitrice or Poly 0 , and the photoresist is stripped. The ANCHOR2 level provides openings for Poly 2 to contact with Nitride or Poly 0 .
首先,氧化物經過 RIE 蝕刻,停止於氮化物或聚合物 0,然後去除光阻。ANCHOR2 層提供聚合物 2 與氮化物或聚合物 0 接觸的開口。


Figure 1.14. The wafer is coated with photoresist and the seventh level (POLY2) is lithographically patterned. The PSG hard mask Poly 2 layers are RE etched and the photoresist and hard mask are reved Al mechanical structures have now been fabricated. The remaining steps are to deposit the metal layer and remove the sacrificial oxides.
圖 1.14。晶圓上塗覆了光刻膠,第七層(POLY2)經過光刻圖案化。PSG 硬掩模 Poly 2 層經過 RE 蝕刻,光刻膠和硬掩模被去除,機械結構已經製造完成。剩下的步驟是沉積金屬層並去除犧牲氧化物。

METAL 金屬

Figure 1.15. The wafer is coated with photoresist and the eighth level (METAL) is lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by lif–off patterning which does not require etching. The side wall of the photoresist is
圖 1.15。晶圓上塗覆了光刻膠,並且第八層(金屬)經過光刻圖案化。金屬(帶有薄附著層的金)是通過去除圖案化沉積的,這不需要蝕刻。光刻膠的側壁是

sloped at a reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent bath. The process is now complete and the wafers can be coated with a protective layer of photoresist and diced. The chips are sorted and shipped
以凹入角度傾斜,這使得金屬可以沉積在晶圓和光阻的表面上,但在凹入的光阻階梯上提供了金屬連續性的中斷。然後在溶劑浴中去除光阻和不需要的金屬(在光阻上方)。該過程現在已完成,晶圓可以塗覆一層保護性的光阻並進行切割。晶片被分類並運送。

Figure 1.16. The structures are released by immersing the chips in a 49 % HF 49 % HF 49%HF49 \% \mathrm{HF} solution. The Poly 1 “rotor” can be seen around the fixed Poly 2 hub. The stacks of Poly 1 , Poly 2 and Metal on the sides represent the stators used to drive the motor electrostatically.
圖 1.16。這些結構是通過將晶片浸入 49 % HF 49 % HF 49%HF49 \% \mathrm{HF} 溶液中釋放的。可以看到固定的 Poly 2 中心周圍有 Poly 1 “轉子”。側面的 Poly 1、Poly 2 和金屬堆疊代表用於靜電驅動馬達的定子。

Concepts of MEMS Modeling
MEMS 建模的概念

Yao-Joe Yang 楊耀久
National Taiwan University
國立臺灣大學

Outline 大綱

  • Modeling, simulation and measurement
    建模、模擬與測量
  • Modeling is essential ?
    建模是必不可少的嗎?
  • Introduction to MEMS modeling package
    MEMS 建模套件介紹

What is Modeling ?
什麼是建模?

  • “Model” + “ing” “模型” + “化”
  • Search for appropriate models for physical systems
    尋找適合物理系統的模型
  • F=ma by Sir I. Newton.
    F=ma 由艾薇·牛頓爵士提出。
  • E = mc 2 E = mc 2 E=mc^(2)\mathrm{E}=\mathrm{mc}^{2} by A. Einstein.  E = mc 2 E = mc 2 E=mc^(2)\mathrm{E}=\mathrm{mc}^{2} 由阿爾伯特·愛因斯坦。
  • Atomic model by Bohr
    波爾的原子模型
  • We all are more or less doing “some” modeling works for our research.
    我們或多或少都在為我們的研究進行「一些」建模工作。

What is Simulation? 什麼是模擬?

  • Computer simulation 電腦模擬
  • Predict the behavior of a physical system by solving corresponding models (GEs + BCs + ICs … ) using computers
    通過使用計算機解決相應的模型(GEs + BCs + ICs … )來預測物理系統的行為

> > >> Purposes of simulations:
模擬的目的:

> > >> Verify modeling works (models)
> > >> 驗證建模工作(模型)

> > >> Physics  > > >> 物理學
> > >> Help design works  > > >> 幫助設計作品
> > >> Engineering  > > >> 工程

Relationship among 關係之間

Modeling, Experiment and Simulation
建模、實驗與模擬

> > >> Experiment and Simulation are the two ways to verify the model of a system.
實驗和模擬是驗證系統模型的兩種方法。
Experiment: 實驗:
> > >> Expensive (typically)
> > >> 昂貴(通常)

> > >> Device fabrication, measurement equipment setup > > >> Plausible
> > >> 裝置製造,測量設備設置 > > >> 可信的

> > >> Usually can verify the “model” under special conditions > > >> Compare with analytical solution of the “model”
> > >> 通常可以在特定條件下驗證“模型” > > >> 與“模型”的解析解進行比較

> > >> Simulation:  > > >> 模擬:
> > >> Cheap (typically)  > > >> 便宜(通常)
> > >> Computer programming, software package
> > >> 電腦程式設計,軟體套件

> > >> Acceptable but not satisfactory
可接受但不令人滿意

> > >> Can verify the “model” under arbitrary conditions
> > >> 可以在任意條件下驗證“模型”

> > >> Good for engineers (CAD and optimization)
> > >> 對工程師有利(計算機輔助設計和優化)

MEMS Modeling 6 MEMS 建模 6

Modeling vs. Simulation ?
建模與模擬?

  • Modeling and Simulation bind together
    建模與模擬緊密結合

    > > >> Typical approach  > > >> 典型方法
  • Modeling with the support of simulations
    利用模擬進行建模

    > > >> Insufficient modeling works result in insufficient understanding of the physical systems
    > > >> 模型建構不足導致對物理系統的理解不足

    > > >> may apply wrong GEs, BCs … for simulation > > >> GIGO
    > > >> 可能對模擬 > > >> 應用錯誤的 GEs、BCs … GIGO
  • Overhead of computer simulation
    電腦模擬的開銷

    > > >> approximation techniques (discretization)
    > > >> 近似技術(離散化)

    > > >> FEM, BEM, FDM …
    > > >> 有限元素法、邊界元素法、有限差分法 …

    > > >> numerical computing techniques
    > > >> 數值計算技術
Inversion technology, roots searching …
反演技術、根搜尋……

> > >> Others …  > > >> 其他…

Simulation vs. Machine Learning
模擬與機器學習

  • Both require Computers 兩者都需要電腦
  • Simulation: 模擬:
  • predict the behaviors of physical systems by specific rules/models (GEs + BCs + ICs … )
    透過特定的規則/模型(一般方程 + 邊界條件 + 初始條件……)預測物理系統的行為
  • CPU 中央處理器

> > >> Machine Learning: 機器學習:

  • models are unknown; synthesize models/rule based on given inputs/outputs.
    模型是未知的;根據給定的輸入/輸出合成模型/規則。
  • GPU 圖形處理單元

Is Modeling Essential in MEMS ?
在微機電系統中建模是否必要?

Examples of MEMS Physics
MEMS 物理的例子

SEM Picture of an RF switch
RF 開關的掃描電子顯微鏡圖片

When operating in ambient, what is the switching time?
在環境中操作時,切換時間是多少?
Assume there is no damping (in vacuum), the simulated switching time is about 10 20 μ s 10 20 μ s 10-20 mus10-20 \mu \mathrm{~s}.
假設沒有阻尼(在真空中),模擬的開關時間約為 10 20 μ s 10 20 μ s 10-20 mus10-20 \mu \mathrm{~s}
Damping is huge in microsystems
阻尼在微系統中是巨大的

MEMS Modeling 12 MEMS 模型 12

Examples of MEMS Physics
MEMS 物理的例子

micrograph of an optical modulator
光學調製器的顯微照片

What’s the Resonant Frequency?
共振頻率是什麼?

If there is no damping (in vacuum), the simulated resonant frequency is 2.02 Mhz (FEM modal analysis)
如果沒有阻尼(在真空中),模擬的共振頻率為 2.02 MHz(有限元素法模態分析)

Typical Procedure of Circuit Design
電路設計的典型程序

Electronic Design Automation (EDA)
電子設計自動化 (EDA)

Modeling is essential for MEMS ?
建模對於微機電系統(MEMS)是必不可少的

以研發成本而言:
  • 製程費用及人力成本高
電腦模擬所需的設備只有電腦及相關軟體
部份原本需要經由賽際製程"嘗試錯誤"的步驟,可經由電腦模擬而省略 rarr\rightarrow 大大降低研發成本。
部分原本需要經由賽際製程「嘗試錯誤」的步驟,可經由電腦模擬而省略 rarr\rightarrow 大大降低研發成本。

> > >> 以產品性能而言:
> > >> 產品性能上稍許的(marginal)差别就可能是此產品是否能提高市場佔有率或在市場生存的關鍵。
產品性能上稍許的差別就可能是此產品是否能提高市場佔有率或在市場生存的關鍵。

可經由電腦輔助設計及模擬,有效率地找出最佳性能的設計。

Modeling is essential for MEMS ?
建模對於微機電系統(MEMS)是必不可少的

> > >> 以設計效率而言:
在三個月至半年之内即必須推出下一代的設計,才能維持市場上的競爭力。
在三個月至半年之內即必須推出下一代的設計,才能維持市場上的競爭力。

沒有電腦的輔助,"嘗試錯誤"的製程次數會大大增加,勢必會延長新產品設計週期。
以系統整合而言:
一個完整的微機電系統,微機械装置與感測控制電路必需整合後才能判斷整體的性能。
一個完整的微機電系統,微機械裝置與感測控制電路必須整合後才能判斷整體的性能。

> > >> 由於半導體積體電路的設計早已完全採用電腦輔助的方式,所有電路的特性皆可電路計算程式模擬產生。
由於半導體積體電路的設計早已完全採用電腦輔助的方式,所有電路的特性皆可透過電路計算程式模擬產生。

結合微機電元件與電路元件模型,採用既有的電路計算程式來模擬整體系統,是明確的發展趨勢。

Classification of MEMS Modeling
MEMS 建模的分類

  • Process Level 過程層級
  • Process simulation 過程模擬
  • Process emulation 過程模擬
  • Device Physical Level 裝置物理層
  • Device Behavior Level 裝置行為層級
  • System Level 系統層級

LAYOUT EDITOR 佈局編輯器

Ability to import layout data from standard commercial layout CAD packages, i.e. Cadence, Mentor, etc. GDSII, CIF, DXF, IGES
能夠從標準商業佈局 CAD 套件中導入佈局數據,即 Cadence、Mentor 等。GDSII、CIF、DXF、IGES

files in- and out
進出文件

Non-Manhattan layout supported including “true” curves Layout generators
非曼哈頓佈局支援,包括“真”曲線佈局生成器

PROCESS DESCRIPTION 過程描述

Process Description Editor is
過程描述編輯器是

Flexible Multi Process 靈活多處理器
Emulator of: 模擬器:
Surface & Bulk Micromachining, LIGA, etc.
表面與體積微加工、LIGA 等。

Not a physical simulation
不是物理模擬

Material Property Database
材料性質數據庫

User Measured Values 使用者測量值
Foundry Database Available Basic Database Provided
鑄造數據庫可用 基本數據庫提供

3-D solid modeling 三維實體建模
Layout 佈局

Process Level 過程層級

Device Physical Level 裝置物理層
FEM/FDM/BEM field simuations
有限元素法/有限差分法/邊界元素法場模擬

Multi-physics, coupled-energy domain
多物理場,耦合能量領域

Device Behavior Level 裝置行為層級
System Level 系統層級

Device Physical Level Simulation
裝置物理層級模擬

  • Device Performance Simulation/Multi-Physics Simulation/Coupled Fields Analysis
    裝置性能模擬/多物理場模擬/耦合場分析
  • Energy Domains: Thermal, Mechanical, Electrical, Magnetic, Fluidic, Optical, Chemical … Domains
    能量領域:熱能、機械能、電能、磁能、流體能、光學能、化學能……領域
  • Single Domains Simulation via Existing Specific Simulation Tools
    透過現有特定模擬工具進行單一領域模擬
  • Multi-Physics Simulations Tools
    多物理場模擬工具
  • Direct Coupling 直接耦合
    > > >> e.g. piezoelectric analysis
    例如壓電分析
Fully-coupled Newton methods for Nonlinear Problems
完全耦合的牛頓方法用於非線性問題
  • Sequential or Indirect Coupling
    序列或間接耦合

    > > >> Relaxation Method  > > >> 放鬆方法
Surface Newton’s Method 表面牛頓法
Multi-Newton’s Method 多牛頓法
Benefits: Combining with the existence of commercially-available single
好處:結合現有的商業可用單一

domain (black-box approach)
領域(黑箱方法)

FEM and BEM Solvers
有限元素法與邊界元素法求解器

FEM 有限元素法

> > >> finite element method
有限元素法
meshing the volume of the computational domain
網格化計算域的體積

> > >> mature and widely used in industries
> > >> 成熟且廣泛應用於各行各業

> > >> applications:  > > >> 應用:
> > >> Mechanical, Fluid and Thermal solvers. BEM
機械、流體和熱解算器。邊界元素法

> > >> boundary element method
邊界元素法

> > >> meshing the boundary of computational domain
> > >> 網格化計算域的邊界

> > >> applications:  > > >> 應用:

Electrostatics including dielectrics.
靜電學包括介電材料。

Coupled Electrostatics-Mechanics Solver
耦合靜電學-力學求解器

Force depends on Movable Geometry
力依賴於可動幾何學

Charge re-distribution with mechanical deformation FEM and BEM Combination avoids remeshing
機械變形下的電荷重分佈有限元素法與邊界元素法結合避免了重新網格化

Coupled Electrostatics-Mechanics Solver TI micromirrrors
耦合電靜力學-機械解算器 TI 微鏡
Externat Surface 外部表面
Contours 輪廓

Elements in FEM 有限元素法中的元素

  • Choose Proper Elements For Analysis (Closely Related to Accuracy and Efficiency)
    選擇適當的分析元素(與準確性和效率密切相關)
  • Family 家庭
  • Degrees of Freedom (directly related to element family)
    自由度(直接與元素家族相關)
  • Shapes: Tetraheral, Wedge (triangular prism), Hexahedron (brick)
    形狀:四面體、楔形(三角柱)、六面體(磚)
  • Number of Nodes (Linear, quadratic or high-order elements)
    節點數(線性、二次或高階元素)
  • Quality of Meshing: Aspect Ratio, Distorsion
    網格質量:長寬比,變形
  • Formulation 配方
  • Integration (Full or reduced integration)
    整合(完全整合或部分整合)

Process Level 過程層級

Device Physical Level 裝置物理層
Device Behavior Level 裝置行為層級
Macromodels 巨型模型
model order reduction 模型階數縮減
System Level 系統層級

Device Behavior Level 裝置行為層級

  • Macro-Model (Compact Model, Reduced Order Model) of MEMS Device for System Level Simulation
    MEMS 設備的宏觀模型(緊湊模型、降階模型)用於系統級模擬
  • How to get an approximate model (ODE’s or DAE’s) from an field domain model (PDE’s)?
    如何從場域模型(偏微分方程)獲得近似模型(常微分方程或微分代數方程)?

Types of Macromodels 巨型模型的類型

  • Signal flow approach 信號流方法
  • Transfer functions 傳遞函數
  • Matlab, simulink Matlab,Simulink
  • Power flow approach 功率流方法
  • Spice compitable 香料相容性
  • Saber with MAST AHDL
    MAST AHDL 的劍
  • Spectre with Verilog-A AHDL
    使用 Verilog-A AHDL 的 Spectre
  • ELDO with HDL-A ELDO 與 HDL-A
  • IEEE standard 1076.1: VHDL-AMS (Very High Speed Integrated Circuit HDL-Analog Mixed Signal)
    IEEE 標準 1076.1:VHDL-AMS(非常高速集成電路硬體描述語言-類比混合信號)

Why macro-models (reduced order models) ?
為什麼使用宏觀模型(降階模型)?

  • Efficient (fast) simulation of accurate and physically-correct models.
    高效(快速)模擬準確且物理正確的模型。
Transient and spectral analysis
瞬態與頻譜分析
  • Efficient (fast) simulation of a whole MEMS device including sensing, driving, controlling circuitry and μ μ mu\mu Fluidics components
    高效(快速)模擬整個 MEMS 裝置,包括感測、驅動、控制電路和流體元件
Transient and spectral analysis
瞬態與頻譜分析
Reduce the DOF of the system from tens of thousands (FEM/BEM approaches) to a much lower DOF
將系統的自由度從數萬(有限元素法/邊界元素法)降低到更低的自由度
  • Lumped-element method 集中元件法
  • Modal analysis (modal decomposition)
    模態分析(模態分解)
  • Galerkin-based method 伽勒金法
  • Arnoldi-based method 阿諾德利方法
Process Level 過程層級
Device Physical Level 裝置物理層
Device Behavior Level 裝置行為層級
System Level 系統層級
SPICE
Simulink
Saber 
. . . .
System-level model (Saber, HDL): VCO with MEMS components
系統級模型(Saber,HDL):具有 MEMS 元件的 VCO

System-level model (Simulink, Matlab):
系統級模型(Simulink,Matlab):

RF switch with nonlinear damping effect
具有非線性阻尼效應的射頻開關

Typical Design Flow 典型設計流程

(bottom-up approach) (自下而上方法)

Optical MEMS System Modeling
光學微機電系統建模

Modules of a Typical MEMS Modeling Software
典型 MEMS 建模軟體的模組

  • Layout Editor 佈局編輯器
  • Capacitance Solver 電容解算器
  • Mechanics 力學
Modal and Harmonic Analyses
模態與和聲分析

Contact Mechanics with Hysteresis
接觸力學與滯後現象
  • Coupled Electro-Mechanical Analysis
    耦合電機械分析
Automatic Electrostatic Pull-in Analysis
自動靜電吸引分析

Electrostatic Spring Softening Effects
靜電彈簧軟化效應
  • Thermo-Mechanical Analysis
    熱機械分析
  • Visualization (post process)
    可視化(後處理)

Modules of a Typical MEMS Modeling Software
典型 MEMS 建模軟體的模組

  • Piezo-electric/resistive analysis
    壓電/電阻分析

    . Electro-Thermo-Mechanical Analysis
    電熱機械分析
  • Damping 阻尼
Squeeze film damping 擠壓薄膜阻尼
Lateral damping 側向阻尼
  • High frequency effects 高頻效應
Inductance and Resistance
電感與電阻
  • Optical 光學
  • Packaging Analysis 包裝分析
  • Automatic macromodel (HDL) Generation
    自動宏模型(HDL)生成
  • System Level Simulation 系統級模擬

Infrared Detecting Technologies:
紅外線檢測技術:

Bolometers, Thermopiles and QWIPs
波洛米特、熱電堆和量子點光電探測器
Yao-Joe Yang (楊燿州), Professor
楊燿州教授

Department of Mechanical Engineering
機械工程系

National Taiwan University
國立臺灣大學

Fig. 14. IR inage of tank produced with 512 × 512 512 × 512 512 xx512512 \times 512 scence generator aray (image viewed with IR camera)
圖 14. 使用 512 × 512 512 × 512 512 xx512512 \times 512 場景生成器陣列製作的坦克的紅外影像(使用紅外相機查看的影像)

Fig. 13. IR image with 240 × 336 240 × 336 240 xx336240 \times 336 microbolometer camera
圖 13. 使用 240 × 336 240 × 336 240 xx336240 \times 336 微熱計相機的紅外圖像

Outline 大綱

Introduction to Infrared Detectors
紅外探測器簡介

Description of Three Types of Infrared Detectors
三種紅外線探測器的描述

> > >> thermal detectors :
> > >> 熱檢測器:
  • Honeywell Bolometer 霍尼韋爾波洛米特

* JPL Thermopile * JPL 熱電堆

> > >> photon detector: * JPL QWIP
> > >> 光子探測器:* JPL QWIP
Performance Index 績效指標
Comparison and Applications
比較與應用

What is 什麼是

Infrared Detectors 紅外探測器

Thermal Radiation : 熱輻射:

radiation emitted by any object at a rate and a wavelength distribution determined by the temperature of the object
任何物體以其溫度所決定的速率和波長分佈發射的輻射

> > >> thermal radiation through atmosphere is attenuated by scattering and absorption process
> > >> 熱輻射在大氣中受到散射和吸收過程的衰減
Why Infrared (IR) Detecting
為什麼使用紅外線(IR)檢測

> > >> maximum radiation occurs around waveband of 2 - 15 μ m 15 μ m 15 mum15 \mu \mathrm{~m}
> > >> 最大輻射發生在波段 2 - 15 μ m 15 μ m 15 mum15 \mu \mathrm{~m} 附近


number of photons and emission power vs. wavelength
光子數量與發射功率對波長的關係

What is 什麼是

Infrared Detectors 紅外探測器

Why Infrared (IR) Detecting (cont.)
為什麼紅外線(IR)檢測(續)

> > >> less scattering  > > >> 較少散射
  • infrared can penetrate the atmosphere further than visible light because the wavelength is longer.
    紅外線能夠比可見光更深入地穿透大氣,因為其波長較長。

    > > >> Two infrared windows with low absorption by gas molecules:
    兩個對氣體分子吸收率低的紅外窗口:
  • 3 5 μ m 3 5 μ m 3-5mum3-5 \mu \mathrm{~m} and 8-14 μ m μ m mum\mu \mathrm{m}  3 5 μ m 3 5 μ m 3-5mum3-5 \mu \mathrm{~m} 和 8-14 μ m μ m mum\mu \mathrm{m}

Thermal Detectors 熱檢測器

Thermal Detectors 熱檢測器
> > >> two-stage transducers
> > >> 雙階轉換器

& radiation absorbing & 輻射吸收
photon energy is converted to thermal energy in the absorber
光子能量在吸收體中轉換為熱能
  • temperature measurement 溫度測量
    temperature change is converted to an electrical signal by temperature measurement mechanism
    溫度變化通過溫度測量機制轉換為電信號


    temperature measure mechanisms determine the types of thermal detectors
    溫度測量機制決定了熱檢測器的類型

Thermal Detectors 熱檢測器

Types of Thermal Detectors
熱檢測器的類型

> > >> all of them have radiation absorbers, but have different types of temperature measurement mechanisms
> > >> 它們都有輻射吸收器,但擁有不同類型的溫度測量機制
Type 類型 Measured property 測量屬性
Bolometers 波洛米特 Electrical resistance 電阻
Pyroelectric detectors 熱電偵測器 Electrical polarization 電極化
Thermopiles 熱電堆 Seebeck voltage 塞貝克電壓
Golay cell 高萊單元 Gas pressure 氣壓
Bi-material 雙材料 Bending deflection 彎曲撓度
Type Measured property Bolometers Electrical resistance Pyroelectric detectors Electrical polarization Thermopiles Seebeck voltage Golay cell Gas pressure Bi-material Bending deflection| Type | Measured property | | :--- | :--- | | Bolometers | Electrical resistance | | Pyroelectric detectors | Electrical polarization | | Thermopiles | Seebeck voltage | | Golay cell | Gas pressure | | Bi-material | Bending deflection |

Photon Detectors 光子探測器

Photon Detectors 光子探測器
  • IR photons excite electrons to higher energy states and thus modulate some electronic property of the sensor.
    紅外光子使電子激發至更高的能量狀態,從而調節傳感器的某些電子特性。

    The energy of an incident photon must be high enough to excite an electron to an available state.
    入射光子的能量必須足夠高,以激發電子至可用狀態。

    To avoid large background signals and noise due to thermal carrier excitation, the sensor has to be cooled to cryogenic temperatures.
    為了避免由於熱載流子激發而產生的大背景信號和噪聲,傳感器必須冷卻至低溫。

Thermal Detectors 熱檢測器

Types of Photon Detectors
光子探測器的類型
TYPE Transition 過渡 Electrical output 電輸出 Example 範例
Intrinsic 內在的 Interband 帶間

光導電光伏電容 PEM
Photoconductive
Photovoltaic
Capacitance
PEM
Photoconductive Photovoltaic Capacitance PEM| Photoconductive | | :--- | | Photovoltaic | | Capacitance | | PEM |
PbS, InSb, HgCdTe
PbTe , InSb , HgCdTe PbTe , InSb , HgCdTe PbTe,InSb,HgCdTe\mathrm{PbTe}, \mathrm{InSb}, \mathrm{HgCdTe}
InSb, HgCdTe
InSb, HgCdTe
PbS, InSb, HgCdTe PbTe,InSb,HgCdTe InSb, HgCdTe InSb, HgCdTe| PbS, InSb, HgCdTe | | :--- | | $\mathrm{PbTe}, \mathrm{InSb}, \mathrm{HgCdTe}$ | | InSb, HgCdTe | | InSb, HgCdTe |
Extrinsic 外在的 Impurity to band 雜質到帶 Photoconductive 光導電的 Si:In, Si:Ga
Free Carriers 自由載體 Intraband 內帶

光發射光伏
Photoemissive
Photovoltaic
Photoemissive Photovoltaic| Photoemissive | | :--- | | Photovoltaic |
PtSi, IrSi, GaAs/CsO InSb
QWIPs 量子點光子檢測器 Between bound levels 在界限層級之間

光導電光伏
Photoconductive
Photovoltaic
Photoconductive Photovoltaic| Photoconductive | | :--- | | Photovoltaic |
HgTe/CdTe, GaAs/AlGaAs
InSb/InAsSb
HgTe/CdTe, GaAs/AlGaAs InSb/InAsSb| HgTe/CdTe, GaAs/AlGaAs | | :--- | | InSb/InAsSb |
TYPE Transition Electrical output Example Intrinsic Interband "Photoconductive Photovoltaic Capacitance PEM" "PbS, InSb, HgCdTe PbTe,InSb,HgCdTe InSb, HgCdTe InSb, HgCdTe" Extrinsic Impurity to band Photoconductive Si:In, Si:Ga Free Carriers Intraband "Photoemissive Photovoltaic" PtSi, IrSi, GaAs/CsO InSb QWIPs Between bound levels "Photoconductive Photovoltaic" "HgTe/CdTe, GaAs/AlGaAs InSb/InAsSb"| TYPE | Transition | Electrical output | Example | | :---: | :---: | :---: | :---: | | Intrinsic | Interband | Photoconductive <br> Photovoltaic <br> Capacitance <br> PEM | PbS, InSb, HgCdTe <br> $\mathrm{PbTe}, \mathrm{InSb}, \mathrm{HgCdTe}$ <br> InSb, HgCdTe <br> InSb, HgCdTe | | Extrinsic | Impurity to band | Photoconductive | Si:In, Si:Ga | | Free Carriers | Intraband | Photoemissive <br> Photovoltaic | PtSi, IrSi, GaAs/CsO InSb | | QWIPs | Between bound levels | Photoconductive <br> Photovoltaic | HgTe/CdTe, GaAs/AlGaAs <br> InSb/InAsSb |
HgCdTe has the best sensitivity of IR absorption, but its low fabrication process yield has not been solved even after about 40 years since the first device was made.
HgCdTe 具有最佳的紅外吸收敏感度,但自從約 40 年前製造出第一個裝置以來,其低製造過程產量的問題仍未解決。
Basic Heat Transfer Analysis for Thermal
基本熱傳遞分析
Detectors 檢測器
Thermal Detectors 熱檢測器
  • Heat Flow Equation : 熱流方程:
C d Δ T d t + G Δ T = η P 0 e j ω t C d Δ T d t + G Δ T = η P 0 e j ω t C(d Delta T)/(dt)+G Delta T=etaP_(0)e^(j omega t)C \frac{d \Delta T}{d t}+G \Delta T=\eta P_{0} e^{j \omega t}
  • Solution : 解決方案:
| Δ T | = η P 0 G ( 1 + ω 2 τ 2 ) 1 / 2 | Δ T | = η P 0 G 1 + ω 2 τ 2 1 / 2 |Delta T|=(etaP_(0))/(G(1+omega^(2)tau^(2))^(1//2))|\Delta T|=\frac{\eta P_{0}}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
-Thermal time constant τ = C / G τ = C / G tau=C//G\tau=C / G
-熱時間常數 τ = C / G τ = C / G tau=C//G\tau=C / G

Basic Heat Transfer 基本熱傳遞

Analysis for Thermal 熱分析

Detectors 檢測器
Bolometer 波洛米特
A bolometer measures temperature changes via temperature dependent resistance of a resistor which is in thermal contact with the absorber
一種輻射計通過與吸收體熱接觸的電阻的溫度依賴性電阻來測量溫度變化
Δ R = α R Δ T Δ R = α R Δ T Delta R=alpha R Delta T\Delta R=\alpha R \Delta T
Assume constant current flowing across the resistor
假設恆定電流流經電阻器
V s = i b Δ R = i b α R Δ T = i b α R η P 0 G ( 1 + ω 2 τ 2 ) 1 / 2 V s = i b Δ R = i b α R Δ T = i b α R η P 0 G 1 + ω 2 τ 2 1 / 2 V_(s)=i_(b)Delta R=i_(b)alpha R Delta T=(i_(b)alpha R etaP_(0))/(G(1+omega^(2)tau^(2))^(1//2))V_{s}=i_{b} \Delta R=i_{b} \alpha R \Delta T=\frac{i_{b} \alpha R \eta P_{0}}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
The responsivity R R R\boldsymbol{R} of an IR pixel is defined as the output signal (voltage or current) divided by the input radiant power falling on the pixel
紅外像素的響應度 R R R\boldsymbol{R} 定義為輸出信號(電壓或電流)除以落在像素上的輸入輻射功率
R = i b α R η G ( 1 + ω 2 τ 2 ) 1 / 2 R = i b α R η G 1 + ω 2 τ 2 1 / 2 R=(i_(b)alpha R eta)/(G(1+omega^(2)tau^(2))^(1//2))\boldsymbol{R}=\frac{i_{b} \alpha R \eta}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
Basic Heat Transfer Analysis for
基本熱傳遞分析

Thermal Detectors 熱檢測器

Thermoplie 熱電堆

Thermopile is a series of thermocouples, which apply the Seebeck effect to measure temperature
熱電堆是一系列熱電偶,利用塞貝克效應來測量溫度
V s = N ( S 1 S 2 ) Δ T V s = N S 1 S 2 Δ T V_(s)=N(S_(1)-S_(2))Delta TV_{s}=N\left(S_{1}-S_{2}\right) \Delta T
Assume constant current flowing across the resistor
假設恆定電流流經電阻器
R = η N ( S 1 S 2 ) G ( 1 + ω 2 τ 2 ) 1 / 2 R = η N S 1 S 2 G 1 + ω 2 τ 2 1 / 2 R=(eta N(S_(1)-S_(2)))/(G(1+omega^(2)tau^(2))^(1//2))\boldsymbol{R}=\frac{\eta N\left(S_{1}-S_{2}\right)}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
A quad\quad  quad\quad
Detecting 檢測
Junction 交匯點
Detecting Junction| Detecting | | :---: | | Junction |
A A AA and B B BB are two different materials Temperature difference at the two junction results in a voltage V V VV.
A A AA B B BB 是兩種不同的材料,兩個接點之間的溫度差會產生電壓 V V VV
The responsivity R R R\boldsymbol{R} of an IR pixel is defined as the output signal (voltage or current) divided by the input radiant power falling on the pixel.
紅外像素的響應度 R R R\boldsymbol{R} 定義為輸出信號(電壓或電流)除以落在像素上的輸入輻射功率。
The absorber ( Si 3 N 4 ) Si 3 N 4 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) is raised above the Si substrate, supported by two legs at diagonally opposite corners.
吸收器 ( Si 3 N 4 ) Si 3 N 4 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) 被抬高於矽基板之上,並由位於對角相對角落的兩條腿支撐。
Electronics at each pixel are embedded in the substrate.
每個像素的電子元件嵌入在基板中。
Vanadium oxide ( VO x ) VO x (VO_(x))\left(\mathrm{VO}_{x}\right) (the thermally sensitive resistive material) are deposited on the absorber.
氧化釩 ( VO x ) VO x (VO_(x))\left(\mathrm{VO}_{x}\right) (熱敏感電阻材料)被沉積在吸收體上。

In 2D array 在二維陣列中

Honeywell Bolometer: 霍尼韋爾波洛米特

Suspended absorber 懸浮吸收器
excellent thermal isolation (small G)
優異的熱隔離(小 G)

Thin membrane of absorber
吸收器的薄膜

> > >> small heat capacity (small C)
> > >> 小熱容 (小 C)

keep time constant (C/G) small but with excellent thermal isolation
保持時間常數 (C/G) 小但具有優良的熱隔離性

integrated transistor switch
集成晶體管開關

> > >> better readout performance
> > >> 更佳的讀取性能

Stress of Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} film is annoying
Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 膜的應力令人煩惱

need tremendous work to control the stress to prevent the suspended structure from tilting or touching substrate
需要大量的工作來控制壓力,以防止懸浮結構傾斜或接觸基材

> > >> Honeywell solved this problem.
霍尼韋爾解決了這個問題。

JPL Thermopile JPL 熱電堆
The 0.6 μ m 0.6 μ m 0.6 mum0.6 \mu \mathrm{~m} absorber ( Si 3 N 4 ) Si 3 N 4 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) is a microbridge membrane released by Bulk micromaching
0.6 μ m 0.6 μ m 0.6 mum0.6 \mu \mathrm{~m} 吸收器 ( Si 3 N 4 ) Si 3 N 4 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) 是一種由大規模微加工技術釋放的微橋膜

thermoelectric materials ( Bi 2 Te 3 Bi 2 Te 3 (Bi_(2)Te_(3):}\left(\mathrm{Bi}_{2} \mathrm{Te}_{3}\right. and
熱電材料 ( Bi 2 Te 3 Bi 2 Te 3 (Bi_(2)Te_(3):}\left(\mathrm{Bi}_{2} \mathrm{Te}_{3}\right.

Bi 0.55 Sb 1.45 Te 3.6 Bi 0.55 Sb 1.45 Te 3.6 Bi_(0.55)Sb_(1.45)Te_(3.6)\mathrm{Bi}_{0.55} \mathrm{Sb}_{1.45} \mathrm{Te}_{3.6} ) are deposited alternatively on both ends of the bridge
Bi 0.55 Sb 1.45 Te 3.6 Bi 0.55 Sb 1.45 Te 3.6 Bi_(0.55)Sb_(1.45)Te_(3.6)\mathrm{Bi}_{0.55} \mathrm{Sb}_{1.45} \mathrm{Te}_{3.6} )交替地沉積在橋的兩端
A gold interconnect connects the two thermocouples groups on both ends
一條金屬互連連接了兩端的兩組熱電偶

Au / Ti Au / Ti Au//Ti\mathrm{Au} / \mathrm{Ti} contacts are used for connecting different materials.
Au / Ti Au / Ti Au//Ti\mathrm{Au} / \mathrm{Ti} 接觸點用於連接不同的材料。

JPL Thermopile: JPL 熱電堆:

Characteristic 特徵
Thin Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} bridge made by bulk micromachining - fair thermal isolation
Si 3 N 4 Si 3 N 4 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 橋樑由大宗微機械加工製成 - 良好的熱隔離
11 thermocouple elements for each pixel
每個像素有 11 個熱電偶元件

> > >> increase responsivity
> > >> 增加反應性

> > >> trade-off between thermal isolation design and number of thermocouples very simple electronics
熱隔離設計與熱電偶數量之間的權衡非常簡單的電子設備

> > >> self-generating Seebeck effect, readout circuit is very simple
自生成的塞貝克效應,讀取電路非常簡單

special backside KOH etching
特殊背面氫氧化鉀蝕刻

> > >> Need special etching fixture to protect the device during etching
> > >> 需要特殊的蝕刻夾具以保護設備在蝕刻過程中

> > >> if membranes break during etching, the KOH will damage the thermoelectric material in the front side
如果在蝕刻過程中膜破裂,氫氧化鉀將損壞前側的熱電材料

Brief Quantum Mechanics 簡明量子力學
Background in QWIPs QWIPs 的背景

intersubband absorption mechanism
子帶間吸收機制

> > >> transition between energy levels within the conduction (or valence) band
> > >> 在導電帶(或價帶)內的能量級之間的轉變

> > >> photoionized electrons are collected by a small bias applied on both side of the well
> > >> 照射電離的電子是通過施加在井兩側的小偏壓來收集的

superlattice structure of AIGaAs/GaAs
AIGaAs/GaAs 超晶格結構
a stack of quantum wells in order to generate more photoionizied electrons
一堆量子井以產生更多光電離電子

Brief Quantum Mechanics 簡明量子力學

Background in QWIPs QWIPs 的背景
For infinite-high-barrier well, the
對於無限高障礙井,

energy level is given by
能量水平由以下公式給出
E n = n 2 2 π 2 2 m L w 2 E n = n 2 2 π 2 2 m L w 2 E_(n)=n^(2)(ℏ^(2)pi^(2))/(2m^(**)L_(w)^(2))E_{n}=n^{2} \frac{\hbar^{2} \pi^{2}}{2 m^{*} L_{w}^{2}}
The transition energy between ground state and the first excited level is
基態與第一激發態之間的躍遷能量是
E 2 E 1 = 3 2 π 2 2 m L w 2 E 2 E 1 = 3 2 π 2 2 m L w 2 E_(2)-E_(1)=(3ℏ^(2)pi^(2))/(2m^(**)L_(w)^(2))E_{2}-E_{1}=\frac{3 \hbar^{2} \pi^{2}}{2 m^{*} L_{w}^{2}}
by changing the quantum-well width L w L w L_(w)L_{w} this intersubband transition energy can be varied over a wide range of wavelength (2 20 μ m μ m mum\mu \mathrm{m} ).
透過改變量子井的寬度 L w L w L_(w)L_{w} ,此種子帶間的躍遷能量可以在廣泛的波長範圍內變化(2 20 μ m μ m mum\mu \mathrm{m} )。

Three Intersubband Transition
三重子帶間躍遷

Types of QWIPs QWIP 的類型
Bound-to-bound 邊界到邊界
> > >> narrow absorption spectrum
> > >> 狹窄吸收光譜

> > >> need higher bias voltage to collect photoexcited electrons; high dark current
> > >> 需要更高的偏壓電壓來收集光激發的電子;高暗電流
Bound-to-continuum 綁定於連續體
> > >> wide absorption spectrum
> > >> 寬吸收光譜

> > >> need lower bias voltage, lower dark current than B-to-B
> > >> 需要比 B-to-B 更低的偏壓和更低的暗電流

> > >> better design than B-to-B
> > >> 比 B-to-B 更好的設計

Bound-to-quasibound 束縛至準束縛
> > >> better design than bound-tocontinuum --> next viewgraph
> > >> 比連續體更好的設計 --> 下一張幻燈片


Comparison of B-to-B and
B2B 與 B2C 的比較

B-to-QB Designs B-to-QB 設計
QWIP’s killer : dark current
QWIP 的致命因素:暗電流

Thermionic emission dark current is the major portion of dark noise as T > 45 K
熱電子發射暗電流是當溫度高於 45 K 時暗噪聲的主要部分

for the bound-to-continuum design, the E T E T E_(T)\mathrm{E}_{\mathrm{T}} is lower than E p E p E_(p)E_{p}, thermionic emission is obvious
對於束縛於連續體設計, E T E T E_(T)\mathrm{E}_{\mathrm{T}} 低於 E p E p E_(p)E_{p} ,熱電子發射明顯

for the bound-to-quasibound design, E T = E P E T = E P E_(T)=E_(P)\mathrm{E}_{\mathrm{T}}=\mathrm{E}_{\mathrm{P}}, so the barrier for the thermionic emission is higher at the same temperature, thus reduces the dark current
對於束縛到準束縛的設計, E T = E P E T = E P E_(T)=E_(P)\mathrm{E}_{\mathrm{T}}=\mathrm{E}_{\mathrm{P}} ,因此在相同溫度下,熱電子發射的障礙較高,從而降低了暗電流
Since E p E p E_(p)E_{p} of B-to-QB is right on the top of the well, need similar bias voltage as the B-to-C case
由於 E p E p E_(p)E_{p} 的 B 到 QB 正好位於井的頂部,因此需要類似於 B 到 C 情況的偏壓電壓


L w 2 L w 2 L_(w2)\mathrm{L}_{\mathrm{w} 2}

L w 3 L w 3 L_(w3)\mathrm{L}_{\mathrm{w} 3}

Absorption vs. Wavelength
吸收與波長
Normalized absorption vs.
標準化吸收與

wavelength 波長
B-to-C is much broader than B-to-B and B B BB-to-QB because of more delocalized excited state.
B-to-C 的範疇遠比 B-to-B 和 B B BB -to-QB 更廣,因為其激發態更為去局部化。
Due to conservation of integrated oscillator strength, the absorption coefficient of the B B BB-to-C is lower than those of B-to-B and B-to-QB.
由於整合振盪強度的守恆, B B BB 到 C 的吸收係數低於 B 到 B 和 B 到 QB 的吸收係數。


JPL QWIP

Superlattice structure of 50 periods of 6.5 nm well of GaAs and 60 nm barrier of A l 0.15 G a 0.85 A l 0.15 G a 0.85 Al_(0.15)Ga_(0.85)\mathbf{A l}_{0.15} \mathbf{G a}_{0.85} As
50 個周期的 6.5 納米 GaAs 井和 60 納米 A l 0.15 G a 0.85 A l 0.15 G a 0.85 Al_(0.15)Ga_(0.85)\mathbf{A l}_{0.15} \mathbf{G a}_{0.85} As 障礙的超晶格結構
The superlattice is sandwiched between 0.5
超晶格夾在 0.5 之間

GaAs substrate GaAs 基板

JPL QWIP:

Bound-to-quasibound design
束縛至準束縛設計
reduce dark current 降低暗電流
mature GaAs MBE fabrication process
成熟的砷化鎵分子束外延製程

> 128 × 128 > 128 × 128 > 128 xx128>128 \times 128 array  > 128 × 128 > 128 × 128 > 128 xx128>128 \times 128 陣列
> > >> very uniform superlattice ( 0.1 % non-uniformity)
> > >> 非常均勻的超晶格 (0.1% 非均勻性)

very high yield ( 99.9 % 99.9 % 99.9%99.9 \% )
非常高的產量 ( 99.9 % 99.9 % 99.9%99.9 \% )

hybrid readout electronics
混合讀出電子學

> > >> CMOS multiplexer is bonded to the array
> > >> CMOS 多路複用器與陣列連接

> > >> expensive but not optimized
> > >> 昂貴但未經優化

random reflector design 隨機反射器設計
> > >> a factor of eight enhancement in responsivity compared with 45 45 45^(@)45^{\circ} illumination of test structure. (to be explained)
> > >> 45 45 45^(@)45^{\circ} 測試結構的照明相比,響應性增強了八倍。
Periodic grating 週期性光柵
Previous approach 先前的方法
> > >> all the incident radiation escape after the second reflection from the grating surface
> > >> 所有的入射輻射在第二次從光柵表面反射後逃逸

> > >> A factor of 2 or 3 responsivity enhancement compared to the 45 45 45^(@)45^{\circ} illumination geometry
相較於 45 45 45^(@)45^{\circ} 照明幾何,響應增強的因素為 2 或 3 倍

(a) GRating PIXELMESA


JPL QWIP:

Light Coupling 光耦合

Random reflector 隨機反射器
> > >> The random structure on top of the detector prevents the light from being diffracted normally backward after the second bounce
隨機結構位於探測器上,防止光在第二次反射後正常向後衍射

> > >> light is scattered at a different random angle and the only chance to escape out of the detector is when reflected toward the surface within the critical angle of the normal ( 17 17 17^(@)17^{\circ} for the GaAs/Air interface)
> > >> 光以不同的隨機角度散射,只有在反射向表面並位於法線的臨界角內時( 17 17 17^(@)17^{\circ} 對於 GaAs/空氣界面),才有機會逃出檢測器

> > >> a factor of 8 responsivity enhancement compared with 45 45 45^(@)45^{\circ} illumination face case
> > >> 45 45 45^(@)45^{\circ} 照明面案例相比,響應度增強的因素為 8
RANDOM REFLECTOR 隨機反射器
Normalized Detectivity ( D D D^(**)D^{*} )
標準化檢測能力 ( D D D^(**)D^{*} )

> D = 1 / N E P > D = 1 / N E P > D=1//NEP>D=1 / N E P; NEP : noise equivalent power
> D = 1 / N E P > D = 1 / N E P > D=1//NEP>D=1 / N E P ; NEP : 噪聲等效功率

> D = ( A B ) 1 / 2 D > D = ( A B ) 1 / 2 D > D^(**)=(AB)^(1//2)D>D^{*}=(A B)^{1 / 2} D; normalized to square root of area and bandwidth
> D = ( A B ) 1 / 2 D > D = ( A B ) 1 / 2 D > D^(**)=(AB)^(1//2)D>D^{*}=(A B)^{1 / 2} D ;標準化為面積和帶寬的平方根

> > >> the less the noise, the higher the detectivity
噪音越小,檢測能力越高

Noise Equivalent Temperature Difference ( NETD )
噪聲等效溫度差 (NETD)

> > >> Change in temperature of a large thermal radiating object makes the detector’s signal-to-noise ratio equals to one
> > >> 大型熱輻射物體的溫度變化使檢測器的信號與噪聲比等於一

> > >> the smallest resolvable temperature difference of the radiating object by the detector
> > >> 探測器可解析的輻射物體的最小可解析溫度差

Comparison of Key Parameters
關鍵參數的比較

 霍尼韋爾波洛米特
Honeywell
Bolometer
Honeywell Bolometer| Honeywell | | :---: | | Bolometer |
 JPL 熱電堆
JPL
Thermopile
JPL Thermopile| JPL | | :---: | | Thermopile |
JPL
QWIP
JPL QWIP| JPL | | :---: | | QWIP |
NETD 39.4 mK 39.4 毫開爾文 N/A 抱歉,您沒有提供任何文本供翻譯。請提供需要翻譯的內容 30 mK
D D D^(**)\mathbf{D}^{*} 1 × 10 9 1 × 10 9 1xx10^(9)1 \times 10^{9} (est) 1.4 × 10 9 1.4 × 10 9 1.4 xx10^(9)1.4 \times 10^{9} 1.6 × 10 10 1.6 × 10 10 1.6 xx10^(10)1.6 \times 10^{10}
τ τ tau\tau 15 ms 15 毫秒 99 ms 99 毫秒

快速(至少 5 毫秒 ) ) ))
Fast
(at least 5 ms ) ) ))
Fast (at least 5 ms)| Fast | | :---: | | (at least 5 ms$)$ |
R R R\boldsymbol{R} 70000 V / W 70000 V / W 70000V//W70000 \mathrm{~V} / \mathrm{W} 1000 V / W 1000 V / W 1000V//W1000 \mathrm{~V} / \mathrm{W}
560 mA / W 560 mA / W 560mA//W560 \mathrm{~mA} / \mathrm{W}
( @ V B = 4 V ) @ V B = 4 V (@V_(B)=4(V))\left(@ \mathrm{~V}_{\mathrm{B}}=4 \mathrm{~V}\right)
560mA//W (@V_(B)=4(V))| $560 \mathrm{~mA} / \mathrm{W}$ | | :---: | | $\left(@ \mathrm{~V}_{\mathrm{B}}=4 \mathrm{~V}\right)$ |
 陣列均勻性
Array
Uniformity
Array Uniformity| Array | | :---: | | Uniformity |
 由快門修正
Corrected by
shutter
Corrected by shutter| Corrected by | | :---: | | shutter |
N/A 抱歉,您沒有提供任何文本供翻譯。請提供需要翻譯的內容 0.1 % 0.1 % 0.1%0.1 \%
"Honeywell Bolometer" "JPL Thermopile" "JPL QWIP" NETD 39.4 mK N/A 30 mK D^(**) 1xx10^(9) (est) 1.4 xx10^(9) 1.6 xx10^(10) tau 15 ms 99 ms "Fast (at least 5 ms)" R 70000V//W 1000V//W "560mA//W (@V_(B)=4(V))" "Array Uniformity" "Corrected by shutter" N/A 0.1%| | Honeywell <br> Bolometer | JPL <br> Thermopile | JPL <br> QWIP | | :---: | :---: | :---: | :---: | | NETD | 39.4 mK | N/A | 30 mK | | $\mathbf{D}^{*}$ | $1 \times 10^{9}$ (est) | $1.4 \times 10^{9}$ | $1.6 \times 10^{10}$ | | $\tau$ | 15 ms | 99 ms | Fast <br> (at least 5 ms$)$ | | $\boldsymbol{R}$ | $70000 \mathrm{~V} / \mathrm{W}$ | $1000 \mathrm{~V} / \mathrm{W}$ | $560 \mathrm{~mA} / \mathrm{W}$ <br> $\left(@ \mathrm{~V}_{\mathrm{B}}=4 \mathrm{~V}\right)$ | | Array <br> Uniformity | Corrected by <br> shutter | N/A | $0.1 \%$ |

Dimensions 維度

JPL THERMOPILE JPL 熱電堆 DIMENSIONS
Pixel size 像素大小 1500 μ m × 71 μ m × 0.6 μ m 1500 μ m × 71 μ m × 0.6 μ m 1500 mumxx71 mumxx0.6 mum1500 \mu \mathrm{~m} \times 71 \mu \mathrm{~m} \times 0.6 \mu \mathrm{~m}
Pitch distance 音高距離 75 μ m 75 μ m 75 mum75 \mu \mathrm{~m}
Number of pixel (linear)
像素數量(線性)
63
Number of thermocouple on one pixel
每個像素上的熱電偶數量
11
HONEYWELL BOLOMETER 霍尼韋爾波洛米特
Pixel size 像素大小 50 μ m × 50 μ m × 0.5 μ m 50 μ m × 50 μ m × 0.5 μ m 50 mumxx50 mumxx0.5 mum50 \mu \mathrm{~m} \times 50 \mu \mathrm{~m} \times 0.5 \mu \mathrm{~m}
Gap between absorber and subsrate
吸收體與基板之間的間隙
1-2 μ m μ m mum\mu \mathrm{m}
Array size 陣列大小 512 × 512 512 × 512 512 xx512512 \times 512
JPL QWIP
Pixel size 像素大小 38 μ m × 38 μ m 38 μ m × 38 μ m 38 mumxx38 mum38 \mu \mathrm{~m} \times 38 \mu \mathrm{~m}
Number of wells (superlattice)
井的數量(超晶格)
50
Pitch distance 音高距離 50 μ m 50 μ m 50 mum50 \mu \mathrm{~m}
Array size 陣列大小 128 × 128 128 × 128 128 xx128128 \times 128
JPL THERMOPILE DIMENSIONS Pixel size 1500 mumxx71 mumxx0.6 mum Pitch distance 75 mum Number of pixel (linear) 63 Number of thermocouple on one pixel 11 HONEYWELL BOLOMETER Pixel size 50 mumxx50 mumxx0.5 mum Gap between absorber and subsrate 1-2 mum Array size 512 xx512 JPL QWIP Pixel size 38 mumxx38 mum Number of wells (superlattice) 50 Pitch distance 50 mum Array size 128 xx128| JPL THERMOPILE | DIMENSIONS | | :---: | :---: | | Pixel size | $1500 \mu \mathrm{~m} \times 71 \mu \mathrm{~m} \times 0.6 \mu \mathrm{~m}$ | | Pitch distance | $75 \mu \mathrm{~m}$ | | Number of pixel (linear) | 63 | | Number of thermocouple on one pixel | 11 | | HONEYWELL BOLOMETER | | | Pixel size | $50 \mu \mathrm{~m} \times 50 \mu \mathrm{~m} \times 0.5 \mu \mathrm{~m}$ | | Gap between absorber and subsrate | 1-2 $\mu \mathrm{m}$ | | Array size | $512 \times 512$ | | JPL QWIP | | | Pixel size | $38 \mu \mathrm{~m} \times 38 \mu \mathrm{~m}$ | | Number of wells (superlattice) | 50 | | Pitch distance | $50 \mu \mathrm{~m}$ | | Array size | $128 \times 128$ |

Comparison and Discussion
比較與討論

Honeywell Bolometer 霍尼韋爾波洛米特

excellent performance, excellent integration, high potential of commercialization for civilian applications
優異的表現、卓越的整合、高度的商業化潛力以應用於民用領域

> > >> at T D = T B = 300 K T D = T B = 300 K T_(D)=T_(B)=300 KT_{D}=T_{B}=300 K and G = 1 e 7 G = 1 e 7 G=1e^(-7)G=1 e^{-7} W/K, experimental NETD=39 mK,
T D = T B = 300 K T D = T B = 300 K T_(D)=T_(B)=300 KT_{D}=T_{B}=300 K G = 1 e 7 G = 1 e 7 G=1e^(-7)G=1 e^{-7} W/K 時, > > >> ,實驗 NETD=39 mK,

> > >> the device G = 1 e 7 W / K G = 1 e 7 W / K G=1e^(-7)W//K\mathrm{G}=1 \mathrm{e}^{-7} \mathrm{~W} / \mathrm{K} is the lowest one for the working thermal detectors
> > >> 該裝置 G = 1 e 7 W / K G = 1 e 7 W / K G=1e^(-7)W//K\mathrm{G}=1 \mathrm{e}^{-7} \mathrm{~W} / \mathrm{K} 是工作熱探測器中最低的

Since G G G\mathbf{G} is very difficult to improve due to electrical interconnect, finding a material with better temperature coefficient of resistance (TCR) may be a easier way to improve the performance.
由於 G G G\mathbf{G} 因電氣互連而難以改善,尋找具有更好溫度係數的材料可能是一種更簡單的提高性能的方法。

Or, increase the filling factor (only 50 % 50 % 50%50 \% right now) to increase the Detectivity, which is proportional to square root of absorption area.
或者,增加填充因子(目前僅為 50 % 50 % 50%50 \% )以提高檢測能力,該能力與吸收面積的平方根成正比。

Comparison and Discussion
比較與討論

JPL Thermopile JPL 熱電堆

> > >> large pixel size; linear array
> > >> 大像素尺寸;線性陣列
expensive and low yield (special thermoelectric material and not compatible with CMOS process)
昂貴且產量低(特殊熱電材料,且不兼容 CMOS 工藝)

> > >> highest detectivity ( 1.4 × 10 9 cmHz 1 / 2 / W ) 1.4 × 10 9 cmHz 1 / 2 / W (1.4 xx10^(9)cmHz^(1//2)//W)\left(1.4 \times 10^{9} \mathrm{cmHz}^{1 / 2} / \mathrm{W}\right) for thermopiles,
> > >> 最高檢測能力 ( 1.4 × 10 9 cmHz 1 / 2 / W ) 1.4 × 10 9 cmHz 1 / 2 / W (1.4 xx10^(9)cmHz^(1//2)//W)\left(1.4 \times 10^{9} \mathrm{cmHz}^{1 / 2} / \mathrm{W}\right) 用於熱電堆,

> > >> fundamental limit of detectivity is 2 × 10 10 cmHz 1 / 2 / W 2 × 10 10 cmHz 1 / 2 / W 2xx10^(10)cmHz^(1//2)//W2 \times 10^{10} \mathrm{cmHz}^{1 / 2} / \mathrm{W}
> > >> 偵測能力的基本極限是 2 × 10 10 cmHz 1 / 2 / W 2 × 10 10 cmHz 1 / 2 / W 2xx10^(10)cmHz^(1//2)//W2 \times 10^{10} \mathrm{cmHz}^{1 / 2} / \mathrm{W}

> > >> key element for monochromatic detectors or spectrometers
> > >> 單色檢測器或光譜儀的關鍵元素

Fresnel zone plate Linear thermopile array
菲涅耳區域板 線性熱電堆陣列

Comparison and Discussion
比較與討論

JPL QWIP

> > >> highly uniform; excellent performance
> > >> 高度均勻;卓越的性能

> > >> dark current noise limit of QWIPs is strongly dependent on the temperature
> > >> 量子井探測器的暗電流噪聲極限與溫度有很大關聯

> > >> For longer wavelength, lower operation temperature is needed in order to push the device performance to BLIP
對於較長的波長,需要較低的操作溫度以推動設備性能達到 BLIP

> > >> operating temperature = 45 K = 45 K =45K=45 \mathrm{~K}
> > >> 操作溫度 = 45 K = 45 K =45K=45 \mathrm{~K}
integration of GaAs readout circuit is a possible way to improve (increase) the operating temperature
將 GaAs 讀出電路的整合是一種提高(增加)操作溫度的可能方法
Comparison of Applications
應用比較
Honeywell Bolometer 霍尼韋爾波洛米特 JPL Thermopile JPL 熱電堆 JPL QWIP
Applications 應用

警察、消防員、夜間駕駛等。
Police, firefighters,
night driving, e.t.c.
Police, firefighters, night driving, e.t.c.| Police, firefighters, | | :--- | | night driving, e.t.c. |

單色探測器,光譜儀
Monochromatic
detectors,
spectrometers
Monochromatic detectors, spectrometers| Monochromatic | | :--- | | detectors, | | spectrometers |

太空應用,檢測具有極端溫差的物體
Space applications,
Detecting objects with
extreme difference of
temperature spots
Space applications, Detecting objects with extreme difference of temperature spots| Space applications, | | :--- | | Detecting objects with | | extreme difference of | | temperature spots |
Cost 成本

便宜(價格控制權)
Cheap
(price-control power)
Cheap (price-control power)| Cheap | | :---: | | (price-control power) |
Expensive 昂貴 Expensive 昂貴
Honeywell Bolometer JPL Thermopile JPL QWIP Applications "Police, firefighters, night driving, e.t.c." "Monochromatic detectors, spectrometers" "Space applications, Detecting objects with extreme difference of temperature spots" Cost "Cheap (price-control power)" Expensive Expensive| | Honeywell Bolometer | JPL Thermopile | JPL QWIP | | :---: | :--- | :---: | :---: | | Applications | Police, firefighters, <br> night driving, e.t.c. | Monochromatic <br> detectors, <br> spectrometers | Space applications, <br> Detecting objects with <br> extreme difference of <br> temperature spots | | Cost | Cheap <br> (price-control power) | Expensive | Expensive |

What is
Infrared Detectors
紅外線探測器是什麼

Thermal Radiation : 熱輻射:
> > >> radiation emitted by any object at a rate and a wavelength distribution determined by the temperature of the object
> > >> 輻射由任何物體以由物體的溫度決定的速率和波長分佈發射

> > >> thermal radiation through atmosphere is attenuated by scattering and absorption process
> > >> 熱輻射在大氣中受到散射和吸收過程的衰減
Why Infrared (IR) Detecting > > >> maximum radiation occurs around waveband of 2 - 15 μ m 15 μ m 15 mum15 \mu \mathrm{~m}
為什麼紅外線(IR)檢測 > > >> 的最大輻射發生在波段約為 2 - 15 μ m 15 μ m 15 mum15 \mu \mathrm{~m}


number of photons and emission power vs. wavelength
光子數量與發射功率對波長的關係
Fabricating Suspended MEMS structures using ICP in Single Run
使用單次運行中的 ICP 製造懸浮 MEMS 結構

楊燿州

Chamber configuration 腔室配置

Etching / Passivation Steps
蝕刻 / 被動化步驟


(1) etching step (1) 蝕刻步驟

(3) etching step (3) 蝕刻步驟
\square silicon substrate  \square 矽基板

(2) passivation step (2) 鈍化步驟

(4) passivation step (4) 鈍化步驟
\square mask \square polymer  \square 面具 \square 聚合物
Passivation Etching Active Active Time Time
鈍化蝕刻 主動 主動時間 時間

Alternating etching/passivation steps
交替蝕刻/鈍化步驟

  • Etching step: 蝕刻步驟:
  • Ion bombardment provides etch directionality
    離子轟擊提供蝕刻方向性
  • Directional etching removes polymer from base of structure at much higher rate than from side-walls
    定向蝕刻以遠高於側壁的速率從結構基部去除聚合物

    -SF 6 6 _(6){ }_{6} plasma etches silicon after passivation removal
    -SF 6 6 _(6){ }_{6} 等離子體在去除鈍化層後蝕刻矽
  • Passivation step : 鈍化步驟:
  • C 4 F 8 C 4 F 8 C_(4)F_(8)C_{4} F_{8} plasma deposits fluorocarbon polymer
    C 4 F 8 C 4 F 8 C_(4)F_(8)C_{4} F_{8} 等離子體沉積氟碳聚合物
  • Isotropic process without applied bias voltage
    無施加偏壓的各向同性過程

Process is likely to be trade-off
過程可能是權衡取捨

Anisotropy = = == 各向異性 = = ==
Relationship between RF power, pressure,
射頻功率與壓力之間的關係

SF 6 SF 6 SF_(6)\mathrm{SF}_{6} flow rate  SF 6 SF 6 SF_(6)\mathrm{SF}_{6} 流量

  • RF coil power, SF 6 SF 6 SF_(6)\mathrm{SF}_{6} flow rate (sccm) and pressure (mT) are key parameters for controlling Si etch rate
    RF 線圈功率、 SF 6 SF 6 SF_(6)\mathrm{SF}_{6} 流量(sccm)和壓力(mT)是控制矽蝕刻速率的關鍵參數
  • High RF coil power increases F etchant species concentration by enhanced S F 6 S F 6 SF_(6)S F_{6} dissociation
    高射頻線圈功率通過增強 S F 6 S F 6 SF_(6)S F_{6} 解離來提高 F 蝕刻劑物種濃度
  • At high RF coil power, high SF 6 SF 6 SF_(6)\mathrm{SF}_{6} flow rate further increases F etchant species concentration
    在高射頻線圈功率下,高 SF 6 SF 6 SF_(6)\mathrm{SF}_{6} 流量進一步增加了 F 蝕刻劑物種的濃度
  • High pressure results in higher concentration of F etchant species
    高壓導致氟蝕刻劑物種的濃度增加
Relationship between RF power, pressure, SF 6 SF 6 SF_(6)\mathrm{SF}_{6} flow rate
射頻功率、壓力與 SF 6 SF 6 SF_(6)\mathrm{SF}_{6} 流量之間的關係

MEMS Lab, MEMS 實驗室,

Dept. of Mech. Eng., National Taiwan University
國立台灣大學機械工程系
Etch / Pass. Time ratio v.s profile changing
蝕刻/通過時間比與輪廓變化

Figure The experimental result of the etching of trenches using three etching steps with different etching/polymerization time configurations. 7 s / 7 s , 9 s / 7 s 7 s / 7 s , 9 s / 7 s 7s//7s,9s//7s7 \mathrm{~s} / 7 \mathrm{~s}, 9 \mathrm{~s} / 7 \mathrm{~s} and 5 s / 7 s 5 s / 7 s 5s//7s5 \mathrm{~s} / 7 \mathrm{~s} are used sequentially.
圖示 使用三個不同蝕刻/聚合時間配置的蝕刻步驟進行溝槽蝕刻的實驗結果。 7 s / 7 s , 9 s / 7 s 7 s / 7 s , 9 s / 7 s 7s//7s,9s//7s7 \mathrm{~s} / 7 \mathrm{~s}, 9 \mathrm{~s} / 7 \mathrm{~s} 5 s / 7 s 5 s / 7 s 5s//7s5 \mathrm{~s} / 7 \mathrm{~s} 依次使用。

each for 5 min .
每個持續 5 分鐘。

不同溝寬底部側邊之表面粗度-1

不同溝寬底部側邊之表面粗度-2
Fabricating Suspended MEMS Structures Using ICP in Single Run
利用單次運行中的 ICP 製造懸浮 MEMS 結構
  • Motivations 動機
Traditional approaches for releasing structures are either
傳統的結構釋放方法要麼是
Complicated 複雜
required other 所需其他
deposition/lithography/doping processes before structure releasing
沉積/光刻/摻雜過程在結構釋放之前

Expensive 昂貴
if using SOI wafer
如果使用 SOI 晶圓
What is suspended structures
懸掛結構是什麼

單層Test Device結構製作 單層測試裝置結構製作

Process Step 過程步驟

  1. Trench etching (ICP-RIE ASE process)
    溝槽蝕刻(ICP-RIE ASE 過程)
Silicon Polymer  Silicon   Polymer  {:[" Silicon "],[" Polymer "]:}\begin{aligned} & \text { Silicon } \\ & \text { Polymer } \end{aligned}

2. Sidewall deposition (Passivation step only)
2. 側壁沉積(僅限於鈍化步驟)


3. Remove floor polymer (Etch step only or ASE process)
3. 移除地板聚合物(僅限蝕刻步驟或 ASE 過程)


4. Isotropic silicon releasing (Etch step only without platen power)
4. 各向同性矽釋放(僅蝕刻步驟,無平臺功率)