Same function can be achieved by a 1.5 xx1.5cm^(2)1.5 \times 1.5 \mathrm{~cm}^{2} die in mid 1970s! 在 1970 年代中期，可以通過一個 1.5 xx1.5cm^(2)1.5 \times 1.5 \mathrm{~cm}^{2} 模具實現相同的功能！
IC Industries IC 產業
Raw material supplier 原材料供應商
wafers, chemicals 晶圓，化學品
IC circuitry design 集成電路設計
Design house 設計公司
IC fabrication 集成電路製造
E.g., TSMC, UMI for fab only 例如，台積電，僅限於晶圓廠的 UMI
E.g., Intel, TI, Lucent for both design and fabrication 例如，英特爾、德州儀器、盧森特用於設計和製造。
Equipment suppliers of IC fabrication/characterization IC 製造/表徵的設備供應商
An overall idea on how a IC chip was fabricated IC 晶片製造的整體概念
Certain depth on each important fabrication step 每個重要製造步驟的特定深度
The role of a non-electrical engineering background person in semiconductor industries or related research projects 非電機工程背景的人在半導體產業或相關研究項目中的角色
Courses after this introductory material 這些入門材料之後的課程
Semiconductor fabrication related courses 半導體製造相關課程
MEMS related courses MEMS 相關課程
nanosystems related courses 納米系統相關課程
semiconductor processes 半導體製程
Microelectronics Devices 微電子裝置
Yao-Joe Yang 楊耀久
Outline 大綱
Basic semiconductor physics 基本半導體物理學
Semiconductor devices 半導體裝置
Resistors 電阻器
Capacitors 電容器
P-N diodes P-N 二極體
BJT/MOSFET
Solid materials may be classified as follows: 固體材料可以分類如下：
Amorphous 無定形
no ordered atomic arrangement 無序的原子排列
Polycrystalline 多晶體
short range atomic order usually in small crystalline grains (10 Å - few mum\mu \mathrm{m} ) 短程原子序通常存在於小的晶粒中（10 Å - 幾個 mum\mu \mathrm{m} ）
Crystalline 晶體的
long range, ordered, atomic arrangement, repeating unit cell 長程、有序、原子排列、重複單元格
All important semiconductor devices are based on crystalline materials (Si especially) because of their reproducible and predictable electrical properties 所有重要的半導體器件都是基於晶體材料（特別是矽），因為它們具有可重複和可預測的電氣特性
Strength strongly depends on surface quality 強度在很大程度上依賴於表面質量
Poly silicon has similar elastic constant and mechanical properties as crystalline silicon. However, residual strength, toughness, and electrical properties are quite different 多晶矽的彈性常數和機械性能與晶體矽相似。然而，殘餘強度、韌性和電氣性能卻有很大不同。
Extrinsic Semiconductors 外部半導體
In all important electronic devices, dopant are purposely added to control the electronic properties 在所有重要的電子設備中，故意添加摻雜劑以控制電子特性
n-type semiconductor n 型半導體
add phosphorus or arsenic to provide excess electron carriers 添加磷或砷以提供過量的電子載體
p-type semiconductor p 型半導體
add boron, gallium, or indium into silicon to provide additional vacancies or holes 在矽中添加硼、鎵或銦以提供額外的空位或孔洞
The mass-action law is still valid 質量作用定律仍然有效
np=n_(i)^(2)n p=n_{i}^{2}
Doping 禁藥使用
All semiconductor devices are fabricated LOCALLY introducing controlled number of n - and p -type dopant 所有半導體設備都是在本地製造的，並引入受控數量的 n 型和 p 型摻雜劑
Semiconductor Conductivity 半導體導電性
The conductivity ((Omega.cm)^(-1))\left((\Omega . \mathrm{cm})^{-1}\right) is determined by the mobility and concentration of both electrons and holes 導電率 ((Omega.cm)^(-1))\left((\Omega . \mathrm{cm})^{-1}\right) 由電子和空穴的遷移率及濃度決定
sigma=qmu_(n)n+qmu_(p)p\sigma=q \mu_{n} n+q \mu_{p} p
where mu\mu is the mobility, for silicon 其中 mu\mu 是矽的遷移率 -mu_(n)=1350cm^(2)//V.s-\mu_{\mathrm{n}}=1350 \mathrm{~cm}^{2} / \mathrm{V} . \mathrm{s} -mu_(p)=480cm^(2)//V.s-\mu_{p}=480 \mathrm{~cm}^{2} / \mathrm{V} . \mathrm{s} -q=1.609 xx10^(-19)C-\mathrm{q}=1.609 \times 10^{-19} \mathrm{C}
temperature decreases, conductivity increases 溫度降低，導電性增加
Resistivity Vs. Doping Concentration 電阻率與摻雜濃度
Resistivity = 1/conductivity 電阻率 = 1/導電率
Semiconductor Device Overview 半導體器件概述
VLSI are consisted by many transistors, capacitors, diodes, and resistors. However, the transistor fabrication can cover the other three VLSI 由許多晶體管、電容器、二極體和電阻器組成。然而，晶體管的製造可以涵蓋其他三者。
One need to know the basic definition, working principle, and fabrication routes for these basic elements 需要了解這些基本元素的基本定義、工作原理和製造途徑
Resistors 電阻器
A resistor can be defined as a device in which the applied electric potential and measured current exhibit a certain relationship, i.e., V=f(I)V=f(I) 電阻器可以定義為一種裝置，其中施加的電位和測量的電流之間顯示出某種關係，即 V=f(I)V=f(I)
For linear device, we have V=RI\mathrm{V}=\mathrm{RI}, where R is called the resistance of the resistor 對於線性元件，我們有 V=RI\mathrm{V}=\mathrm{RI} ，其中 R 被稱為電阻器的電阻
Consider a resistor with length LL and crosssectional dimension W and d, R can be expressed as 考慮一個長度為 LL 且橫截面尺寸為 W 和 d 的電阻器，R 可以表示為
reduce the junction barrier and eliminate the depletion zone 降低接面障礙並消除耗盡區域
Reverse bias 反向偏壓
enhance the junction barrier and increase the depletion zone 增強接面障礙並增加耗盡區域
Capacitors 電容器
Capacitor is a device in which the charge and electric potential can be defined, i.e., V=f(Q)V=f(Q). 電容器是一種可以定義電荷和電位的裝置，即 V=f(Q)V=f(Q) 。
In linear element, we can express the above relationship as Q=CV\mathrm{Q}=\mathrm{CV}. Where C is the capacitance of the capacitor. 在線性元件中，我們可以將上述關係表示為 Q=CV\mathrm{Q}=\mathrm{CV} 。其中 C 是電容器的電容。
Where epsi\varepsilon is the dielectric constant of dielectric, A is the overlapped area and dd is the separation of two parallel plates. 其中 epsi\varepsilon 是介電材料的介電常數，A 是重疊面積，而 dd 是兩個平行板之間的距離。
Transistors 晶體管
Transistors are widely used for switching and amplification 晶體管廣泛用於開關和放大
replace vacuum tubes 更換真空管
Two major transistors 兩個主要的晶體管
Bipolar Junction Transistor (BJT) 雙極接面晶體管 (BJT)
collector, emitter, base 集電極、發射極、基極
current controlled 當前控制
Field Effect Transistor (FET) 場效應晶體管 (FET)
source, drain, gate 源極、漏極、閘極
voltage controlled 電壓控制
Bipolar Junction Transistors (BJT) 雙極接面晶體管 (BJT)
Fig. 4.1 A simplified structure of the non transistor. 圖 4.1 簡化的非晶體管結構。
p型基板 p 型基板
(a) npn
23
Field Effect Transistors (FET) 場效應晶體管 (FET)
FET is the most popular transistor at this moment FET 是目前最受歡迎的晶體管
incorporate with MOS process 結合 MOS 過程
Can be divided into 可以分為
two catalog 兩個目錄
MOSFET
depletion 耗竭
enhancement 增強
JFET
Symbols of FET 場效應晶體管的符號
FETs are unipolar devices 場效應晶體管是單極裝置
for switch operation, usually we use NMOS or CMOS technology to further reduce power consumption and increase the device density 在開關操作中，通常我們使用 NMOS 或 CMOS 技術來進一步降低功耗並增加設備密度
CMOS IC CMOS 集成電路
From Basic Elements to a IC Chips 從基本元素到集成電路晶片
Analog 類比
basic devices (transistors, resistors…) to OPAMP 基本元件（晶體管、電阻器……）到運算放大器
OPAMP to analog circuit 運算放大器至類比電路
The designer may start from basic devices 設計師可以從基本設備開始
Overall Yield determines whether a fab is making profit or losing money 整體產量決定了一個晶圓廠是否在盈利或虧損
Compare beams a and b with geometric similarity but with different absolute size: (delta_(a)//L_(a))/(delta_(b)L_(b))=(L_(a))/(L_(b))\frac{\delta_{a} / L_{a}}{\delta_{b} L_{b}}=\frac{L_{a}}{L_{b}} 比較具有幾何相似性但絕對大小不同的梁 a 和 b： (delta_(a)//L_(a))/(delta_(b)L_(b))=(L_(a))/(L_(b))\frac{\delta_{a} / L_{a}}{\delta_{b} L_{b}}=\frac{L_{a}}{L_{b}}
The beam in upper picture: 56^('')56^{\prime \prime} long, 1//2^('')1 / 2^{\prime \prime} diameter The beam in lower picture: 7^('')7^{\prime \prime} long, 1//16^('')1 / 16^{\prime \prime} diameter (same material, same aspect ratio – isometry) 上圖中的梁： 56^('')56^{\prime \prime} 長， 1//2^('')1 / 2^{\prime \prime} 直徑 下圖中的梁： 7^('')7^{\prime \prime} 長， 1//16^('')1 / 16^{\prime \prime} 直徑（相同材料，相同長寬比 - 等距）
The size difference in the example is 8 times. 範例中的大小差異為 8 倍。
The relative deformation of a 300 mum300 \mu \mathrm{~m}-long beam (typical size for microbeams) would be 1/5000 that of the 56" long beam. 一根長度為 300 mum300 \mu \mathrm{~m} 的梁（微梁的典型尺寸）的相對變形將是 56 英寸長的梁的 1/5000。
=> In microscale, structures appear stiffer against inertia forces. 在微觀尺度上，結構對慣性力顯得更為剛性。
Inertia force is generally insignificant for micro-devices. 慣性力對於微型裝置通常是微不足道的。
(proof-mass for accelerometers; strong against shock) （加速度計的質量證明；抗震性強）
Long microbeams suspended over silicon wafer by only 1-2 mum\mu \mathrm{m} (typical surface-micromachined devices) do not sag to touch the surface: 長微束僅以 1-2 mum\mu \mathrm{m} 懸浮於矽晶圓上（典型的表面微機械裝置）不會下垂觸及表面：
Resonant microstructure (Tang et al, Sensors and Actuators '89) 共振微結構（唐等，傳感器與執行器 '89）
On-wafer microgripper (Kim et al., J.MEMS '92) 晶圓上微型夾具（Kim et al., J.MEMS '92）
What is suspended structures 懸掛結構是什麼
Locomotion 運動學
e.g. blue whale swims at Re∼10^(8)\operatorname{Re} \sim 10^{8} large fish swims at Re∼10^(5)\operatorname{Re} \sim 10^{5} 例如，藍鯨在 Re∼10^(8)\operatorname{Re} \sim 10^{8} 游泳，大魚在 Re∼10^(5)\operatorname{Re} \sim 10^{5} 游泳。
large bird flies at Re∼10^(4)\operatorname{Re} \sim 10^{4} 大型鳥類在 Re∼10^(4)\operatorname{Re} \sim 10^{4} 飛行
bacteria swims at Re∼10^(-6)\operatorname{Re} \sim 10^{-6} 細菌在 Re∼10^(-6)\operatorname{Re} \sim 10^{-6} 游泳
(based on its length and speed) （根據其長度和速度）
World lifting records 世界舉重紀錄
Common nails produced 普通釘的生產
Crystal Growth 晶體生長
Semiconductor Materials 半導體材料
Single crystal 單晶 >> will be discussed in this section 本節將討論 >> >> no grain boundary >> 無晶界 >> almost all atoms occupy well defined positions 幾乎所有原子都佔據明確的位置 >> E.g., substrate of Si and GaAs 例如，矽和砷化鎵的基材
Amorphous 無定形 >> no long range order >> 無長程有序 >> E.g., Oxide 例如，氧化物
Polycrystalline 多晶體 >> small single crystal randomly oriented >> 小型單晶隨機取向 >> E.g., CVD Silicon 例如，CVD 矽
Crystal structure 晶體結構
Body centered cube (BCC) 體心立方晶格 (BCC)
Face centered cube (FCC) 面心立方體 (FCC)
Diamond structure : Si crystal 鑽石結構：矽晶體
Diamond structure 鑽石結構
Simple cube 簡單立方體
Body centered cube Face centered cube 體心立方體 面心立方體
Tetrahedral bonding of silicon atoms 矽原子的四面體鍵合
Crystallography 結晶學
The Miller index 米勒指數
Mechanical properties of silicon is orientation dependent 矽的機械性質依賴於取向
100
111
Miller Indices 米勒指數
Crystal Growth 晶體生長
98% of total devices use single crystal Si 98% 的總設備使用單晶矽
CZ Growth (Czochralski Growth) CZ 生長（Czochralski 生長） > 85%>85 \% of total semiconductor product > 85%>85 \% 的總半導體產品 >> DRAM 、SRAM 、ASIC >> 動態隨機存取記憶體 (DRAM)、靜態隨機存取記憶體 (SRAM)、應用特定積體電路 (ASIC) >> Large size wafer (ingot) 大型晶圓（單晶棒）
FZ Growth (Float Zone Growth) FZ 成長（浮區成長） >> for extremely high purity wafer >> 用於極高純度的晶圓 > 15%>15 \% of total semiconductor product > 15%>15 \% 的總半導體產品 >> High power devices 高功率裝置
Czochralski Growth Czochralski 生長
The most important fabrication process to grow single crystal silicon substrate 生長單晶矽基板的最重要製造過程
Pre-process 前處理 >> Starting from raw material to form metallurgical-grade Si 從原材料開始形成冶金級矽
SiO_(2)+2Crarr(2000^(@)C)Si+2COuarr\mathrm{SiO}_{2}+2 \mathrm{C} \rightarrow\left(2000^{\circ} \mathrm{C}\right) \mathrm{Si}+2 \mathrm{CO} \uparrow >> Metallurgical-grade Si to form Trichlorosilane (gas) 冶金級矽形成三氯矽烷（氣體）
Si+nHClrarr(300^(@)C)SiHCl_(3)+MCl_(x)\mathrm{Si}+\mathrm{nHCl} \rightarrow\left(300^{\circ} \mathrm{C}\right) \mathrm{SiHCl}_{3}+\mathrm{MCl}_{\mathrm{x}} >> Trichlorosilane to form polysilicon 三氯硅烷形成多晶矽
For extremely high purity of silicon 對於極高純度的矽 >> carrier concentration can be 3 order of magnitude lower than that grown by CZ method >> 載流子濃度可以比通過 CZ 方法生長的低三個數量級
power devices, devices for terahertz applications or detector applications 功率裝置、太赫茲應用裝置或探測器應用裝置 >> no crucible (for oxygen) >> 無熔爐（用於氧氣）
Difficulty of introducing a uniform concentration of dopant 引入均勻濃度摻雜物的難度 >> core doping: use doped polysilicon >> 核心摻雜：使用摻雜多晶矽 >> pill doping: >> 藥丸興奮劑： >> gas doping: dopant gases were injected into melten ring >> 氣體摻雜：摻雜氣體被注入熔融環中 >> neutron doping: >> 中子摻雜：
Floating Zone Method 浮區法
Comparison of the Two Methods 兩種方法的比較
CZ method is more popular CZ 方法更受歡迎 >> Cheaper >> 更便宜 >> Larger wafer size (300 mm in production) >> 更大的晶圓尺寸（300 毫米在生產中） >> Reusable materials 可重複使用的材料
Floating Zone 浮動區域 >> Pure silicon crystal (no crucible) >> 純矽晶體（無坩埚） >> More expensive, smaller wafer size ( 150 mm ) 更昂貴，晶圓尺寸較小（150 毫米） >> Mainly for power devices. 主要用於功率設備。
Introducing flats: major or minor flat 引入降音：大降音或小降音
Sawing: to form wafers 鋸切：形成晶圓
Laser marked: wafer ID 雷射標記：晶圓識別碼
Lapping/ grinding: right thickness 磨削/研磨：適當的厚度
Shaping edge: smooth edge 成形邊緣：平滑邊緣
Chemical-Mechanical polishing: smooth surface Another 50% material were lost during wafering 化學機械拋光：光滑表面 在晶圓加工過程中又損失了 50%的材料
C) CHECK CHARACTERS C) 檢查字符
Ingot Polishing, Flat, or Notch 錠材拋光、平面或缺口
Flat, 150 mm and smaller 平面，150 毫米及以下
Notch, 200 mm and larger 凹槽，200 毫米及以上
Wafer Orientation 晶圓取向
Major flat 主要平面 >> indicate the (110) direction >> 表示 (110) 方向
Minor flat 小平面 >> combining with major flat to determine the wafer and doping type >> 結合主要平面以確定晶圓和摻雜類型
Orientation flat 方向平面
(110) plane (110) 平面
Orientation flat on (110) plane 在 (110) 平面上的取向平坦
Oxygen in Silicon 矽中的氧
Can be as high as 10^(18)cm^(-3)10^{18} \mathrm{~cm}^{-3} in CZ silicon 在 CZ 矽中可以高達 10^(18)cm^(-3)10^{18} \mathrm{~cm}^{-3} >> come from crucible erosion >> 來自熔爐侵蝕
Problem of oxygen in silicon 矽中的氧問題 >> quality of thin gate oxide >> 薄閘氧化層的品質 >> may cause device failure by excessive leakage current >> 可能因過度漏電流而導致設備故障
Gate oxide quality 閘極氧化層質量 >> the most important issue to control the device performance >> 控制裝置性能的最重要問題 >> oxide leakage current >> 氧化物漏電流 >> breakdown voltage >> 突穿電壓
both can be degradation by contamination 兩者都可以因污染而降解
Part 4:
Overview of Wafer Fabrication 第四部分：晶圓製造概述
Yao-Joe Yang 楊耀久
Basic Wafer Fabrication Operations 基本晶圓製造操作
Layering rarr\rightarrow Part 6, Part 7 分層 rarr\rightarrow 第 6 部分，第 7 部分 >> form thin layer/film structures >> 形成薄層/薄膜結構
A series of steps that remove unwanted patterns from substrate surface layers 一系列去除基材表面層中不需要圖案的步驟 >> Patterns are defined by photo-masks >> 圖案由光罩定義
Also known as: Photomasking, masking, lithography, photo-lithography, mu\mu-lithography 也稱為：光掩模、掩模、光刻、光刻技術、 mu\mu -刻蝕
Doping 禁藥使用
Implant specific amount dopant in wafers 在晶圓中植入特定量的摻雜劑 >> modify electrical/mechanical properties of the material >> 修改材料的電氣/機械性質
ion implantation or thermal diffusion 離子植入或熱擴散 >> ion implantation >> 離子植入 *\cdot room temperature physical “bombardment” process >> thermal diffusion *\cdot 室溫物理“轟擊”過程 >> 熱擴散
high temperature process 高溫過程
purpose 目的 >> create either n- or p-type pockets in semiconductor >> 在半導體中創建 n 型或 p 型孔
Heat Treatment 熱處理
Operations in which the wafer is simply heated & cooled to achieve specific results 操作中，晶圓僅被加熱和冷卻以達成特定結果 >> e.g., annealing after ion implantation 例如，離子植入後的退火 >> e.g., annealing of PECVD oxide 例如，PECVD 氧化物的退火
From ME point of view 從我的角度來看 >> Definition of fundamental steps: Layering and Etching 基本步驟的定義：分層與蝕刻
Layering: a material being deposited (added) on a structure 分層：在結構上沉積（添加）材料
Etching: a material being etched (removed) by an etchant 蝕刻：一種被蝕刻劑蝕刻（去除）的材料
Etching must come with an Etching Mask (otherwise, nonsense) 蝕刻必須配有蝕刻面具（否則，毫無意義）
Etching masks prevent material from being etched by etchants. 蝕刻掩模防止材料被蝕刻劑蝕刻。
Etching masks are usually “defined” by photo-masks using lithography techniques. 蝕刻掩模通常是通過使用光刻技術的光掩模來“定義”的。 >> Lithography is a combination of many steps. 光刻是一個由多個步驟組成的過程。 >> Patterning rarr\rightarrow Lithography + Etching >> 圖案化 rarr\rightarrow 光刻 + 蝕刻
Summary: Layering and Patterning rarr\rightarrow create 3D micro structures 摘要：分層和圖案化 rarr\rightarrow 創造 3D 微結構
Etching (with mask) 蝕刻（使用掩模）
Layer 1 is etched by an etchant 第一層由蝕刻劑蝕刻而成
Pattern is defined by photo-mask (etching mask is not shown) 圖案由光罩定義（蝕刻掩模未顯示）
Layering 分層
Three types of Layering (deposition or growing): 三種層疊（沉積或生長）方式：
Conformal 共形
Planar 平面
Stack (not traditional IC process) 堆疊（非傳統集成電路製程）
Conformal 共形
Planar 平面
Stack 堆疊
(not traditional IC process) （非傳統集成電路製程）
Part 5:
Pattern Transfer (Patterning) 第五部分：圖案轉移（圖案化）
Yao-Joe Yang 楊耀久
Patterning 圖案化
Patterns transferred from photo-masks to thin-films on a planar substrate via lithographic process 通過光刻工藝將圖案從光罩轉移到平面基板上的薄膜上
Step 1: 步驟 1：
Transfer patterns of photo-masks to photoresist (etching-mask) by lithography techniques, 通過光刻技術將光掩模的轉移圖案到光刻膠（蝕刻掩模）上，
Step 2: 步驟二：
Use etchants to etch unwanted portion of material defined by etching-masks. 使用蝕刻劑蝕刻由蝕刻掩模定義的材料中不需要的部分。
Example 2: 範例 2：
Patterning 圖案化
Example 2: 範例 2：
Starting Material 起始材料
Example 2: 範例 2：
Spin-coating PR 旋轉塗佈光敏樹脂
Example 2: 範例 2：
Gate Mask Exposure 閘門遮罩曝光
Example 2: 範例 2：
Development 發展
Example 2: 範例 2：
Etch Polysilicon (not finished yet) 刻蝕多晶矽（尚未完成）
Example 2: 範例 2：
Strip Photoresist 去除光阻
Patterning 圖案化
Summary of a typical patterning procedure 典型圖案化程序的摘要
Spin coating photoresist (PR) on a wafer 在晶圓上旋塗光刻膠（PR）
Mask alignment with the wafer using an aligner 使用對準機將掩模與晶圓對準
Exposure of PR PR 的暴露
Development (remove unwanted PR) 發展（移除不必要的公關）
With the remained PR as etching masks, etch the wafer 利用剩餘的光刻膠作為蝕刻掩模，對晶圓進行蝕刻
Striping the remaining PR from the wafer 去除晶圓上剩餘的光阻
Part 5-1: 第五部分-1：
Lithography 石版印刷
Pattern Transfer (Patterning) 圖案轉移（圖案化）
Types of lithography systems: 光刻系統的類型：
Optical 光學
X-ray X 光
electron beam writer (non-traditional, no masks) 電子束寫入器（非傳統，無掩模）
Two-dimensional pattern transfer: 二維圖案轉移：
limited tolerance for non-planar topography on wafer 對晶圓上非平面地形的容忍度有限
2-D pattern transfer imposes constraints on process design 二維圖案轉移對工藝設計施加了限制
The position control of the lithography systems need 10 times better than the achieved electronic resolution level. 光刻系統的定位控制需要比實現的電子解析度水平好十倍。 rarr\rightarrow semiconductor industry strongly depends on precision machine design. rarr\rightarrow 半導體產業強烈依賴精密機械設計。
Lithography Basic Steps 光刻基本步驟
Wafer clean 晶圓清洗
Dehydration bake 脫水烘焙
Spin coating primer and PR 旋轉塗佈底漆和光刻膠
Soft bake 軟烘焙
Alignment and exposure 對齊與曝光
Development 發展
Pattern inspection 圖樣檢查
Hard bake 硬烘焙
PR coating J PR 塗層 J
Development 發展
Optical Lithography 光學光刻術
- Optical Lithography - 光學微影技術
Photo-masks 光罩
Interface between designers and devices 設計師與設備之間的介面
Designers layout design (mask) on computers (2D patterns) 設計師在電腦上進行佈局設計（掩模）（2D 圖案）
photo-masks 光罩
Photo-masks: opaque patterns (chromium) on transparent glass (fused silica) 光罩：透明玻璃（熔融二氧化矽）上的不透明圖案（鉻）
Masks 面具
Photoresist 光阻
- Photoresist (PR) 光阻 (PR)
Optical resists: photosensitive polymers 光學抗蝕劑：光敏聚合物 > PR>\mathrm{PR} is coated on the whole substrate surface using spincoater > PR>\mathrm{PR} 使用旋轉塗佈機均勻塗覆於整個基材表面
Positive PR: 正面公關：
can be removed by specific solution if it is exposed 如果暴露在特定溶液中，可以被去除
most popular for IC process 最受歡迎的集成電路製程
preferred for the pattern in which removed area < reserved area 偏好於移除區域 < 保留區域的模式
Negative PR: 負面公關：
can be removed by specific 可以被特定移除
solution if it is NOT exposed 解決方案如果未被暴露
exposure 暴露
DEVELOPED 發展中
not good for feature size < 3 um 不適用於特徵尺寸 < 3 微米
preferred for the pattern in which 偏好於該模式中
removed area > reserved area 移除區域 > 保留區域
Photoresist Spin Coating 光阻旋塗
Photoresist Spin Coating 光阻旋塗
To vacuum 抽真空
pump 泵
Coater / HMDS 塗佈機 / HMDS
Coating of Photoresists 光刻膠的塗佈
Spinning coating 旋轉塗層 >> Final thickness of photoresist is a function of rotating speed. 光刻膠的最終厚度是旋轉速度的函數。
Thickness prop(1)/(sqrtomega)\propto \frac{1}{\sqrt{\omega}} 厚度 prop(1)/(sqrtomega)\propto \frac{1}{\sqrt{\omega}} >> Relationship has been calibrated and formed a look up table >> 關係已經被校準並形成了一個查詢表
Photoresist Baking 光刻膠烘烤
Pre-bake (soft-bake) 預烤（軟烤） >> After PR coating, before exposure 在光刻膠塗佈後，曝光之前 >> Removing residual solvent and increasing adhesion 去除殘留溶劑並增加附著力 >> e.g., 90^(@)-120^(@)C90^{\circ}-120^{\circ} \mathrm{C} for 1min(1 \mathrm{~min}( hot plate) ∼30min\sim 30 \mathrm{~min} (oven) >> 例如， 90^(@)-120^(@)C90^{\circ}-120^{\circ} \mathrm{C} 用於 1min(1 \mathrm{~min}( 熱板） ∼30min\sim 30 \mathrm{~min} （烤箱）
Post-exposure bake 後曝光烘烤 >> After exposure, before developing >> 曝光後，發展之前
Hard-bake 硬烘 >> After PR developing >> 在公關發展之後 >> Further reduce the solvent concentration 進一步降低溶劑濃度 >> Increase resistance to etchant and ions. I.e., selectivity >> 增加對蝕刻劑和離子的抵抗力。即，選擇性 >> e.g., 100^(@)-130^(@)C100^{\circ}-130^{\circ} \mathrm{C} for 2min(2 \mathrm{~min}( hot plate) ∼30min\sim 30 \mathrm{~min} (oven) >> 例如， 100^(@)-130^(@)C100^{\circ}-130^{\circ} \mathrm{C} 用於 2min(2 \mathrm{~min}( 熱板） ∼30min\sim 30 \mathrm{~min} （烤箱）
Photoresist Removing 光阻去除
After exposure, PR is usually removed in NaOH or KOH based solution 在曝光後，光阻通常在氫氧化鈉或氫氧化鉀的溶液中去除
PR stripping PR 剝離 >> After etching, we need to remove PR. 在蝕刻後，我們需要去除光刻膠。
Etching is a process to selectively remove materials using chemical reactions 蝕刻是一種通過化學反應選擇性去除材料的過程 >> Wet and Dry >> 濕與乾
Classified by chemical reaction 根據化學反應分類 >> Isotropic and anisotropic 各向同性與各向異性
Classified by topology 根據拓撲分類
Etching is usually involved in the lithography cycle as a major step 蝕刻通常作為平版印刷過程中的一個主要步驟
Performance Index 績效指標
Etch rate 蝕刻速率 >> Usually represented as mum//min\mu \mathrm{m} / \mathrm{min} >> 通常表示為 mum//min\mu \mathrm{m} / \mathrm{min}
Selectivity 選擇性 >> defined as the ratio between the etch rate of two materials subject to a particular etchant. Especially one is the thin film (or substrate); the other one is the mask material. >> 定義為在特定蝕刻劑作用下，兩種材料的蝕刻速率之比。特別是其中一種是薄膜（或基材）；另一種是掩模材料。 >> High selectivity is desired 高選擇性是所期望的
Aspect ratio 長寬比 >> Degree of anisotropy 各向異性程度
Uniformity 均勻性
Wet Etching 濕蝕刻
Remove materials by wet chemistry 通過濕化學去除材料
Basic mechanisms 基本機制 >> Reactant transport to surface 反應物運輸至表面
NH_(4)F\mathrm{NH}_{4} \mathrm{~F} is usually added into HF as the buffer agent. We called buffered oxide etch (BOE) NH_(4)F\mathrm{NH}_{4} \mathrm{~F} 通常被添加到氫氟酸中作為緩衝劑。我們稱之為緩衝氧化物蝕刻 (BOE)。
Etch rate is ∼0.5 mum//min\sim 0.5 \mu \mathrm{~m} / \mathrm{min}. Depends on temperature, concentration, and type of oxide 蝕刻速率為 ∼0.5 mum//min\sim 0.5 \mu \mathrm{~m} / \mathrm{min} 。取決於溫度、濃度和氧化物的類型。 >> Dry oxide has lowest etch rate >> 干氧化物的蝕刻速率最低 >> CVD oxide has much high etch rate CVD 氧化物的蝕刻速率非常高
Application of Wet Oxide Etch 濕氧化物蝕刻的應用
Creation of oxide masks 氧化物掩模的製作 >> For subsequent applications in diffusion and ion implantation >> 用於隨後的擴散和離子植入應用
Removal of oxide masks 去除氧化物掩模 >> After doping steps >> 掺杂步骤后
Chemical reaction 化學反應 >> Pure plasma etching >> 純等離子體蝕刻 >> Dry equivalent of wet chemistry (e.g., SF6 etching for silicon) >> 濕化學的乾等效（例如，硫六氟化物蝕刻矽）
Combination of physical and chemical mechanisms 物理與化學機制的結合 >> Plasma etching: with bombardment 等離子體蝕刻：伴隨轟擊 >> Reactive ion etching (RIE) 反應離子蝕刻 (RIE)
Dry Etching of Silicon 矽的乾蝕刻
Chlorine based plasmas result in better anisotropy than Fluorine based plasma. 氯基等離子體的各向異性優於氟基等離子體。
Fluorine based plasmas have higher etch rate 氟基等離子體具有更高的蝕刻速率
For polysilicon only 僅限多晶矽 > Cl_(2)>\mathrm{Cl}_{2} and SF_(6)\mathrm{SF}_{6}> Cl_(2)>\mathrm{Cl}_{2} 和 SF_(6)\mathrm{SF}_{6}
For polysilicon on oxide 對於氧化物上的多晶矽 >> Need high selectivity over oxide 需要對氧化物具有高選擇性 > CCl_(4)>\mathrm{CCl}_{4} are usually selected > CCl_(4)>\mathrm{CCl}_{4} 通常被選擇
Dry Etching of Oxide 氧化物的乾蝕刻
Fluorocarbon based plasmas are usually used for oxide etch 氟碳基等離子體通常用於氧化物蝕刻 > CF_(4),CHF_(3),C_(2)F_(6),C_(3)F_(8)>\mathrm{CF}_{4}, \mathrm{CHF}_{3}, \mathrm{C}_{2} \mathrm{~F}_{6}, \mathrm{C}_{3} \mathrm{~F}_{8} > CF>\mathrm{CF} based molecules was dissociated into many unstable species, radicals, and atoms. They react with oxide to form volatile species > CF>\mathrm{CF} 基於分子被解離成許多不穩定的物種、自由基和原子。它們與氧化物反應形成揮發性物種。
Reactive Ion Etch 反應離子蝕刻
Utilize ion 利用離子
bombardment to create 轟炸以創造
high degree of anisotropy 高程度的各向異性
– RIE EXAMPLE: SiO_(2)//Si(CF_(4)//H_(2))\mathrm{SiO}_{2} / \mathrm{Si}\left(\mathrm{CF}_{4} / \mathrm{H}_{2}\right) – RIE 範例： SiO_(2)//Si(CF_(4)//H_(2))\mathrm{SiO}_{2} / \mathrm{Si}\left(\mathrm{CF}_{4} / \mathrm{H}_{2}\right)
– Anisotropic (directional) – 各向異性（方向性）
– Selectivity relatively low – 選擇性相對較低
Don’t need a vast array of chemicals to selectively etch Film_A but not Film_B, at the expense of lower selectivity 不需要大量化學品來選擇性地蝕刻 Film_A 而不蝕刻 Film_B，這是以較低的選擇性為代價的
More versatile, controllable, modular 更具多功能性、可控性、模組化
Dry Etch Station 乾蝕刻站
Etching Cluster Tool 蝕刻叢集工具
Loading Effect 載入效應
Etch rate varies with number of wafers (or total area for etching) in a single run 蝕刻速率隨著單次處理的晶圓數量（或總蝕刻面積）而變化
area uarr\uparrow, etch rate darr\downarrow 區域 uarr\uparrow ，蝕刻速率 darr\downarrow
It also related to the mass transportation 它也與大眾交通有關
Bullseye effect: edges have a higher etch rate 靶心效應：邊緣的蝕刻速率較高
Material source is heated to sublimation temperature 材料源被加熱至升華溫度
Vapor of the material is transported to target rarr\rightarrow deposition 材料的蒸氣被運輸到目標 rarr\rightarrow 沉積處
In high vacuum (mean free path =50m=50 \mathrm{~m} ) 在高真空中（平均自由程 =50m=50 \mathrm{~m} ）
Deposition is by “line-of-sight” 沉積是通過“視線”進行的 >> Sputtering 濺射
Procedure: 程序：
Material atoms are removed from target by momentum transfer 材料原子透過動量轉移從目標中移除
» Gas molecules are ionized in a glow discharge 氣體分子在輝光放電中被電離
" ions strike target and remove mainly neutral atoms "離子撞擊目標並主要去除中性原子"
Atoms condense on the substrate rarr\rightarrow deposition 原子在基材上凝聚 rarr\rightarrow 沉積
Easy to deposit alloys 易於沉積的合金
Thermal Evaporator 熱蒸發器
Electron Beam Evaporator 電子束蒸發器
Types of Evaporation 蒸發的類型
Filament evaporation 纖維蒸發 >> major problems >> 主要問題
high contamination level 高污染水平
hard to form composite films 難以形成複合薄膜
Electron-beam evaporation 電子束蒸發 >> using high density electron beam to evaporate metals >> 使用高密度電子束蒸發金屬 >> dual E-beams with dual target can be used to co-evaporate composite materials >> 雙電子束與雙靶可以用來共同蒸發複合材料 >> major problem: radiation damage 主要問題：輻射損傷
(a)
(b)
Step Coverage 步驟覆蓋率
A primary limitation of evaporation 蒸發的一個主要限制 >> material beams are non-divergent >> 材料樑是非發散的
Need wafer rotation to improve step coverage 需要晶圓旋轉以改善步進覆蓋率
Performance index 績效指標 >> AR (step height/step diameter) >> AR (步高/步直徑) >> OK for AR < 0.5\mathrm{AR}<0.5>> 可以用於 AR < 0.5\mathrm{AR}<0.5 >> marginal 0.5 < AR < 10.5<\mathrm{AR}<1>> 邊際 0.5 < AR < 10.5<\mathrm{AR}<1 >> poor if AR > 1A R>1>> 如果 AR > 1A R>1 貧窮
Evaporator 蒸發器
Sputtering 濺射
The major PVD method in silicon technology 矽技術中的主要物理氣相沉積方法
Using ion bombardment to introduce mass transfer 利用離子轟擊引入質量傳遞
Low temperature process 低溫過程 >> can deposit virtually any materials, >> 可以幾乎沉積任何材料，
metals 金屬
ceramics 陶瓷
organic materials 有機材料 >> can deposit composite film (alloy) with controllable composition >> 可以沉積具有可控成分的複合薄膜（合金）
Major disadvantage rarr\rightarrow substrate damage 主要缺點 rarr\rightarrow 基材損壞
Sputtering 濺射
Argon (Ar) atoms is usually used as the ion source 氬（Ar）原子通常用作離子源 >> Inert >> 惰性 >> Relatively heavy 相對較重 >> Abundance >> 豐富性
about 1%1 \% in atmosphere 關於 1%1 \% 在大氣中
low cost 低成本
Sputtering 濺射
Momentum transfer will dislodge surface atoms off 動量轉移將使表面原子脫落
DC Diode Sputtering 直流二極體濺射
Sputter 濺射
Sputtering vs. Evaporator 濺射與蒸發器
Sputtering 濺射
Purer film 更純淨的薄膜 >> Better uniformity 更好的均勻性 >> Single wafer, better process control >> 單晶圓，更佳的製程控制 >> Larger size wafer >> 更大尺寸的晶圓 >> Low temperature 低溫
Versatile in materials 多功能材料
Evaporator 蒸發器
More impurities 更多雜質 >> Batch process >> 批次處理 >> Cheaper tool >> 更便宜的工具
Less substrate damage 較少的基材損傷
Introduction to CVD CVD 簡介
Form thin films by thermal decomposition and/or reaction of gaseous compounds 通過熱分解和/或氣體化合物反應形成薄膜
Application: 應用： >> masks to prevent oxidation for LOCOS process >> 面具以防止 LOCOS 過程中的氧化 >> final passivation barrier for moisture and sodium contamination >> 最終鈍化屏障以防潮濕和鈉污染
Residual stress 殘餘應力 >> stress of the thin film under no external loading 在無外部載荷下薄膜的 >> 應力 >> A major mechanical problem in thin film materials 薄膜材料中的一個主要機械問題
Problem associated with residual stress 與殘餘應力相關的問題 >> structural integrity 結構完整性 >> change of geometry, causing difficulty for subsequent processes >> 幾何變化，導致後續過程的困難 >> natural frequency shift of MEMS structures >> MEMS 結構的自然頻率偏移
Major sources 主要來源 >> mismatch in thermal mechanical properties >> 在熱機械性質上的不匹配 >> grain growth, impurity, phase transformation, etc >> 顆粒生長、雜質、相變化等
Part 7 第七部分
Oxidation 氧化
Yao-Joe Yang 楊耀久
Oxidation Process 氧化過程
One of the thin-film processes 薄膜製程之一
For thermal oxidation of silicon 矽的熱氧化 >> Dry oxidation 乾氧化
Dielectric 介電體 >> gate oxide for MOS capacitors and FET >> 閘氧化層用於 MOS 電容器和場效應晶體管
Masks 面具 >> for ion implantation or etching >> 用於離子植入或蝕刻
Protective layer 保護層 >> to avoid IC damage >> 以避免集成電路損壞
Modeling of oxidation process 氧化過程的建模
Microscopically, the oxidation process is a combination of transportation and surface reaction >> Oxygen must be transported into silicon/oxide interafce prior to the reaction 在微觀上，氧化過程是運輸和表面反應的結合 >> 氧氣必須在反應之前被運輸到矽/氧化物界面
Ideally, 46%46 \% volume of silicon were converted into 100%100 \% oxide during oxidation 理想情況下， 46%46 \% 立方體的矽在氧化過程中轉化為 100%100 \% 氧化物 >> actual ratio depends on the quality of oxide >> 實際比率取決於氧化物的質量
-Volume increases during oxidation -氧化過程中體積增加 *0.46Sirarr1\cdot 0.46 \mathrm{Si} \rightarrow 1 oxide *0.46Sirarr1\cdot 0.46 \mathrm{Si} \rightarrow 1 氧化物
for sufficiently thick oxide (parabolic regime) 對於足夠厚的氧化物（拋物線區域）
t_(ox)^(2)~~B(t+tau)t_{o x}^{2} \approx B(t+\tau)
The tau\tau parameter is used to compensate for the rapid growth regime for thin oxides. (After Deal and Grove.) tau\tau 參數用於補償薄氧化物的快速增長模式。（根據 Deal 和 Grove。）
Oxidation Equipment 氧化設備
Oxide Quality 氧化物質量
Wet oxide 濕氧化物 >> relative quick process, maximum thickness ∼\sim a few mum\mu \mathrm{m} >> 相對快速的過程，最大厚度 ∼\sim 幾個 mum\mu \mathrm{m} >> Mainly for the insulating or masking purpose >> 主要用於絕緣或遮蔽目的
Dry oxide 乾氧化物 >> slow process, higher density, maximum thickness ∼1000"Å"\sim 1000 \AA >> 緩慢過程，更高密度，最大厚度 ∼1000"Å"\sim 1000 \AA >> higher breakdown voltage ( ∼5-10MV//cm\sim 5-10 \mathrm{MV} / \mathrm{cm} ) >> 較高的擊穿電壓 ( {{1 }} ) >> used as dielectric for capacitors and MOSFET >> 用作電容器和 MOSFET 的介電材料
high quality gate oxide is critical for microelectronics 高品質的閘極氧化層對微電子學至關重要
Part 8
Ion Implantation 第八部分 離子植入
Yao-Joe Yang 楊耀久
Introduction 引言
Ion implantation is a technology to change the electrical properties by “shooting” high energy impurity (donors/acceptors) into semiconductor substrates 離子植入是一種通過將高能雜質（施主/受主）“射入”半導體基板來改變電性質的技術
advantages over diffusion process 擴散過程的優勢 >> low temperature process >> 低溫過程 >> wide variety of masks 各式各樣的面具 >> minimize the movement of impurity by diffusion >> 透過擴散最小化雜質的運動
Implantation Technologies 植入技術
Ion inplanter is a high-voltage particle accelerator producing a high velocity beam of impurity. It can be divided into the following parts: 離子植入機是一種高電壓粒子加速器，產生高速度的雜質束。它可以分為以下幾個部分： >> Ion source >> 離子源 >> Mass spectrometer 質量分析儀 >> High-voltage accelerator 高壓加速器 >> Scanning system >> 掃描系統 >> Target chamber >> 目標腔體
Ion Implantation Systems 離子植入系統
Usually it is quite “big” and “expansive” 通常它是相當“龐大”和“廣闊”的
Starting material 起始材料
Ion Implantation 離子植入
Ion Implantation System 離子植入系統
Ion Mask Materials 離子面具材料
Typical mask materials 典型的口罩材料
Oxide, nitride: all temperature 氧化物、氮化物：所有溫度
Aluminum, PR: low temperature 鋁，PR：低溫
Silicon nitride is a more effective barrier than oxide > Only 85% required (Jaeger, p97) 氮化矽是一種比氧化物更有效的屏障 > 只需 85%（Jaeger，第 97 頁）
PR is less effective 公關的效果較差
Need 180% over oxide thickness 需要 180%的氧化物厚度
Channeling 引導
In crystalline substrate, at certain angle, the implanted ions can travel longer than expected before they were finally loss their momentum 在晶體基板中，於特定角度下，植入的離子可以比預期更長時間地運行，直到它們最終失去動量 >> Result in deeper junction >> 在更深的接合處的結果 >> Somewhat it is not desirable because it make things uncontrollable 某種程度上這是不可取的，因為它使事情變得無法控制
It will be resolved by a 7^(@)7^{\circ} tilting for (100) silicon 將通過對(100)矽的 7^(@)7^{\circ} 傾斜來解決
Channeling 引導
§ Micromachining rarr\rightarrow two major catagories: § 微加工 rarr\rightarrow 兩大類別：
Structural Layer SAC layer etchant
Polysilicon SiO_(2) BOE,HF
Si_(3)N_(4) Si KOH//H_(2)O
Polyimide Al PAN
Ni Al PAN| Structural Layer | SAC layer | etchant |
| :---: | :---: | :---: |
| Polysilicon | $\mathrm{SiO}_{2}$ | $\mathrm{BOE}, \mathrm{HF}$ |
| $\mathrm{Si}_{3} \mathrm{~N}_{4}$ | Si | $\mathrm{KOH} / \mathrm{H}_{2} \mathrm{O}$ |
| Polyimide | Al | PAN |
| Ni | Al | PAN |
PAN: Phosphoric acid (H3PO4), Acetic acid (Ch3COOH)(\mathrm{Ch} 3 \mathrm{COOH}), and Nitric acid (HNO_(3))\left(\mathrm{HNO}_{3}\right) and water. PAN：磷酸（H3PO4）、醋酸 (Ch3COOH)(\mathrm{Ch} 3 \mathrm{COOH}) 、硝酸 (HNO_(3))\left(\mathrm{HNO}_{3}\right) 和水。
IV. MUMPS Process (ANOTHER PPT) IV. MUMPS 過程（另一個 PPT）
§ Bulk Micromachining § 大規模微機械加工
I. Wet isotropic etching of silicon I. 矽的濕等向蝕刻
Typical chemistry of silicon etching 典型的矽蝕刻化學反應
(i) oxidation of silicon to Si^(+2)\mathrm{Si}^{+2} by strong oxidizing agents (i) 硅在強氧化劑作用下氧化至 Si^(+2)\mathrm{Si}^{+2}
rarr\rightarrow mixtures of HNO_(3)\mathrm{HNO}_{3} and HF diluted in water and/or acetic acid rarr\rightarrow 與 HF 稀釋於水和/或醋酸的 HNO_(3)\mathrm{HNO}_{3} 混合物
the oxidizing agent HNO_(2)\mathrm{HNO}_{2} and (OH)^(-)(\mathrm{OH})^{-}ion are supplied by HNO_(3)\mathrm{HNO}_{3}, when it combines with water and small amount of HNO_(2)\mathrm{HNO}_{2}HNO_(2)+HNO_(3)+H_(2)Orarr2HNO_(2)+2OH^(-)+2H^(+)\mathrm{HNO}_{2}+\mathrm{HNO}_{3}+\mathrm{H}_{2} \mathrm{O} \rightarrow 2 \mathrm{HNO}_{2}+2 \mathrm{OH}^{-}+2 \mathrm{H}^{+} 氧化劑 HNO_(2)\mathrm{HNO}_{2} 和 (OH)^(-)(\mathrm{OH})^{-} 離子由 HNO_(3)\mathrm{HNO}_{3} 提供，當它與水和少量的 HNO_(2)\mathrm{HNO}_{2}HNO_(2)+HNO_(3)+H_(2)Orarr2HNO_(2)+2OH^(-)+2H^(+)\mathrm{HNO}_{2}+\mathrm{HNO}_{3}+\mathrm{H}_{2} \mathrm{O} \rightarrow 2 \mathrm{HNO}_{2}+2 \mathrm{OH}^{-}+2 \mathrm{H}^{+} 結合時
Note: The regeneration of HNO_(2)rarr\mathrm{HNO}_{2} \rightarrow auto-catalytic reaction 注意： HNO_(2)rarr\mathrm{HNO}_{2} \rightarrow 自催化反應的再生
Isotropic etching (a) without and (b) with stirring 各向同性蝕刻 (a) 無攪拌及 (b) 有攪拌
(i) Etch rate have been measured for silicon etching as a function of concentration of its constituents, and plotted on isoetch curves. (i) 硅蝕刻的蝕刻速率已根據其成分的濃度進行測量，並繪製在等蝕刻曲線上。
(ii) Increasing the HNO_(3)\mathrm{HNO}_{3} concentration move the reaction toward the diffusion limited case where etching can be controlled by stirring (ii) 增加 HNO_(3)\mathrm{HNO}_{3} 濃度使反應朝向擴散限制情況移動，在此情況下，蝕刻可以通過搖動來控制
(iii) Increasing the HF concentration or temperature, increases the surface reaction rate. (iii) 增加氫氟酸濃度或溫度會提高表面反應速率。
(iv) Reaction rate limited is likely to result in rough surface. As a result, it enhances the defect area. 反應速率受限可能導致表面粗糙。因此，它會增加缺陷區域。
(v) For transport limited reaction, a smoother surface will be resulted. 對於運輸限制反應，將產生更光滑的表面。
Electro-Chemical Etching 電化學蝕刻
Apply external electrical source to drive the chemical reaction by supplying oxidizing agent to the silicon surface. 施加外部電源以通過向矽表面提供氧化劑來驅動化學反應。
primarily for polishing surfaces. 主要用於拋光表面。
(vi) the etching rate increases with current density rarr\rightarrow high spots on the surface are more rapidly etched. (vi) 蝕刻速率隨著電流密度增加而增加，表面的高點被蝕刻得更快。
(vii) The typical current densities ∼100\sim 100mA//cm^(2)\mathrm{mA} / \mathrm{cm}^{2} （七）典型的電流密度 ∼100\sim 100mA//cm^(2)\mathrm{mA} / \mathrm{cm}^{2}
(viii) heavily doped (low resistivity) substrates can be selectively removed （八）重摻雜（低電阻率）基板可以被選擇性去除
Discover by Uhlir in 1956 由烏赫爾於 1956 年發現
(i) high aspect ratio pores. （i）高長寬比孔隙。
(ii) interesting physics, ref. Madou, pp. 229-232 (2nd 2^("nd ")2^{\text {nd }} ) 有趣的物理學，參見 Madou，第 229-232 頁 (第 2 2^("nd ")2^{\text {nd }} )
Electrochemical etching at 電化學蝕刻於
(i) High HF concentrations (i) 高濃度的高頻電場
(ii) Low etch current (ii) 低蝕刻電流
Diameter range 20A to microns; Oriented in < 100 ><100> direction 直徑範圍 20A 至微米；定向於 < 100 ><100> 方向
Aspect ratio (length/diameter) maintained over millimeter distances 在毫米距離內保持的長度與直徑比（長度/直徑）
Application: Permeable membrane. 應用：可滲透膜。
Highly reactant: oxidizes and etches at high rates 高反應性：以高速度氧化和蝕刻
Porosity varies directly with current density 孔隙率與電流密度成正比
Pore formation in n-type requires illumination. n 型材料中的孔隙形成需要照明。
Operation in dark provides preferential etching of p-type regions. 在黑暗中操作可對 p 型區域提供優先刻蝕。
II. Dry isotropic etching of silicon II. 矽的乾式各向同性蝕刻
Plasma Etching 等離子體蝕刻
Use glow discharge to create a chemically-reactive species from non-reactive gas. 使用輝光放電從非反應性氣體中產生化學反應性物質。
Example: SF_(6)\mathrm{SF}_{6} or CF_(4)\mathrm{CF}_{4} plasma etching of Si using oxide or resist masks 範例： SF_(6)\mathrm{SF}_{6} 或 CF_(4)\mathrm{CF}_{4} 使用氧化物或抗蝕劑掩模對矽進行等離子體蝕刻
highly exothermic deleterious moisture effect; rough surface 高度放熱的有害濕氣效應；粗糙表面
III. Wet anisotropic etching of silicon III. 矽的濕性各向異性蝕刻
The most typical etchant of this type of etching: KOH solution 這種類型蝕刻的最典型蝕刻劑：氫氧化鉀溶液
Crystallographic effects 晶體學效應
Etch rate of {111}\{111\} plane is much slower than all other planes. rarr\rightarrow etch rate ratios as high as 1000 . {111}\{111\} 平面的蝕刻速率遠低於所有其他平面。 rarr\rightarrow 的蝕刻速率比率高達 1000。
The {111}\{111\} planes rarr\rightarrow the highest density of atoms //cm^(2)/ \mathrm{cm}^{2} 這些 {111}\{111\} 平面 rarr\rightarrow 具有最高的原子密度 //cm^(2)/ \mathrm{cm}^{2} rarr3\rightarrow 3 bonds are below {111}\{111\} plane. rarr3\rightarrow 3 鍵結位於 {111}\{111\} 平面以下。
etching along the planes at the angle defined by the surface intersection with the (111) surface. 在與（111）表面交叉的角度上，沿著平面進行蝕刻。
100
110
(1,1,1) (1,0,0)(1,0,0)
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- Commonly used etchants - 常用的蝕刻劑
Alkaline hydroxide (KOH)(\mathrm{KOH}) and water 氫氧化物 (KOH)(\mathrm{KOH}) 和水
(i) Example: KOH and NaOH （i）範例：KOH 和 NaOH
(ii) (+): High etch rate ratio (100)/(111) (high selectivity) (ii) (+): 高蝕刻速率比 (100)/(111) (高選擇性)
(iii) (-): Relatively high SiO_(2)\mathrm{SiO}_{2} etch rate, alkali contamination (iii) (-): 相對較高的 SiO_(2)\mathrm{SiO}_{2} 蝕刻速率，鹼性污染
Ethylene-Diamine-Pyrocatechol/ H_(2)O\mathrm{H}_{2} \mathrm{O} (EDP) 乙烯二胺-吡咯卡特醇/ H_(2)O\mathrm{H}_{2} \mathrm{O} (EDP)
(i) (+): High selectivity rarr\rightarrow variety of etch mask material （i）(+）：高選擇性 rarr\rightarrow 種刻蝕掩模材料
(ii) (-): Optically dense (ii) (-): 光學密度
(iii) SiO_(2)\mathrm{SiO}_{2} is good mask (iii) SiO_(2)\mathrm{SiO}_{2} 是良好的口罩
Hydrazine-water (N_(2)H_(4):H_(2)O)\left(\mathrm{N}_{2} \mathrm{H}_{4}: \mathrm{H}_{2} \mathrm{O}\right) 肼-水 (N_(2)H_(4):H_(2)O)\left(\mathrm{N}_{2} \mathrm{H}_{4}: \mathrm{H}_{2} \mathrm{O}\right)
(i) (+): Low SiO_(2)\mathrm{SiO}_{2} etch rate (i) (+): 低 SiO_(2)\mathrm{SiO}_{2} 蝕刻速率
(ii) (-): Low etch rate ratio (100)/(111), gas is explosive (ii) (-): 低蝕刻速率比 (100)/(111)，氣體具有爆炸性
Etch Masks: 蝕刻掩模：
Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} etch rate in most anisotropic etchants is virtually zero. 在大多數各向異性蝕刻劑中， Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 蝕刻速率幾乎為零。
SiO_(2)\mathrm{SiO}_{2} etch rate is dependent on etch conditions. SiO_(2)\mathrm{SiO}_{2} 蝕刻速率取決於蝕刻條件。
p-n diode configuration rarr\rightarrow anodizing current blocked by the diode rarr\rightarrow etch p-type substrate only p-n 二極體配置 rarr\rightarrow 被二極體阻擋的陽極氧化電流 rarr\rightarrow 僅蝕刻 p 型基板
As the n-layer exposes, its surface anodizes rarr\rightarrow passivation layer forms and etching stops. 隨著 n 層的暴露，其表面陽極氧化 rarr\rightarrow 鈍化層形成並且蝕刻停止。
Membrane thickness is determined by the epi-layer 膜厚度由表層決定
Large applied voltage results in large reverse diode (p-n junction) leakage current rarr\rightarrow form passivation 大應用電壓導致大反向二極體（p-n 結）漏電流 rarr\rightarrow 形成鈍化
layer before etch through p-Si. 在蝕刻 p-Si 之前的層。
issues need to be considered for P-N junction etch-stop 在 P-N 接面蝕刻停止過程中需要考慮的問題
(i) Effect of light (light can accelerate the etch process) (i) 光的影響（光可以加速蝕刻過程）
(ii) Resistive loss changes potential (二) 電阻損失改變潛力
(iii) Electrical contact to alter the electric potential (iii) 電接觸以改變電位
V. Wafer Bonding V. 晶圓鍵合
Types of wafer bonding 晶圓鍵合的類型
Fusion bonding (direct bonding) 融合鍵合（直接鍵合）
(i) Silicon-silicon bonds 矽-矽鍵
(ii) Process （二）過程
(1) Cleaning and hydration of the wafer surface (1) 晶圓表面的清潔與水合作用
(2) fusion at high temperature ( ∼1000^(@)C\sim 1000^{\circ} \mathrm{C} ) (2) 高溫熔合 ( ∼1000^(@)C\sim 1000^{\circ} \mathrm{C} )
(iii) Advantages: (iii) 優勢：
(1) All single crystal silicon, thermal match (1) 所有單晶矽，熱匹配
(2) High strength (2) 高強度
(3) No intermediate layers (3) 無中介層
(4) Hermetic sealing (4) 密封封閉
(5) Self-packaged (5) 自我包裝
Anodic bonding 陽極鍵合
(i) Silicon (=anode) to Pyrex glass (=cathode) (一) 矽 (=陽極) 與鋼化玻璃 (=陰極)
(ii) 200^(@)C∼500^(@)C,500V∼1000V200^{\circ} \mathrm{C} \sim 500^{\circ} \mathrm{C}, 500 \mathrm{~V} \sim 1000 \mathrm{~V}
(iii) high field and high temperature on interface rarr\rightarrow sodium in glass drifts rarr\rightarrow pulls two surface together rarr\rightarrow bond. (iii) 高場和高溫對界面 rarr\rightarrow 鈉在玻璃中的漂移 rarr\rightarrow 使兩個表面相互吸引 rarr\rightarrow 鍵結。
(iv) Hermetic sealing （四）密封封閉
(v) Need good thermal match for silicon and glass (Pyrex 7740 ) (v) 需要良好的熱匹配以適應矽和玻璃（Pyrex 7740）
Gold eutectic bonding 金共晶鍵合
(i) Silicon to silicon; silicon to other materials （i）矽對矽；矽對其他材料
(ii) Silicon and gold alloy has a eutectic temperature ∼316^(@)C\sim 316{ }^{\circ} \mathrm{C}. (ii) 矽和金合金的共晶溫度為 ∼316^(@)C\sim 316{ }^{\circ} \mathrm{C} 。
(iii) Low temperature bond, less thermal budget (iii) 低溫鍵合，較少的熱預算
(iv) Strength is not as good as fusion bond (iv) 強度不如熔接接頭
Glass frit or solder bonding 玻璃粉或焊接粘合
Process 過程
Process sequence for fusion bond 融合接合的過程順序
(i) Surface hydration (i) 表面水合 rarr\rightarrow rinse, NH_(4)OH,H_(2)SO_(4):H_(2)O_(2),HNO_(3)\mathrm{NH}_{4} \mathrm{OH}, \mathrm{H}_{2} \mathrm{SO}_{4}: \mathrm{H}_{2} \mathrm{O}_{2}, \mathrm{HNO}_{3}rarr\rightarrow 漱口， NH_(4)OH,H_(2)SO_(4):H_(2)O_(2),HNO_(3)\mathrm{NH}_{4} \mathrm{OH}, \mathrm{H}_{2} \mathrm{SO}_{4}: \mathrm{H}_{2} \mathrm{O}_{2}, \mathrm{HNO}_{3}
(i) Press polished surface together. Particles must be avoided on contact surface. （i）將拋光表面壓合在一起。接觸表面必須避免顆粒。
(ii) High temperature anneal (strength increases with temperature) (ii) 高溫退火（強度隨溫度增加）
Important parameters 重要參數
(i) Surface roughness (must less than 1 nano meter) 表面粗糙度（必須小於 1 納米）
(ii) Wafer bow (二) 晶圓翹曲
(iii) For bonding of patterned wafers, cavity pressure is important (iii) 對於圖案化晶圓的粘合，腔體壓力是重要的
CVD film can be bonded if the are polished smooth. CVD 薄膜可以在表面被拋光平滑後進行粘合。
Inspection Methods: 檢查方法：
(i) IR imaging, X-ray topography, Ultrasonic (i) 紅外成像、X 射線拓撲學、超聲波
(ii) Bond strength testing (ii) 鍵合強度測試
VI. Other bulk micromachining 六. 其他大規模微加工
Dissolved wafer process 溶解晶圓製程
(wafer dissolved in EDP) （在 EDP 中溶解的晶圓）
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DRIE (Deep RIE) - The Bosch Process DRIE（深度 RIE）- 博世工藝
ICP (Inductively Coupled Plasma) 感應耦合等離子體 (ICP)
Patented process by the Bosch Company 博世公司專利工藝
Time-multiplexed glow-discharge of a silicon isotropic etch gas (SF_(6))\left(\mathrm{SF}_{6}\right) with a polymer (passivation) forming gas (C_(4)F_(6))\left(\mathrm{C}_{4} \mathrm{~F}_{6}\right). 時間多工的矽各向同性蝕刻氣體 (SF_(6))\left(\mathrm{SF}_{6}\right) 與聚合物（鈍化）形成氣體 (C_(4)F_(6))\left(\mathrm{C}_{4} \mathrm{~F}_{6}\right) 的輝光放電。
Pattern mask and isotropic etch r-30secr-30 \mathrm{sec} 圖案掩模和各向同性蝕刻 r-30secr-30 \mathrm{sec}
Lift-off Process 起飛過程
Very common for metal film patterning 金屬薄膜圖案化非常常見
Good for patterning the film whose residual is difficult to be etched thoroughly 適合於圖案化那些殘留物難以徹底蝕刻的薄膜
Need good stencil patterns for successful lift-off 需要良好的模板圖案以實現成功的脫落
Three-layer-polysilicon surface process 三層多晶矽表面處理工藝
Figure 1.1. Cross sectional view showing all 7 layers of the MUMPsTTM process (not to scale). 圖 1.1. 橫截面圖顯示 MUMPsTTM 過程的所有 7 層（不按比例）。
-Three-layer-polysilicon surface process. 三層多晶矽表面處理。
ㅁ polysilicon is used as the structural material (3 layers) 多晶矽被用作結構材料（3 層）
ㅁ oxide (PSG) is used as the sacrificial layer (2 layers) 氧化物 (PSG) 被用作犧牲層 (2 層)
Silicon nitride is used as electrical isolation (1 layer) 氮化矽用作電氣隔離（1 層）
Metal is used as metal contact for wire bonding (1 layer) 金屬用作線焊接的金屬接觸（1 層）
Wicro Illotor Falurication Precess 微克伊洛托爾法盧里卡申過程
MIT/RTET Micro Motor (Eirca 1989] 麻省理工學院/RTET 微型馬達（約 1989 年）
Figure 1.4. Reactive ion etching (RIE) is used to remove the unwanted polysilicon. After the etch, the photoresist is chemically stripped in a solvent bath. This method of patterning the wafers with photoresist, etching and stripping the remaining photoresist is used repeatedly in the MUMPs ^("TTM "){ }^{\text {TTM }} process 圖 1.4. 反應離子蝕刻（RIE）用於去除不需要的多晶矽。蝕刻後，光刻膠在溶劑浴中進行化學去除。這種使用光刻膠對晶圓進行圖案化、蝕刻及去除剩餘光刻膠的方法在 MUMPs ^("TTM "){ }^{\text {TTM }} 過程中反覆使用。
Figure 1.8. A blanket 2.0 um layer of un-doped polysilicon is deposited by LPCVD followed by the deposition of 200 nm PSG and a 1050^(@)C//11050^{\circ} \mathrm{C} / 1 hour anneal. The anneal serves to both dope the polysilicon and reduce its residual stress 圖 1.8。通過低壓化學氣相沉積（LPCVD）沉積一層 2.0 微米的未摻雜多晶矽，隨後沉積 200 奈米的磷掺雜玻璃（PSG）並進行 1050^(@)C//11050^{\circ} \mathrm{C} / 1 小時的退火。退火的作用是對多晶矽進行摻雜並減少其殘餘應力。
to create a hard mask and then Poly 1 is etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed. 創建一個硬掩模，然後通過反應離子蝕刻（RIE）蝕刻 Poly 1。在蝕刻完成後，去除光刻膠和 PSG 硬掩模。
Figure 1.10. The Second Oxide layer, 0.75 mum0.75 \mu \mathrm{~m} of PSG, is deposited on the wafer. This layer is patterned twice to allow contact to both Poly 1 and substrate layers 圖 1.10。第二氧化層 0.75 mum0.75 \mu \mathrm{~m} 的 PSG 被沉積在晶圓上。此層被圖案化兩次，以便與 Poly 1 和基板層接觸。
Figure 1.11. The wafer is coated with photoresist and the fith level (POLY1_POLY2_VIA) is lithographically patterned. The unwanted Second Oxide is RIE etched, stopping on Poly 1 , and the photoresist is stripped. 圖 1.11。晶圓上塗覆了光刻膠，並且第五層 (POLY1_POLY2_VIA) 進行了光刻圖案化。多餘的第二氧化層經過 RIE 蝕刻，停止於 Poly 1，然後去除光刻膠。
The wafer is re-coated with photoresist and the sixth level (ANCHOR2) is lithographically patterned. The Second and 晶圓重新塗覆光刻膠，並對第六層（ANCHOR2）進行光刻圖案化。第二層和
First Oxides are RIE etched, stopping on either Nitrice or Poly 0 , and the photoresist is stripped. The ANCHOR2 level provides openings for Poly 2 to contact with Nitride or Poly 0 . 首先，氧化物經過 RIE 蝕刻，停止於氮化物或聚合物 0，然後去除光阻。ANCHOR2 層提供聚合物 2 與氮化物或聚合物 0 接觸的開口。
Figure 1.14. The wafer is coated with photoresist and the seventh level (POLY2) is lithographically patterned. The PSG hard mask Poly 2 layers are RE etched and the photoresist and hard mask are reved Al mechanical structures have now been fabricated. The remaining steps are to deposit the metal layer and remove the sacrificial oxides. 圖 1.14。晶圓上塗覆了光刻膠，第七層（POLY2）經過光刻圖案化。PSG 硬掩模 Poly 2 層經過 RE 蝕刻，光刻膠和硬掩模被去除，機械結構已經製造完成。剩下的步驟是沉積金屬層並去除犧牲氧化物。
METAL 金屬
Figure 1.15. The wafer is coated with photoresist and the eighth level (METAL) is lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by lif–off patterning which does not require etching. The side wall of the photoresist is 圖 1.15。晶圓上塗覆了光刻膠，並且第八層（金屬）經過光刻圖案化。金屬（帶有薄附著層的金）是通過去除圖案化沉積的，這不需要蝕刻。光刻膠的側壁是
sloped at a reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent bath. The process is now complete and the wafers can be coated with a protective layer of photoresist and diced. The chips are sorted and shipped 以凹入角度傾斜，這使得金屬可以沉積在晶圓和光阻的表面上，但在凹入的光阻階梯上提供了金屬連續性的中斷。然後在溶劑浴中去除光阻和不需要的金屬（在光阻上方）。該過程現在已完成，晶圓可以塗覆一層保護性的光阻並進行切割。晶片被分類並運送。
Figure 1.16. The structures are released by immersing the chips in a 49%HF49 \% \mathrm{HF} solution. The Poly 1 “rotor” can be seen around the fixed Poly 2 hub. The stacks of Poly 1 , Poly 2 and Metal on the sides represent the stators used to drive the motor electrostatically. 圖 1.16。這些結構是通過將晶片浸入 49%HF49 \% \mathrm{HF} 溶液中釋放的。可以看到固定的 Poly 2 中心周圍有 Poly 1 “轉子”。側面的 Poly 1、Poly 2 和金屬堆疊代表用於靜電驅動馬達的定子。
Concepts of MEMS Modeling MEMS 建模的概念
Yao-Joe Yang 楊耀久
National Taiwan University 國立臺灣大學
Outline 大綱
Modeling, simulation and measurement 建模、模擬與測量
Modeling is essential ? 建模是必不可少的嗎？
Introduction to MEMS modeling package MEMS 建模套件介紹
What is Modeling ? 什麼是建模？
“Model” + “ing” “模型” + “化”
Search for appropriate models for physical systems 尋找適合物理系統的模型
F=ma by Sir I. Newton. F=ma 由艾薇·牛頓爵士提出。
E=mc^(2)\mathrm{E}=\mathrm{mc}^{2} by A. Einstein. E=mc^(2)\mathrm{E}=\mathrm{mc}^{2} 由阿爾伯特·愛因斯坦。
Atomic model by Bohr 波爾的原子模型
We all are more or less doing “some” modeling works for our research. 我們或多或少都在為我們的研究進行「一些」建模工作。
What is Simulation? 什麼是模擬？
Computer simulation 電腦模擬
Predict the behavior of a physical system by solving corresponding models (GEs + BCs + ICs … ) using computers 通過使用計算機解決相應的模型（GEs + BCs + ICs … ）來預測物理系統的行為
>> Purposes of simulations: 模擬的目的：
>> Verify modeling works (models) >> 驗證建模工作（模型） >> Physics >> 物理學 >> Help design works >> 幫助設計作品 >> Engineering >> 工程
Relationship among 關係之間
Modeling, Experiment and Simulation 建模、實驗與模擬
>> Experiment and Simulation are the two ways to verify the model of a system. 實驗和模擬是驗證系統模型的兩種方法。
Experiment: 實驗： >> Expensive (typically) >> 昂貴（通常） >> Device fabrication, measurement equipment setup >> Plausible >> 裝置製造，測量設備設置 >> 可信的 >> Usually can verify the “model” under special conditions >> Compare with analytical solution of the “model” >> 通常可以在特定條件下驗證“模型” >> 與“模型”的解析解進行比較 >> Simulation: >> 模擬： >> Cheap (typically) >> 便宜（通常） >> Computer programming, software package >> 電腦程式設計，軟體套件 >> Acceptable but not satisfactory 可接受但不令人滿意 >> Can verify the “model” under arbitrary conditions >> 可以在任意條件下驗證“模型” >> Good for engineers (CAD and optimization) >> 對工程師有利（計算機輔助設計和優化）
MEMS Modeling 6 MEMS 建模 6
Modeling vs. Simulation ? 建模與模擬？
Modeling and Simulation bind together 建模與模擬緊密結合 >> Typical approach >> 典型方法
Modeling with the support of simulations 利用模擬進行建模 >> Insufficient modeling works result in insufficient understanding of the physical systems >> 模型建構不足導致對物理系統的理解不足 >> may apply wrong GEs, BCs … for simulation >> GIGO >> 可能對模擬 >> 應用錯誤的 GEs、BCs … GIGO
predict the behaviors of physical systems by specific rules/models (GEs + BCs + ICs … ) 透過特定的規則/模型（一般方程 + 邊界條件 + 初始條件……）預測物理系統的行為
CPU 中央處理器
>> Machine Learning: 機器學習：
models are unknown; synthesize models/rule based on given inputs/outputs. 模型是未知的；根據給定的輸入/輸出合成模型/規則。
GPU 圖形處理單元
Is Modeling Essential in MEMS ? 在微機電系統中建模是否必要？
Examples of MEMS Physics MEMS 物理的例子
SEM Picture of an RF switch RF 開關的掃描電子顯微鏡圖片
When operating in ambient, what is the switching time? 在環境中操作時，切換時間是多少？
Assume there is no damping (in vacuum), the simulated switching time is about 10-20 mus10-20 \mu \mathrm{~s}. 假設沒有阻尼（在真空中），模擬的開關時間約為 10-20 mus10-20 \mu \mathrm{~s} 。
Damping is huge in microsystems 阻尼在微系統中是巨大的
MEMS Modeling 12 MEMS 模型 12
Examples of MEMS Physics MEMS 物理的例子
micrograph of an optical modulator 光學調製器的顯微照片
What’s the Resonant Frequency? 共振頻率是什麼？
If there is no damping (in vacuum), the simulated resonant frequency is 2.02 Mhz (FEM modal analysis) 如果沒有阻尼（在真空中），模擬的共振頻率為 2.02 MHz（有限元素法模態分析）
Ability to import layout data from standard commercial layout CAD packages, i.e. Cadence, Mentor, etc. GDSII, CIF, DXF, IGES 能夠從標準商業佈局 CAD 套件中導入佈局數據，即 Cadence、Mentor 等。GDSII、CIF、DXF、IGES
files in- and out 進出文件
Non-Manhattan layout supported including “true” curves Layout generators 非曼哈頓佈局支援，包括“真”曲線佈局生成器
PROCESS DESCRIPTION 過程描述
Process Description Editor is 過程描述編輯器是
Flexible Multi Process 靈活多處理器
Emulator of: 模擬器：
Surface & Bulk Micromachining, LIGA, etc. 表面與體積微加工、LIGA 等。
Not a physical simulation 不是物理模擬
Material Property Database 材料性質數據庫
User Measured Values 使用者測量值
Foundry Database Available Basic Database Provided 鑄造數據庫可用 基本數據庫提供
3-D solid modeling 三維實體建模
Layout 佈局
Process Level 過程層級
Device Physical Level 裝置物理層
FEM/FDM/BEM field simuations 有限元素法/有限差分法/邊界元素法場模擬
Multi-physics, coupled-energy domain 多物理場，耦合能量領域
Device Behavior Level 裝置行為層級
System Level 系統層級
Energy Domains: Thermal, Mechanical, Electrical, Magnetic, Fluidic, Optical, Chemical … Domains 能量領域：熱能、機械能、電能、磁能、流體能、光學能、化學能……領域
Single Domains Simulation via Existing Specific Simulation Tools 透過現有特定模擬工具進行單一領域模擬
Multi-Physics Simulations Tools 多物理場模擬工具
Direct Coupling 直接耦合 >> e.g. piezoelectric analysis 例如壓電分析
Fully-coupled Newton methods for Nonlinear Problems 完全耦合的牛頓方法用於非線性問題
Sequential or Indirect Coupling 序列或間接耦合 >> Relaxation Method >> 放鬆方法
Surface Newton’s Method 表面牛頓法
Multi-Newton’s Method 多牛頓法
Benefits: Combining with the existence of commercially-available single 好處：結合現有的商業可用單一
domain (black-box approach) 領域（黑箱方法）
FEM and BEM Solvers 有限元素法與邊界元素法求解器
FEM 有限元素法
>> finite element method 有限元素法
meshing the volume of the computational domain 網格化計算域的體積 >> mature and widely used in industries >> 成熟且廣泛應用於各行各業 >> applications: >> 應用： >> Mechanical, Fluid and Thermal solvers. BEM 機械、流體和熱解算器。邊界元素法 >> boundary element method 邊界元素法 >> meshing the boundary of computational domain >> 網格化計算域的邊界 >> applications: >> 應用：
Electrostatics including dielectrics. 靜電學包括介電材料。
Number of Nodes (Linear, quadratic or high-order elements) 節點數（線性、二次或高階元素）
Quality of Meshing: Aspect Ratio, Distorsion 網格質量：長寬比，變形
Formulation 配方
Integration (Full or reduced integration) 整合（完全整合或部分整合）
Process Level 過程層級
Device Physical Level 裝置物理層
Device Behavior Level 裝置行為層級
Macromodels 巨型模型
model order reduction 模型階數縮減
System Level 系統層級
Device Behavior Level 裝置行為層級
Macro-Model (Compact Model, Reduced Order Model) of MEMS Device for System Level Simulation MEMS 設備的宏觀模型（緊湊模型、降階模型）用於系統級模擬
How to get an approximate model (ODE’s or DAE’s) from an field domain model (PDE’s)? 如何從場域模型（偏微分方程）獲得近似模型（常微分方程或微分代數方程）？
Types of Macromodels 巨型模型的類型
Signal flow approach 信號流方法
Transfer functions 傳遞函數
Matlab, simulink Matlab，Simulink
Power flow approach 功率流方法
Spice compitable 香料相容性
Saber with MAST AHDL MAST AHDL 的劍
Spectre with Verilog-A AHDL 使用 Verilog-A AHDL 的 Spectre
ELDO with HDL-A ELDO 與 HDL-A
IEEE standard 1076.1: VHDL-AMS (Very High Speed Integrated Circuit HDL-Analog Mixed Signal) IEEE 標準 1076.1：VHDL-AMS（非常高速集成電路硬體描述語言-類比混合信號）
Why macro-models (reduced order models) ? 為什麼使用宏觀模型（降階模型）？
Efficient (fast) simulation of accurate and physically-correct models. 高效（快速）模擬準確且物理正確的模型。
Transient and spectral analysis 瞬態與頻譜分析
Efficient (fast) simulation of a whole MEMS device including sensing, driving, controlling circuitry and mu\mu Fluidics components 高效（快速）模擬整個 MEMS 裝置，包括感測、驅動、控制電路和流體元件
Transient and spectral analysis 瞬態與頻譜分析
Reduce the DOF of the system from tens of thousands (FEM/BEM approaches) to a much lower DOF 將系統的自由度從數萬（有限元素法/邊界元素法）降低到更低的自由度
Bolometers, Thermopiles and QWIPs 波洛米特、熱電堆和量子點光電探測器
Yao-Joe Yang (楊燿州), Professor 楊燿州教授
Department of Mechanical Engineering 機械工程系
National Taiwan University 國立臺灣大學
Fig. 14. IR inage of tank produced with 512 xx512512 \times 512 scence generator aray (image viewed with IR camera) 圖 14. 使用 512 xx512512 \times 512 場景生成器陣列製作的坦克的紅外影像（使用紅外相機查看的影像）
Fig. 13. IR image with 240 xx336240 \times 336 microbolometer camera 圖 13. 使用 240 xx336240 \times 336 微熱計相機的紅外圖像
Outline 大綱
Introduction to Infrared Detectors 紅外探測器簡介
Description of Three Types of Infrared Detectors 三種紅外線探測器的描述 >> thermal detectors : >> 熱檢測器：
Performance Index 績效指標
Comparison and Applications 比較與應用
What is 什麼是
Infrared Detectors 紅外探測器
Thermal Radiation : 熱輻射：
radiation emitted by any object at a rate and a wavelength distribution determined by the temperature of the object 任何物體以其溫度所決定的速率和波長分佈發射的輻射 >> thermal radiation through atmosphere is attenuated by scattering and absorption process >> 熱輻射在大氣中受到散射和吸收過程的衰減
Why Infrared (IR) Detecting 為什麼使用紅外線（IR）檢測 >> maximum radiation occurs around waveband of 2 - 15 mum15 \mu \mathrm{~m} >> 最大輻射發生在波段 2 - 15 mum15 \mu \mathrm{~m} 附近
number of photons and emission power vs. wavelength 光子數量與發射功率對波長的關係
infrared can penetrate the atmosphere further than visible light because the wavelength is longer. 紅外線能夠比可見光更深入地穿透大氣，因為其波長較長。 >> Two infrared windows with low absorption by gas molecules: 兩個對氣體分子吸收率低的紅外窗口：
Thermal Detectors 熱檢測器 >> two-stage transducers >> 雙階轉換器
& radiation absorbing & 輻射吸收
photon energy is converted to thermal energy in the absorber 光子能量在吸收體中轉換為熱能
temperature measurement 溫度測量
temperature change is converted to an electrical signal by temperature measurement mechanism 溫度變化通過溫度測量機制轉換為電信號
temperature measure mechanisms determine the types of thermal detectors 溫度測量機制決定了熱檢測器的類型
Thermal Detectors 熱檢測器
Types of Thermal Detectors 熱檢測器的類型 >> all of them have radiation absorbers, but have different types of temperature measurement mechanisms >> 它們都有輻射吸收器，但擁有不同類型的溫度測量機制
IR photons excite electrons to higher energy states and thus modulate some electronic property of the sensor. 紅外光子使電子激發至更高的能量狀態，從而調節傳感器的某些電子特性。
The energy of an incident photon must be high enough to excite an electron to an available state. 入射光子的能量必須足夠高，以激發電子至可用狀態。
To avoid large background signals and noise due to thermal carrier excitation, the sensor has to be cooled to cryogenic temperatures. 為了避免由於熱載流子激發而產生的大背景信號和噪聲，傳感器必須冷卻至低溫。
HgCdTe has the best sensitivity of IR absorption, but its low fabrication process yield has not been solved even after about 40 years since the first device was made. HgCdTe 具有最佳的紅外吸收敏感度，但自從約 40 年前製造出第一個裝置以來，其低製造過程產量的問題仍未解決。
-Thermal time constant tau=C//G\tau=C / G -熱時間常數 tau=C//G\tau=C / G
Basic Heat Transfer 基本熱傳遞
Analysis for Thermal 熱分析
Detectors 檢測器
Bolometer 波洛米特
A bolometer measures temperature changes via temperature dependent resistance of a resistor which is in thermal contact with the absorber 一種輻射計通過與吸收體熱接觸的電阻的溫度依賴性電阻來測量溫度變化
Delta R=alpha R Delta T\Delta R=\alpha R \Delta T
Assume constant current flowing across the resistor 假設恆定電流流經電阻器
V_(s)=i_(b)Delta R=i_(b)alpha R Delta T=(i_(b)alpha R etaP_(0))/(G(1+omega^(2)tau^(2))^(1//2))V_{s}=i_{b} \Delta R=i_{b} \alpha R \Delta T=\frac{i_{b} \alpha R \eta P_{0}}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
The responsivity R\boldsymbol{R} of an IR pixel is defined as the output signal (voltage or current) divided by the input radiant power falling on the pixel 紅外像素的響應度 R\boldsymbol{R} 定義為輸出信號（電壓或電流）除以落在像素上的輸入輻射功率
R=(i_(b)alpha R eta)/(G(1+omega^(2)tau^(2))^(1//2))\boldsymbol{R}=\frac{i_{b} \alpha R \eta}{G\left(1+\omega^{2} \tau^{2}\right)^{1 / 2}}
Basic Heat Transfer Analysis for 基本熱傳遞分析
Thermal Detectors 熱檢測器
Thermoplie 熱電堆
Thermopile is a series of thermocouples, which apply the Seebeck effect to measure temperature 熱電堆是一系列熱電偶，利用塞貝克效應來測量溫度
V_(s)=N(S_(1)-S_(2))Delta TV_{s}=N\left(S_{1}-S_{2}\right) \Delta T
Assume constant current flowing across the resistor 假設恆定電流流經電阻器
AA and BB are two different materials Temperature difference at the two junction results in a voltage VV. AA 和 BB 是兩種不同的材料，兩個接點之間的溫度差會產生電壓 VV 。
The responsivity R\boldsymbol{R} of an IR pixel is defined as the output signal (voltage or current) divided by the input radiant power falling on the pixel. 紅外像素的響應度 R\boldsymbol{R} 定義為輸出信號（電壓或電流）除以落在像素上的輸入輻射功率。
The absorber (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) is raised above the Si substrate, supported by two legs at diagonally opposite corners. 吸收器 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) 被抬高於矽基板之上，並由位於對角相對角落的兩條腿支撐。
Electronics at each pixel are embedded in the substrate. 每個像素的電子元件嵌入在基板中。
Vanadium oxide (VO_(x))\left(\mathrm{VO}_{x}\right) (the thermally sensitive resistive material) are deposited on the absorber. 氧化釩 (VO_(x))\left(\mathrm{VO}_{x}\right) （熱敏感電阻材料）被沉積在吸收體上。
In 2D array 在二維陣列中
Honeywell Bolometer: 霍尼韋爾波洛米特
Suspended absorber 懸浮吸收器
excellent thermal isolation (small G) 優異的熱隔離（小 G）
Thin membrane of absorber 吸收器的薄膜 >> small heat capacity (small C) >> 小熱容 (小 C)
keep time constant (C/G) small but with excellent thermal isolation 保持時間常數 (C/G) 小但具有優良的熱隔離性
integrated transistor switch 集成晶體管開關 >> better readout performance >> 更佳的讀取性能
Stress of Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} film is annoying Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 膜的應力令人煩惱
need tremendous work to control the stress to prevent the suspended structure from tilting or touching substrate 需要大量的工作來控制壓力，以防止懸浮結構傾斜或接觸基材 >> Honeywell solved this problem. 霍尼韋爾解決了這個問題。
JPL Thermopile JPL 熱電堆
The 0.6 mum0.6 \mu \mathrm{~m} absorber (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) is a microbridge membrane released by Bulk micromaching 0.6 mum0.6 \mu \mathrm{~m} 吸收器 (Si_(3)N_(4))\left(\mathrm{Si}_{3} \mathrm{~N}_{4}\right) 是一種由大規模微加工技術釋放的微橋膜
thermoelectric materials (Bi_(2)Te_(3):}\left(\mathrm{Bi}_{2} \mathrm{Te}_{3}\right. and 熱電材料 (Bi_(2)Te_(3):}\left(\mathrm{Bi}_{2} \mathrm{Te}_{3}\right. 和 Bi_(0.55)Sb_(1.45)Te_(3.6)\mathrm{Bi}_{0.55} \mathrm{Sb}_{1.45} \mathrm{Te}_{3.6} ) are deposited alternatively on both ends of the bridge Bi_(0.55)Sb_(1.45)Te_(3.6)\mathrm{Bi}_{0.55} \mathrm{Sb}_{1.45} \mathrm{Te}_{3.6} ）交替地沉積在橋的兩端
A gold interconnect connects the two thermocouples groups on both ends 一條金屬互連連接了兩端的兩組熱電偶 Au//Ti\mathrm{Au} / \mathrm{Ti} contacts are used for connecting different materials. Au//Ti\mathrm{Au} / \mathrm{Ti} 接觸點用於連接不同的材料。
JPL Thermopile: JPL 熱電堆：
Characteristic 特徵
Thin Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} bridge made by bulk micromachining - fair thermal isolation 薄 Si_(3)N_(4)\mathrm{Si}_{3} \mathrm{~N}_{4} 橋樑由大宗微機械加工製成 - 良好的熱隔離
11 thermocouple elements for each pixel 每個像素有 11 個熱電偶元件 >> increase responsivity >> 增加反應性 >> trade-off between thermal isolation design and number of thermocouples very simple electronics 熱隔離設計與熱電偶數量之間的權衡非常簡單的電子設備 >> self-generating Seebeck effect, readout circuit is very simple 自生成的塞貝克效應，讀取電路非常簡單
special backside KOH etching 特殊背面氫氧化鉀蝕刻 >> Need special etching fixture to protect the device during etching >> 需要特殊的蝕刻夾具以保護設備在蝕刻過程中 >> if membranes break during etching, the KOH will damage the thermoelectric material in the front side 如果在蝕刻過程中膜破裂，氫氧化鉀將損壞前側的熱電材料
Brief Quantum Mechanics 簡明量子力學
Background in QWIPs QWIPs 的背景
intersubband absorption mechanism 子帶間吸收機制
>> transition between energy levels within the conduction (or valence) band >> 在導電帶（或價帶）內的能量級之間的轉變 >> photoionized electrons are collected by a small bias applied on both side of the well >> 照射電離的電子是通過施加在井兩側的小偏壓來收集的
superlattice structure of AIGaAs/GaAs AIGaAs/GaAs 超晶格結構
a stack of quantum wells in order to generate more photoionizied electrons 一堆量子井以產生更多光電離電子
Brief Quantum Mechanics 簡明量子力學
Background in QWIPs QWIPs 的背景
For infinite-high-barrier well, the 對於無限高障礙井，
energy level is given by 能量水平由以下公式給出
by changing the quantum-well width L_(w)L_{w} this intersubband transition energy can be varied over a wide range of wavelength (2 20 mum\mu \mathrm{m} ). 透過改變量子井的寬度 L_(w)L_{w} ，此種子帶間的躍遷能量可以在廣泛的波長範圍內變化（2 20 mum\mu \mathrm{m} ）。
Three Intersubband Transition 三重子帶間躍遷
Types of QWIPs QWIP 的類型
Bound-to-bound 邊界到邊界 >> narrow absorption spectrum >> 狹窄吸收光譜 >> need higher bias voltage to collect photoexcited electrons; high dark current >> 需要更高的偏壓電壓來收集光激發的電子；高暗電流
Bound-to-continuum 綁定於連續體 >> wide absorption spectrum >> 寬吸收光譜 >> need lower bias voltage, lower dark current than B-to-B >> 需要比 B-to-B 更低的偏壓和更低的暗電流 >> better design than B-to-B >> 比 B-to-B 更好的設計
Bound-to-quasibound 束縛至準束縛 >> better design than bound-tocontinuum --> next viewgraph >> 比連續體更好的設計 --> 下一張幻燈片
Comparison of B-to-B and B2B 與 B2C 的比較
B-to-QB Designs B-to-QB 設計
QWIP’s killer : dark current QWIP 的致命因素：暗電流
Thermionic emission dark current is the major portion of dark noise as T > 45 K 熱電子發射暗電流是當溫度高於 45 K 時暗噪聲的主要部分
for the bound-to-continuum design, the E_(T)\mathrm{E}_{\mathrm{T}} is lower than E_(p)E_{p}, thermionic emission is obvious 對於束縛於連續體設計， E_(T)\mathrm{E}_{\mathrm{T}} 低於 E_(p)E_{p} ，熱電子發射明顯
for the bound-to-quasibound design, E_(T)=E_(P)\mathrm{E}_{\mathrm{T}}=\mathrm{E}_{\mathrm{P}}, so the barrier for the thermionic emission is higher at the same temperature, thus reduces the dark current 對於束縛到準束縛的設計， E_(T)=E_(P)\mathrm{E}_{\mathrm{T}}=\mathrm{E}_{\mathrm{P}} ，因此在相同溫度下，熱電子發射的障礙較高，從而降低了暗電流
Since E_(p)E_{p} of B-to-QB is right on the top of the well, need similar bias voltage as the B-to-C case 由於 E_(p)E_{p} 的 B 到 QB 正好位於井的頂部，因此需要類似於 B 到 C 情況的偏壓電壓 L_(w2)\mathrm{L}_{\mathrm{w} 2} L_(w3)\mathrm{L}_{\mathrm{w} 3}
Absorption vs. Wavelength 吸收與波長
Normalized absorption vs. 標準化吸收與
wavelength 波長
B-to-C is much broader than B-to-B and BB-to-QB because of more delocalized excited state. B-to-C 的範疇遠比 B-to-B 和 BB -to-QB 更廣，因為其激發態更為去局部化。
Due to conservation of integrated oscillator strength, the absorption coefficient of the BB-to-C is lower than those of B-to-B and B-to-QB. 由於整合振盪強度的守恆， BB 到 C 的吸收係數低於 B 到 B 和 B 到 QB 的吸收係數。
JPL QWIP
Superlattice structure of 50 periods of 6.5 nm well of GaAs and 60 nm barrier of Al_(0.15)Ga_(0.85)\mathbf{A l}_{0.15} \mathbf{G a}_{0.85} As 50 個周期的 6.5 納米 GaAs 井和 60 納米 Al_(0.15)Ga_(0.85)\mathbf{A l}_{0.15} \mathbf{G a}_{0.85} As 障礙的超晶格結構
The superlattice is sandwiched between 0.5 超晶格夾在 0.5 之間
GaAs substrate GaAs 基板
JPL QWIP:
Bound-to-quasibound design 束縛至準束縛設計
reduce dark current 降低暗電流
mature GaAs MBE fabrication process 成熟的砷化鎵分子束外延製程 > 128 xx128>128 \times 128 array > 128 xx128>128 \times 128 陣列 >> very uniform superlattice ( 0.1 % non-uniformity) >> 非常均勻的超晶格 (0.1% 非均勻性)
very high yield ( 99.9%99.9 \% ) 非常高的產量 ( 99.9%99.9 \% )
hybrid readout electronics 混合讀出電子學 >> CMOS multiplexer is bonded to the array >> CMOS 多路複用器與陣列連接 >> expensive but not optimized >> 昂貴但未經優化
random reflector design 隨機反射器設計 >> a factor of eight enhancement in responsivity compared with 45^(@)45^{\circ} illumination of test structure. (to be explained) >> 與 45^(@)45^{\circ} 測試結構的照明相比，響應性增強了八倍。
Periodic grating 週期性光柵
Previous approach 先前的方法 >> all the incident radiation escape after the second reflection from the grating surface >> 所有的入射輻射在第二次從光柵表面反射後逃逸 >> A factor of 2 or 3 responsivity enhancement compared to the 45^(@)45^{\circ} illumination geometry 相較於 45^(@)45^{\circ} 照明幾何，響應增強的因素為 2 或 3 倍
(a) GRating PIXELMESA
JPL QWIP:
Light Coupling 光耦合
Random reflector 隨機反射器 >> The random structure on top of the detector prevents the light from being diffracted normally backward after the second bounce 隨機結構位於探測器上，防止光在第二次反射後正常向後衍射 >> light is scattered at a different random angle and the only chance to escape out of the detector is when reflected toward the surface within the critical angle of the normal ( 17^(@)17^{\circ} for the GaAs/Air interface) >> 光以不同的隨機角度散射，只有在反射向表面並位於法線的臨界角內時（ 17^(@)17^{\circ} 對於 GaAs/空氣界面），才有機會逃出檢測器 >> a factor of 8 responsivity enhancement compared with 45^(@)45^{\circ} illumination face case >> 與 45^(@)45^{\circ} 照明面案例相比，響應度增強的因素為 8
RANDOM REFLECTOR 隨機反射器
Normalized Detectivity ( D^(**)D^{*} ) 標準化檢測能力 ( D^(**)D^{*} ) > D=1//NEP>D=1 / N E P; NEP : noise equivalent power > D=1//NEP>D=1 / N E P ; NEP : 噪聲等效功率 > D^(**)=(AB)^(1//2)D>D^{*}=(A B)^{1 / 2} D; normalized to square root of area and bandwidth > D^(**)=(AB)^(1//2)D>D^{*}=(A B)^{1 / 2} D ；標準化為面積和帶寬的平方根 >> the less the noise, the higher the detectivity 噪音越小，檢測能力越高
Noise Equivalent Temperature Difference ( NETD ) 噪聲等效溫度差 (NETD) >> Change in temperature of a large thermal radiating object makes the detector’s signal-to-noise ratio equals to one >> 大型熱輻射物體的溫度變化使檢測器的信號與噪聲比等於一 >> the smallest resolvable temperature difference of the radiating object by the detector >> 探測器可解析的輻射物體的最小可解析溫度差
JPL THERMOPILE DIMENSIONS
Pixel size 1500 mumxx71 mumxx0.6 mum
Pitch distance 75 mum
Number of pixel (linear) 63
Number of thermocouple on one pixel 11
HONEYWELL BOLOMETER
Pixel size 50 mumxx50 mumxx0.5 mum
Gap between absorber and subsrate 1-2 mum
Array size 512 xx512
JPL QWIP
Pixel size 38 mumxx38 mum
Number of wells (superlattice) 50
Pitch distance 50 mum
Array size 128 xx128| JPL THERMOPILE | DIMENSIONS |
| :---: | :---: |
| Pixel size | $1500 \mu \mathrm{~m} \times 71 \mu \mathrm{~m} \times 0.6 \mu \mathrm{~m}$ |
| Pitch distance | $75 \mu \mathrm{~m}$ |
| Number of pixel (linear) | 63 |
| Number of thermocouple on one pixel | 11 |
| HONEYWELL BOLOMETER | |
| Pixel size | $50 \mu \mathrm{~m} \times 50 \mu \mathrm{~m} \times 0.5 \mu \mathrm{~m}$ |
| Gap between absorber and subsrate | 1-2 $\mu \mathrm{m}$ |
| Array size | $512 \times 512$ |
| JPL QWIP | |
| Pixel size | $38 \mu \mathrm{~m} \times 38 \mu \mathrm{~m}$ |
| Number of wells (superlattice) | 50 |
| Pitch distance | $50 \mu \mathrm{~m}$ |
| Array size | $128 \times 128$ |
Comparison and Discussion 比較與討論
Honeywell Bolometer 霍尼韋爾波洛米特
excellent performance, excellent integration, high potential of commercialization for civilian applications 優異的表現、卓越的整合、高度的商業化潛力以應用於民用領域 >> at T_(D)=T_(B)=300 KT_{D}=T_{B}=300 K and G=1e^(-7)G=1 e^{-7} W/K, experimental NETD=39 mK, 在 T_(D)=T_(B)=300 KT_{D}=T_{B}=300 K 和 G=1e^(-7)G=1 e^{-7} W/K 時， >> ，實驗 NETD=39 mK， >> the device G=1e^(-7)W//K\mathrm{G}=1 \mathrm{e}^{-7} \mathrm{~W} / \mathrm{K} is the lowest one for the working thermal detectors >> 該裝置 G=1e^(-7)W//K\mathrm{G}=1 \mathrm{e}^{-7} \mathrm{~W} / \mathrm{K} 是工作熱探測器中最低的
Since G\mathbf{G} is very difficult to improve due to electrical interconnect, finding a material with better temperature coefficient of resistance (TCR) may be a easier way to improve the performance. 由於 G\mathbf{G} 因電氣互連而難以改善，尋找具有更好溫度係數的材料可能是一種更簡單的提高性能的方法。
Or, increase the filling factor (only 50%50 \% right now) to increase the Detectivity, which is proportional to square root of absorption area. 或者，增加填充因子（目前僅為 50%50 \% ）以提高檢測能力，該能力與吸收面積的平方根成正比。
Comparison and Discussion 比較與討論
JPL Thermopile JPL 熱電堆
>> large pixel size; linear array >> 大像素尺寸；線性陣列
expensive and low yield (special thermoelectric material and not compatible with CMOS process) 昂貴且產量低（特殊熱電材料，且不兼容 CMOS 工藝） >> highest detectivity (1.4 xx10^(9)cmHz^(1//2)//W)\left(1.4 \times 10^{9} \mathrm{cmHz}^{1 / 2} / \mathrm{W}\right) for thermopiles, >> 最高檢測能力 (1.4 xx10^(9)cmHz^(1//2)//W)\left(1.4 \times 10^{9} \mathrm{cmHz}^{1 / 2} / \mathrm{W}\right) 用於熱電堆， >> fundamental limit of detectivity is 2xx10^(10)cmHz^(1//2)//W2 \times 10^{10} \mathrm{cmHz}^{1 / 2} / \mathrm{W} >> 偵測能力的基本極限是 2xx10^(10)cmHz^(1//2)//W2 \times 10^{10} \mathrm{cmHz}^{1 / 2} / \mathrm{W} >> key element for monochromatic detectors or spectrometers >> 單色檢測器或光譜儀的關鍵元素
Fresnel zone plate Linear thermopile array 菲涅耳區域板 線性熱電堆陣列
Comparison and Discussion 比較與討論
JPL QWIP
>> highly uniform; excellent performance >> 高度均勻；卓越的性能 >> dark current noise limit of QWIPs is strongly dependent on the temperature >> 量子井探測器的暗電流噪聲極限與溫度有很大關聯 >> For longer wavelength, lower operation temperature is needed in order to push the device performance to BLIP 對於較長的波長，需要較低的操作溫度以推動設備性能達到 BLIP >> operating temperature =45K=45 \mathrm{~K} >> 操作溫度 =45K=45 \mathrm{~K}
integration of GaAs readout circuit is a possible way to improve (increase) the operating temperature 將 GaAs 讀出電路的整合是一種提高（增加）操作溫度的可能方法
Comparison of Applications 應用比較
Honeywell Bolometer 霍尼韋爾波洛米特
JPL Thermopile JPL 熱電堆
JPL QWIP
Applications 應用
警察、消防員、夜間駕駛等。
Police, firefighters,
night driving, e.t.c.
Police, firefighters,
night driving, e.t.c.| Police, firefighters, |
| :--- |
| night driving, e.t.c. |
Space applications,
Detecting objects with
extreme difference of
temperature spots| Space applications, |
| :--- |
| Detecting objects with |
| extreme difference of |
| temperature spots |
Thermal Radiation : 熱輻射： >> radiation emitted by any object at a rate and a wavelength distribution determined by the temperature of the object >> 輻射由任何物體以由物體的溫度決定的速率和波長分佈發射 >> thermal radiation through atmosphere is attenuated by scattering and absorption process >> 熱輻射在大氣中受到散射和吸收過程的衰減
Why Infrared (IR) Detecting >> maximum radiation occurs around waveband of 2 - 15 mum15 \mu \mathrm{~m} 為什麼紅外線（IR）檢測 >> 的最大輻射發生在波段約為 2 - 15 mum15 \mu \mathrm{~m}
number of photons and emission power vs. wavelength 光子數量與發射功率對波長的關係
Fabricating Suspended MEMS structures using ICP in Single Run 使用單次運行中的 ICP 製造懸浮 MEMS 結構
Passivation Etching Active Active Time Time 鈍化蝕刻 主動 主動時間 時間
Alternating etching/passivation steps 交替蝕刻/鈍化步驟
Etching step: 蝕刻步驟：
Ion bombardment provides etch directionality 離子轟擊提供蝕刻方向性
Directional etching removes polymer from base of structure at much higher rate than from side-walls 定向蝕刻以遠高於側壁的速率從結構基部去除聚合物
-SF _(6){ }_{6} plasma etches silicon after passivation removal -SF _(6){ }_{6} 等離子體在去除鈍化層後蝕刻矽
RF coil power, SF_(6)\mathrm{SF}_{6} flow rate (sccm) and pressure (mT) are key parameters for controlling Si etch rate RF 線圈功率、 SF_(6)\mathrm{SF}_{6} 流量（sccm）和壓力（mT）是控制矽蝕刻速率的關鍵參數
High RF coil power increases F etchant species concentration by enhanced SF_(6)S F_{6} dissociation 高射頻線圈功率通過增強 SF_(6)S F_{6} 解離來提高 F 蝕刻劑物種濃度
At high RF coil power, high SF_(6)\mathrm{SF}_{6} flow rate further increases F etchant species concentration 在高射頻線圈功率下，高 SF_(6)\mathrm{SF}_{6} 流量進一步增加了 F 蝕刻劑物種的濃度
High pressure results in higher concentration of F etchant species 高壓導致氟蝕刻劑物種的濃度增加
Dept. of Mech. Eng., National Taiwan University 國立台灣大學機械工程系
Etch / Pass. Time ratio v.s profile changing 蝕刻/通過時間比與輪廓變化
Figure The experimental result of the etching of trenches using three etching steps with different etching/polymerization time configurations. 7s//7s,9s//7s7 \mathrm{~s} / 7 \mathrm{~s}, 9 \mathrm{~s} / 7 \mathrm{~s} and 5s//7s5 \mathrm{~s} / 7 \mathrm{~s} are used sequentially. 圖示 使用三個不同蝕刻/聚合時間配置的蝕刻步驟進行溝槽蝕刻的實驗結果。 7s//7s,9s//7s7 \mathrm{~s} / 7 \mathrm{~s}, 9 \mathrm{~s} / 7 \mathrm{~s} 和 5s//7s5 \mathrm{~s} / 7 \mathrm{~s} 依次使用。
each for 5 min . 每個持續 5 分鐘。
不同溝寬底部側邊之表面粗度-1
不同溝寬底部側邊之表面粗度-2
Fabricating Suspended MEMS Structures Using ICP in Single Run 利用單次運行中的 ICP 製造懸浮 MEMS 結構
Motivations 動機
Traditional approaches for releasing structures are either 傳統的結構釋放方法要麼是
Complicated 複雜
required other 所需其他
deposition/lithography/doping processes before structure releasing 沉積/光刻/摻雜過程在結構釋放之前
Expensive 昂貴
if using SOI wafer 如果使用 SOI 晶圓
What is suspended structures 懸掛結構是什麼
單層Test Device結構製作 單層測試裝置結構製作
Process Step 過程步驟
Trench etching (ICP-RIE ASE process) 溝槽蝕刻（ICP-RIE ASE 過程）
