3 Power supply

The device operates on system. Transient operation for these systems can reach maximum. Particular care is to be taken in PCB manufacturing to keep thermal dissipation to a reasonable level.
该设备在 系统上运行。这些系统的瞬态工作最高可达 。在 PCB 制造过程中应特别注意将热耗散保持在合理水平。

All electrical characteristics are valid for the following conditions unless otherwise noted:
除非另有说明，否则所有电气特性均在以下条件下有效：

.

Table 5. Configuration and control DC specifications
表 5.配置和控制直流电规格

The boost regulator can be enabled or disabled via SPI depending on the needs of the application with respect to the operating battery level. It features an integrated power stage and operates at to allow the use of external low cost inductor. The current capability should be enough to grant full I/O pin supply and minimal operation.
升压稳压器可根据应用对工作电池电量的需求，通过 SPI 启用或禁用。它采用集成式功率级，工作电压为 ，允许使用外部低成本电感器 。其电流能力应足以为所有 I/O 引脚供电，并将 操作降至最低。

When not used, BSTSW pin can be connected to ground and VBST directly to the protected battery line. The device enables or keeps disabled the boost converter at start-up depending on the external circuitry: if BSTSW pin is shorted to ground, the boost is disabled at power up and kept disabled; in case the BSTSW experiences a high voltage at power up, given by battery connection through the inductor, the boost is enabled. This condition is reported via SPI with bit BOOST_KEPT_OFF of SUPPLY_CONTROL_2 register (it means that boost has been kept off and will not operate).
不使用时，BSTSW 引脚可连接到地，VBST 直接连接到受保护的电池线路。根据外部电路的不同，该器件可在启动时启用或禁用升压转换器：如果 BSTSW 引脚与地短路，则升压转换器在启动时被禁用，并保持禁用状态；如果 BSTSW 在启动时出现高电压（通过电感与电池连接），则升压转换器被启用。这种情况将通过 SPI 寄存器 SUPPLY_CONTROL_2 的 BOOST_KEPT_OFF 位进行报告（这意味着升压被关闭，不会工作）。

Boost converter diagnostics include under voltage, reported via SPI and FAULT pin (if the regulator is enabled). The integrated FET featuring the boost switch is protected against short to battery by means of a thermal shutdown circuit. When thermal fault is detected the FET is switched off and latched in this state until the related fault flag is read. In case of loss of ground the FET is switched off and automatically reactivated as soon as ground connection is restored. Over-voltage protection from load-dump and inductive flyback is provided via an active clamp and a disable circuitry. A dedicated circuitry is implemented to keep the boost off at start-up till the voltage difference between VB and VBST pins is lower than BST_DISABLETH in order to reduce in-rush current and diagnose VBST pin loss condition or diode loss. An SPI bit is present to report output of this comparator (bit BOOST_READY of SUPPLY_CONTROL_2 register goes high when VBST>=VBBST_DISABLETH).
升压转换器诊断功能包括通过 SPI 和 FAULT 引脚（如果稳压器已启用）报告电压不足。通过热关断电路，具有升压开关功能的集成 FET 可防止与电池短路。当检测到热故障时，场效应晶体管将关闭并保持此状态，直到读取相关故障标志。在失地的情况下，场效应管将被关闭，一旦接地连接恢复，场效应管将自动重新激活。通过有源箝位和禁用电路，可提供来自负载跳变和电感反激的过压保护。为了减少浪涌电流和诊断 VBST 引脚损耗或二极管损耗，还采用了一种专用电路，使升压电路在启动时保持关闭状态，直到 VB 和 VBST 引脚之间的电压差低于 BST_DISABLETH。SPI 位用于报告比较器的输出（当 VBST>=VBBST_DISABLETH 时，Supply_CONTROL_2 寄存器的 BOOST_READY 位变为高电平）。

State of boost regulator is reported via SPI bit BOOST_ON_FLAG in register SUPPLY_CONTROL_2. In case boost is disabled due to diagnostic or battery voltage above output regulation voltage this bit is cleared to 0 .
升压调节器的状态通过寄存器 SUPPLY_CONTROL_2 中的 SPI 位 BOOST_ON_FLAG 报告。如果由于诊断或电池电压高于输出调节电压导致升压被禁用，则该位清零为 0。

Figure 3. Boost regulator block diagram
图 3.升压稳压器框图

All electrical characteristics are valid for the following conditions unless otherwise noted:
除非另有说明，否则所有电气特性均在下列条件下有效：

VBATP
VBATP

Table 6. Boost regulator electrical characteristics
表 6.升压稳压器电气特性

Table 6. Boost regulator electrical characteristics (continued)
表 6.升压稳压器电气特性（续）

The internal analog and digital part is supplied by the supply voltage VBST through integrated voltage regulators. The generated voltage is monitored. In case of under/overvoltage, the device performs a power on reset (POR).
内部模拟和数字部分通过集成稳压器由电源电压 VBST 供电。产生的电压受到监控。如果出现欠压/过压，设备会执行上电复位 (POR)。

An undervoltage condition on VBST will lead to an internal reset of the IC. Above this undervoltage threshold, full functionality is granted.
VBST 欠压将导致集成电路内部复位。超过该欠压阈值，则可实现全部功能。

The device integrates two separated instances of Bandgap voltage regulators; one of these bandgaps is used as voltage reference for the internal regulators, while the other one is used for monitoring the voltage levels.
该器件集成了两个独立的带隙电压调节器；其中一个带隙用作内部调节器的电压基准，而另一个则用于监控电压水平。

GNDD ground line is protected against ground loss scenarios. In case GNDD line would be
GNDD 接地线可防止接地损失。如果 GNDD 线路

GNDD is used for digital logic and charge pump while GNDA is used for analog blocks.
GNDD 用于数字逻辑和电荷泵，而 GNDA 用于模拟模块。

GNDBST is used for boost regulator only.
GNDBST 仅用于升压稳压器。

The device returns to normal operation with full functionality as soon as the POR is released.
POR 释放后，设备立即恢复正常运行，并具备全部功能。

Table 7. Internal supply electrical characteristics
表 7.内部电源电气特性

The input pin IGN can be used as a wake up source connection. In case the voltage on IGN pin raises above WAKE for an interval longer than WAKE , the device wakes up.
输入引脚 IGN 可用作唤醒源连接。如果 IGN 引脚上的电压高于 WAKE ，且时间间隔长于 WAKE ，设备就会被唤醒。

longer than . This input can be connected to ignition battery switches or transceiver inhibit outputs. A filter time is implemented to reject spurious glitches. The filter time is started when the input signal exceeds the specified threshold.
长于 。该输入可连接至点火电池开关或收发器抑制输出。滤波时间用于抑制杂散脉冲。当输入信号超过指定阈值时，滤波时间启动。

All electrical characteristics are valid for the following conditions unless otherwise noted:
除非另有说明，否则所有电气特性均在以下条件下有效：

VBATP .
VBATP .

Table 8. Wake-up input electrical characteristics
表 8.唤醒输入电气特性

A two-stage charge pump is integrated to supply the high voltage circuit in the VPREREG and VCORE regulators and in the pump motor and fail safe pre-drivers.
VPREREG 和 VCORE 稳压器以及泵电机和故障安全预驱动器中都集成了一个两级电荷泵，为高压电路供电。

The charge pump is supplied by the rail connected to VBST pin. External charging capacitors are used to achieve a high current capability.
充电泵由连接至 VBST 引脚的导轨供电。外部充电电容用于实现高电流能力。

Figure 4. Charge pump block diagram
图 4.充电泵框图

It features a current limitation protection when either or is being charged up. The charge pump is protected against over temperature with dedicated thermal sensor. In standby mode the charge pump is disabled.
当 或 充电时，它具有电流限制保护功能。电荷泵通过专用热传感器提供过温保护。在待机模式下，电荷泵处于禁用状态。

In case the CP output voltage remains too low for longer than tfCP the CP LOW bit is latched, which leads to shutdown of VPREREG, pump motor driver and fail safe driver. In turn, under voltage of VPREREG leads to shutdown of VCC, VCC5 and VCORE regulators.
如果 CP 输出电压过低的时间超过 tfCP，CP LOW 位将被锁存，从而导致 VPREREG、泵电机驱动器和故障安全驱动器关机。反过来，VPREREG 电压过低会导致 VCC、VCC5 和 VCORE 稳压器关机。

A second undervoltage threshold is present with a higher value. It can be used together with PDG turn-on threshold voltage to detect that low charge pump voltage is responsible for low PDG ON voltage.
第二个欠压阈值为 ，其值较高。它可与 PDG 接通阈值电压一起用于检测 PDG 接通电压过低是否与电荷泵电压过低有关。

Table 9. Charge pump electrical characteristics
表 9.充电泵电气特性

The integrated buck regulator provides a reduced voltage supply to the remaining regulators and to the WSS / tracking interface. Its default output level can be further increased to via register of BUCK VOLTAGE SELECTION in SPI.
集成降压稳压器为其余稳压器和 WSS/跟踪接口提供降压电源。其默认输出电平 可通过 SPI 中的降压电压选择寄存器进一步提高至 。

This regulator is protected against short circuits and over temperature with dedicated thermal sensor, and an over/under voltage monitor is implemented. VPREREG itself is not shut down in case of over/under voltage at its output. VPREREG itself is not shut down in case of overcurrent, only in case of over temperature the regulator is switched off.
该稳压器采用专用热传感器进行短路和过热保护，并实施过压/欠压监控。在输出电压过高/过低的情况下，VPREREG 本身不会关闭。VPREREG 本身在电流过大时不会关闭，只有在温度过高时才会关闭稳压器。

This regulator is not protected against diode loss and the IC may be irreparably damaged due to diode loss.
该稳压器没有二极管损耗保护，集成电路可能会因二极管损耗而受到不可修复的损坏。

Under voltage of VPREREG (VPREREG_UV) leads to shutdown of VCC, VCC5 and regulators.
VPREREG 电压过低 (VPREREG_UV) 会导致 VCC、VCC5 和 稳压器关机。

Note: In particular corner conditions, the VPREREG output could be affected by transient overvoltage (clamped to VBST) once the Wake-up input is lowered. In these conditions the integrated high-side regulator FET is kept OFF through a passive switch OFF, that may lead the output to bounce. For this reason, it is not recommended the VPREREG to supply eventual external circuits, unless properly protected.
注：在特定的转角条件下，一旦唤醒输入降低，VPREREG 输出可能会受到瞬态过压（箝位至 VBST）的影响。在这种情况下，集成的高压侧稳压器 FET 通过无源开关 OFF 保持关断，这可能会导致输出反弹。因此，除非经过适当保护，否则不建议使用 VPREREG 为最终外部电路供电。

All electrical characteristics are valid for the following conditions unless otherwise noted:
除非另有说明，否则所有电气特性均在以下条件下有效：

VBST .
VBST .

Table 10. VPREREG buck regulator
表 10.VPREREG 降压稳压器

Table 10. VPREREG buck regulator (continued)
表 10.VPREREG 降压稳压器（续）

This regulator provides the supply to the core. The flexible approach with the external voltage divider allows the rail to be regulated from to . It can also be configured either as a buck controller or as a linear controller, driving an external FET in both cases.
该稳压器为 内核供电。利用外部分压器的灵活方法，可将电压轨从 调节到 。它还可配置为降压控制器或线性控制器，在两种情况下均可驱动外部 FET。

Figure 5. VCORE configuration diagram (buck regulator - top, linear regulator bottom)
图 5.VCORE 配置图（顶部为降压稳压器，底部为线性稳压器）

Typically resistor has to be inserted between GCORE pin and gate of the external FET for buck configuration. For buck configuration, the source of the external FET should be connected to the SCORE pin, and the output tank capacitor should be connected to the VCORE pin. For linear configuration, the output tank capacitor should be connected with the source of the external FET and the SCORE pin, while VCORE pin should be either tied to ground or shorted to SCORE.
降压配置时，通常需要在 GCORE 引脚和外部场效应管栅极之间插入 电阻。对于降压配置，外部 FET 的源极应连接至 SCORE 引脚，输出槽电容器应连接至 VCORE 引脚。对于线性配置，输出槽电容应与外部 FET 的源极和 SCORE 引脚相连，而 VCORE 引脚应与地绑定或与 SCORE 短路。

The mode selected for VCORE operation can be read via SPI in SUPPLY_CONTROL_1 register.
可以通过 SPI 读取 SUPPLY_CONTROL_1 寄存器中为 VCORE 运行选择的模式。

Note: When linear mode is selected for VCORE, in order to guarantee the right functionality it is recommended to tie VCORE to GND or eventually realize the short between SCORE and VCORE at device pin level, minimizing the parasitic path coming from the PCB routing.
注：当 VCORE 选择线性模式时，为保证正确的功能，建议将 VCORE 与 GND 绑定，或最终在器件引脚级实现 SCORE 和 VCORE 之间的短路，从而最大限度地减少来自 PCB 布线的寄生路径。

The VCORE regulator has over and under voltage detections and the VCORE is not shut down in case of over or under voltage. It is also protected against short to ground by monitoring regulation loop for VCORE buck or over current for VCORE linear. When short to ground is detected and lasts more than the filter time of tflt_oc_vcore, the vcore is shut down and the restart is automatic in tflt_restart. No thermal protection is implemented for VCORE because the power MOS is external.
VCORE 稳压器具有过压和欠压检测功能，在电压过高或过低时不会关闭 VCORE。VCORE 降压稳压器还通过监控调节回路防止接地短路，VCORE 线性稳压器则通过监控电流过大防止接地短路。当检测到接地短路且持续时间超过 tflt_oc_vcore 的滤波时间时，将关闭 Vcore，并在 tflt_restart 中自动重启。由于功率 MOS 位于外部，因此 VCORE 没有热保护功能。

Both VPREREG and VCORE regulators could be disabled by connecting I_CORE_SH pin to ground. In this case, VPREREG pin should be connected to VBST pin.
将 I_CORE_SH 引脚接地可禁用 VPREREG 和 VCORE 稳压器。在这种情况下，VPREREG 引脚应连接至 VBST 引脚。

Moreover two pins (AI0 and Al1) are used to configure additional features of VCORE regulator. It's possible to disable only VCORE regulator leaving VPREREG enabled. It's possible to change the monitor of regulated voltage (monitor on VCORE pin or monitor on VCOREFDBK pin). All the possibilities are listed in the following table.
此外，还有两个引脚（AI0 和 Al1）用于配置 VCORE 稳压器的其他功能。可以只禁用 VCORE 稳压器，而启用 VPREREG。可以更改稳压电压的监控器（VCORE 引脚上的监控器或 VCOREFDBK 引脚上的监控器）。下表列出了所有可能性。

Table 11. Vcore configuration
表 11.核心电压配置

The state of configuration pins (AI0, Al1 and I_CORE_SH) is latched at power up when VPREREG voltage exceeds the VPREREG_UV threshold and stays latched until next POR event.
上电时，当 VPREREG 电压超过 VPREREG_UV 门限时，配置引脚（AI0、Al1 和 I_CORE_SH）的状态将被锁存，并一直锁存到下一次 POR 事件。

Microcontroller can monitor the voltage of AI0 and Al1 pins using embedded ADC converter and latched configuration is available via SPI bits.
微控制器可使用嵌入式 ADC 转换器监控 AI0 和 Al1 引脚的电压，并可通过 SPI 位进行锁存配置。

All electrical characteristics are valid for the following conditions unless otherwise noted:
除非另有说明，否则所有电气特性均在下列条件下有效：

Table 12. VCORE regulator electrical characteristics
表 12.VCORE 稳压器电气特性

Table 12. VCORE regulator electrical characteristics (continued)
表 12.VCORE 稳压器电气特性（续）

Table 12. VCORE regulator electrical characteristics (continued)
表 12.VCORE 稳压器电气特性（续）