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mipialliance

Specification for D-PHY SM SM  ^("SM "){ }^{\text {SM }}
D-PHY SM SM  ^("SM "){ }^{\text {SM }} 規範

Version 2.0 版本 2.0
23 November 2015 2015 年 11 月 23 日
MIPI Board Adopted 08 March 2016
MIPI 板採用 2016 年 3 月 8 日
Further technical changes to this document are expected as work continues in the Phy Working Group.
隨著物理工作組的持續工作,預期對本文件將進一步進行技術變更。

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Attn: Board Secretary 注意:董事會秘書

Contents 內容

Contents … iii 內容 … iii
Figures … vii 圖表 … vii
Tables … x x xx
Release History … xii
發行歷史 … xii

1 Introduction … 1
1 引言 … 1

1.1 Scope … 1
1.1 範圍 … 1

1.2 Purpose … 2
1.2 目的 … 2

2 Terminology … 3
2 術語 … 3

2.1 Use of Special Terms … 3
2.1 特殊術語的使用 … 3

2.2 Definitions … 3
2.2 定義 … 3

2.3 Abbreviations … 4
2.3 縮寫 … 4

2.4 Acronyms … 4
2.4 縮寫 … 4

3 References … 6
3 參考文獻 … 6

4 D-PHY Overview … 7
4 D-PHY 概述 … 7

4.1 Summary of PHY Functionality … 7
4.1 PHY 功能摘要 … 7

4.2 Mandatory Functionality … 7
4.2 強制功能 … 7

5 Architecture … 8
5 建築 … 8

5.1 Lane Modules … 8
5.1 車道模組 … 8

5.2 Master and Slave … 9
5.2 主從 … 9

5.3 High Frequency Clock Generation … 9
5.3 高頻時鐘生成 … 9

5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface … 9
5.4 時鐘通道、數據通道和 PHY 協議介面 … 9

5.5 Selectable Lane Options … 10
5.5 可選車道選項 … 10

5.6 Lane Module Types … 12
5.6 車道模組類型 … 12

5.6.1 Unidirectional Data Lane … 13
5.6.1 單向數據通道 … 13

5.6.2 Bi-directional Data Lanes … 13
5.6.2 雙向數據通道 … 13

5.6.3 Clock Lane. … 14
5.6.3 鐘路。… 14

5.7 Configurations … 14
5.7 配置 … 14

5.7.1 Unidirectional Configurations … 16
5.7.1 單向配置 … 16

5.7.2 Bi-Directional Half-Duplex Configurations … 17
5.7.2 雙向半雙工配置 … 17

5.7.3 Mixed Data Lane Configurations … 18
5.7.3 混合數據通道配置 … 18

6 Global Operation … 19
6 全球運營 … 19

6.1 Transmission Data Structure … 19
6.1 傳輸數據結構 … 19

6.1.1 Data Units … 19
6.1.1 數據單位 … 19

6.1.2 Bit order, Serialization, and De-Serialization … 19
6.1.2 位元順序、序列化和反序列化 … 19

6.1.3 Encoding and Decoding … 19
6.1.3 編碼與解碼 … 19

6.1.4 Data Buffering … 19
6.1.4 數據緩衝 … 19

6.2 Lane States and Line Levels … 19
6.2 車道狀態和線級 … 19

6.3 Operating Modes: Control, High-Speed, and Escape … 20
6.3 操作模式:控制、高速和逃逸 … 20

6.4 High-Speed Data Transmission … 21
6.4 高速數據傳輸 … 21

6.4.1 Burst Payload Data … 21
6.4.1 突發有效載荷數據 … 21

6.4.2 Start-of-Transmission … 21
6.4.2 傳輸開始 … 21

6.4.3 End-of-Transmission … 22
6.4.3 傳輸結束 … 22

6.4.4 HS Data Transmission Burst. … 22
6.4.4 HS 數據傳輸突發。… 22

6.5 Bi-directional Data Lane Turnaround … 24
6.5 雙向數據通道轉換 … 24

6.6 Escape Mode … 27
6.6 逃脫模式 … 27

6.6.1 Remote Triggers … 28
6.6.1 遠程觸發器 … 28

6.6.2 Low-Power Data Transmission … 28
6.6.2 低功耗數據傳輸 … 28

6.6.3 Ultra-Low Power State … 29
6.6.3 超低功耗狀態 … 29

6.6.4 Escape Mode State Machine … 29
6.6.4 逃逸模式狀態機 … 29

6.7 High-Speed Clock Transmission … 31
6.7 高速時鐘傳輸 … 31

6.8 Clock Lane Ultra-Low Power State … 36
6.8 時鐘巷超低功耗狀態 … 36

6.9 Global Operation Timing Parameters … 37
6.9 全球操作時間參數 … 37

6.10 System Power States … 41
6.10 系統電源狀態 … 41

6.11 Initialization … 41
6.11 初始化 … 41

6.12 Calibration … 41
6.12 校準 … 41

6.13 Global Operation Flow Diagram … 45
6.13 全球操作流程圖 … 45

6.14 Data Rate Dependent Parameters (informative) … 47
6.14 數據速率依賴參數(資訊性)… 47

6.14.1 Parameters Containing Only UI Values. … 48
6.14.1 僅包含 UI 值的參數。… 48

6.14.2 Parameters Containing Time and UI values … 48
6.14.2 包含時間和 UI 值的參數 … 48

6.14.3 Parameters Containing Only Time Values … 48
6.14.3 僅包含時間值的參數 … 48

6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent. … 49
6.14.4 僅包含不依賴於數據速率的時間值的參數。… 49

6.15 Interoperability … 49
6.15 互操作性 … 49

7 Fault Detection … 50
7 故障檢測 … 50

7.1 Contention Detection … 50
7.1 競爭檢測 … 50

7.2 Sequence Error Detection … 50
7.2 序列錯誤檢測 … 50

7.2.1 SoT Error … 51
7.2.1 SoT 錯誤 … 51

7.2.2 SoT Sync Error … 51
7.2.2 SoT 同步錯誤 … 51

7.2.3 EoT Sync Error … 51
7.2.3 EoT 同步錯誤 … 51

7.2.4 Escape Mode Entry Command Error. … 51
7.2.4 逃脫模式進入命令錯誤。… 51

7.2.5 LP Transmission Sync Error … 51
7.2.5 LP 傳輸同步錯誤 … 51

7.2.6 False Control Error … 51
7.2.6 錯誤控制錯誤 … 51

7.3 Protocol Watchdog Timers (informative) … 51
7.3 協議看門狗計時器(資訊性)… 51

7.3.1 HS RX Timeout … 51
7.3.1 HS RX 超時 … 51

7.3.2 HS TX Timeout … 51
7.3.2 HS TX 超時 … 51

7.3.3 Escape Mode Timeout … 51
7.3.3 逃脫模式超時 … 51

7.3.4 Escape Mode Silence Timeout … 51
7.3.4 逃脫模式靜音超時 … 51

7.3.5 Turnaround Errors … 52
7.3.5 轉換錯誤 … 52

8 Interconnect and Lane Configuration … 53
8 互連和通道配置 … 53

8.1 Lane Configuration … 53
8.1 車道配置 … 53

8.2 Boundary Conditions … 53
8.2 邊界條件 … 53

8.3 Definitions … 53
8.3 定義 … 53

8.4 S-parameter Specifications … 54
8.4 S-參數規格 … 54

8.5 Characterization Conditions … 54
8.5 特徵化條件 … 54

8.6 Interconnect Specifications … 54
8.6 互連規範 … 54

8.6.1 Differential Characteristics … 55
8.6.1 差異特徵 … 55

8.6.2 Common-mode Characteristics … 57
8.6.2 共模特性 … 57

8.6.3 Intra-Lane Cross-Coupling … 57
8.6.3 車道內交叉耦合 … 57

8.6.4 Mode-Conversion Limits … 57
8.6.4 模式轉換限制 … 57

8.6.5 Inter-Lane Cross-Coupling … 57
8.6.5 車道間交叉耦合 … 57

8.6.6 Inter-Lane Static Skew … 58
8.6.6 車道間靜態偏差 … 58

8.7 Driver and Receiver Characteristics … 59
8.7 驅動器和接收器特性 … 59

8.7.1 Differential Characteristics … 59
8.7.1 差異特徵 … 59

8.7.2 Common-Mode Characteristics. … 60
8.7.2 共模特性。… 60

8.7.3 Mode-Conversion Limits … 61
8.7.3 模式轉換限制 … 61

9 Electrical Characteristics … 62
9 電氣特性 … 62

9.1 Driver Characteristics … 63
9.1 駕駛員特徵 … 63

9.1.1 High-Speed Transmitter. … 63
9.1.1 高速發射器。… 63

9.1.2 Low-Power Transmitter … 69
9.1.2 低功耗發射器 … 69

9.2 Receiver Characteristics … 72
9.2 接收器特性 … 72

9.2.1 High-Speed Receiver … 72
9.2.1 高速接收器 … 72

9.2.2 Low-Power Receiver … 74
9.2.2 低功耗接收器 … 74

9.3 Line Contention Detection … 75
9.3 線路爭用檢測 … 75

9.4 Input Characteristics … 76
9.4 輸入特性 … 76

10 High-Speed Data-Clock Timing … 78
10 高速數據時鐘定時 … 78

10.1 High-Speed Clock Timing … 78
10.1 高速時鐘定時 … 78

10.2 Forward High-Speed Data Transmission Timing … 79
10.2 前向高速數據傳輸時序 … 79

10.2.1 Data-Clock Timing Specifications. … 80
10.2.1 數據時鐘時序規範。… 80

10.2.2 Normative Spread Spectrum Clocking (SSC) … 81
10.2.2 規範性擴頻時鐘 (SSC) … 81

10.2.3 Transmitter Eye Diagram Specification … 82
10.2.3 發射器眼圖規範 … 82

10.2.4 Receiver Eye Diagram Specification. … 84
10.2.4 接收器眼圖規範。… 84

10.3 Reverse High-Speed Data Transmission Timing … 85
10.3 反向高速數據傳輸時序 … 85

10.4 Operating Modes: Data rate and Channel Support Guidance … 86
10.4 操作模式:數據速率和通道支持指導 … 86

11 Regulatory Requirements. … 88
11 監管要求。… 88

12 Built-In HS Test Mode (Informative) … 89
12 內建 HS 測試模式(資訊性)… 89

12.1 Introduction. … 89
12.1 介紹。… 89

12.2 Entering the HS Test Mode … 90
12.2 進入 HS 測試模式… 90

12.3 HS Test Mode … 90
12.3 HS 測試模式 … 90

12.4 Special Case: Multi-Lane Testing. … 92
12.4 特殊情況:多車道測試。… 92

12.5 Exiting from HS Test Mode … 92
12.5 正在退出 HS 測試模式 … 92

Annex A Logical PHY-Protocol Interface Description (informative) … 93
附錄 A 邏輯 PHY 協議介面描述(資訊性)… 93

A. 1 Signal Description … 93
A. 1 信號描述 … 93

A. 2 High-Speed Transmit from the Master Side … 103
A. 2 高速從主端傳輸 … 103

A. 3 High-Speed Receive at the Slave Side … 104
A. 3 高速接收在從屬端 … 104

A. 4 High-Speed Transmit from the Slave Side … 104
A. 4 從從屬端發送的高速傳輸 … 104

A. 5 High-Speed Receive at the Master Side … 105
A. 5 高速接收在主端 … 105

A. 6 Low-Power Data Transmission. … 105
A. 6 低功耗數據傳輸。… 105

A. 7 Low-Power Data Reception. … 106
A. 7 低功耗數據接收。… 106

A. 8 Turn-around … 106
A. 8 轉彎 … 106

A. 9 Calibration … 107
A. 9 校準 … 107

A. 10 Optical Link Support … 109
A. 10 光學連接支援 … 109

A.10.1 System Setup … 109
A.10.1 系統設置 … 109

A.10.2 Serializer and De-Serializer Block Diagrams. … 110
A.10.2 序列化器和反序列化器區塊圖。… 110

A.10.3 Timing Constraints … 111
A.10.3 時間限制 … 111

A.10.4 System Constraints … 112
A.10.4 系統限制 … 112

Annex B Interconnect Design Guidelines (informative) … 113
附錄 B 互連設計指南(資訊性)… 113

B. 1 Practical Distances … 113
B. 1 實用距離 … 113

B. 2 RF Frequency Bands: Interference … 113
B. 2 RF 頻率頻段:干擾 … 113

B. 3 Transmission Line Design … 113
B. 3 傳輸線設計 … 113

B. 4 Reference Layer … 113
B. 4 參考層 … 113

B. 5 Printed-Circuit Board … 114
B. 5 印刷電路板 … 114

B. 6 Flex-foils … 114
B. 6 彈性薄膜 … 114

B. 7 Series Resistance … 114
B. 7 系列電阻 … 114

B. 8 Connectors … 114
B. 8 連接器 … 114

Annex C 8b9b Line Coding for D-PHY (normative) … 115
附錄 C 8b9b D-PHY 的行編碼(規範)… 115

C. 1 Line Coding Features … 116
C. 1 行編碼特徵 … 116

C.1.1 Enabled Features for the Protocol … 116
C.1.1 協議的啟用功能 … 116

C.1.2 Enabled Features for the PHY … 116
C.1.2 已啟用的 PHY 功能 … 116

C. 2 Coding Scheme … 116
C. 2 編碼方案 … 116

C.2.1 8b9b Coding Properties … 116
C.2.1 8b9b 編碼屬性 … 116

C.2.2 Data Codes: Basic Code Set … 116
C.2.2 數據代碼:基本代碼集 … 116

C.2.3 Comma Codes: Unique Exception Codes … 117
C.2.3 逗號代碼:獨特例外代碼 … 117

C.2.4 Control Codes: Regular Exception Codes … 118
C.2.4 控制碼:常規例外碼 … 118

C.2.5 Complete Coding Scheme … 118
C.2.5 完整編碼方案 … 118

C. 3 Operation with the D-PHY … 118
C. 3 與 D-PHY 的操作 … 118

C.3.1 Payload: Data and Control … 118
C.3.1 負載:數據和控制 … 118

C.3.2 Details for HS Transmission … 119
C.3.2 HS 傳輸的詳細信息 … 119

C.3.3 Details for LP Transmission … 119
C.3.3 LP 傳輸的詳細信息 … 119

C. 4 Error Signaling … 120
C. 4 錯誤信號 … 120

C. 5 Extended PPI … 120
C. 5 擴展 PPI … 120

C. 6 Complete Code Set … 121
C. 6 完整代碼集 … 121

Figures 數字

Figure 1 Universal Lane Module Functions … 8
圖 1 通用車道模組功能 … 8

Figure 2 Two Data Lane PHY Configuration … 10
圖 2 兩個數據通道 PHY 配置 … 10

Figure 3 Option Selection Flow Graph … 11
圖 3 選項選擇流程圖 … 11

Figure 4 Universal Lane Module Architecture … 12
圖 4 通用通道模組架構 … 12

Figure 5 Lane Symbol Macros and Symbols Legend. … 14
圖 5 車道符號宏和符號圖例。… 14

Figure 6 All Possible Data Lane Types and a Basic Unidirectional Clock Lane. … 15
圖 6 所有可能的數據通道類型和一個基本的單向時鐘通道。… 15

Figure 7 Unidirectional Single Data Lane Configuration … 16
圖 7 單向單數據通道配置 … 16

Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT … 16
圖 8 單向多數據通道配置,無 LPDT … 16

Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT … 17
圖 9 使用兩個獨立單向 PHY 的兩個方向,無需 LPDT … 17

Figure 10 Bidirectional Single Data Lane Configuration … 17
圖 10 雙向單數據通道配置 … 17

Figure 11 Bi-directional Multiple Data Lane Configuration … 18
圖 11 雙向多數據通道配置 … 18

Figure 12 Mixed Type Multiple Data Lane Configuration … 18
圖 12 混合型多數據通道配置 … 18

Figure 13 Line Levels … 20
圖 13 線級 … 20

Figure 14 High-Speed Data Transmission in Bursts … 22
圖 14 高速數據突發傳輸 … 22

Figure 15 TX and RX State Machines for High-Speed Data Transmission … 23
圖 15 高速數據傳輸的 TX 和 RX 狀態機 … 23

Figure 16 Turnaround Procedure. … 25
圖 16 轉向程序。… 25

Figure 17 Turnaround State Machine … 26
圖 17 轉換狀態機 … 26

Figure 18 Trigger-Reset Command in Escape Mode … 27
圖 18 逃脫模式下的觸發重置命令 … 27

Figure 19 Two Data Byte Low-Power Data Transmission Example … 29
圖 19 兩個數據字低功耗數據傳輸示例 … 29

Figure 20 Escape Mode State Machine … 30
圖 20 逃逸模式狀態機 … 30

Figure 21 Switching the Clock Lane between Clock Transmission and Low-Power Mode … 33
圖 21 在時鐘傳輸和低功耗模式之間切換時鐘通道 … 33

Figure 22 High-Speed Clock Transmission State Machine … 35
圖 22 高速時鐘傳輸狀態機 … 35

Figure 23 Clock Lane Ultra-Low Power State State Machine … 36
圖 23 時鐘巷超低功耗狀態機 … 36

Figure 24 High-Speed Data Transmission in Skew-Calibration … 42
圖 24 高速數據傳輸中的偏差校準 … 42

Figure 25 Normal Mode vs Skew Calibration. … 42
圖 25 正常模式與偏斜校準。… 42

Figure 26 Normal Mode vs Skew Calibration (Zoom-In) … 43
圖 26 正常模式與偏斜校準(放大)… 43

Figure 27 Data Lane Module State Diagram. … 46
圖 27 數據通道模塊狀態圖。… 46

Figure 28 Clock Lane Module State Diagram. … 47
圖 28 時鐘通道模組狀態圖。… 47

Figure 29 Point-to-point Interconnect … 53
圖 29 點對點互連 … 53

Figure 30 Set-up for S-parameter Characterization of RX, TX and TLIS … 54
圖 30 RX、TX 和 TLIS 的 S 參數特性測試設置… 54

Figure 31 Template for Differential Insertion Losses, Data Rates 80 Mbps 80 Mbps >= 80Mbps\geq 80 \mathrm{Mbps} and 1.5 Gbps 1.5 Gbps <= 1.5Gbps\leq 1.5 \mathrm{Gbps} … 55
圖 31 差分插入損耗、數據速率 80 Mbps 80 Mbps >= 80Mbps\geq 80 \mathrm{Mbps} 1.5 Gbps 1.5 Gbps <= 1.5Gbps\leq 1.5 \mathrm{Gbps} 的模板 … 55

Figure 32 Template for Differential Insertion Losses, Data Rates > 1.5 Gbps and 4.5 Gbps 4.5 Gbps <= 4.5Gbps\leq 4.5 \mathrm{Gbps} … 56
圖 32 差分插入損耗模板,數據速率 > 1.5 Gbps 和 4.5 Gbps 4.5 Gbps <= 4.5Gbps\leq 4.5 \mathrm{Gbps} … 56

Figure 33 Template for Differential Reflection at Both Ports … 57
圖 33 雙端差反射模板 … 57

Figure 34 Inter-Lane Common-mode Cross-Coupling Template … 58
圖 34 車道間共模交叉耦合模板 … 58

Figure 35 Inter-Lane Differential Cross-Coupling Template … 58
圖 35 車道間差分交叉耦合模板 … 58

Figure 36 Differential Reflection Template for Lane Module Receivers … 59
圖 36 差分反射模板用於通道模組接收器 … 59

Figure 37 Differential Reflection Template for Lane Module Transmitters … 60
圖 37 差異反射模板用於通道模組發射器 … 60

Figure 38 Template for RX Common-Mode Return Loss … 61
圖 38 RX 共模回損模板… 61

Figure 39 Electrical Functions of a Fully Featured D-PHY Transceiver … 62
圖 39 完整功能 D-PHY 收發器的電氣功能 … 62

Figure 40 D-PHY Signaling Levels … 63
圖 40 D-PHY 信號水平 … 63

Figure 41 Example HS Transmitter … 64
圖 41 示例 HS 發射器 … 64

Figure 42 Ideal Single-Ended and Resulting Differential HS Signals … 65
圖 42 理想的單端和結果差分高頻信號 … 65

Figure 43 Possible Δ V CMTx Δ V CMTx DeltaV_(CMTx)\Delta \mathrm{V}_{\mathrm{CMTx}} and Δ V OD Δ V OD DeltaV_(OD)\Delta \mathrm{V}_{\mathrm{OD}} Distortions of the Single-ended HS Signals … 66
圖 43 單端 HS 信號的可能 Δ V CMTx Δ V CMTx DeltaV_(CMTx)\Delta \mathrm{V}_{\mathrm{CMTx}} Δ V OD Δ V OD DeltaV_(OD)\Delta \mathrm{V}_{\mathrm{OD}} 失真… 66

Figure 44 Example Circuit for VCMTX and VOD Measurements … 66
圖 44 VCMTX 和 VOD 測量的示例電路 … 66

Figure 45 Common Mode and Differential Swing in Half Swing Mode versus Default … 67
圖 45 半擺模式下的共模和差模擺幅與默認模式的比較… 67

Figure 46 De-emphasis Example … 68
圖 46 降低重點示例 … 68

Figure 47 Example LP Transmitter … 69
圖 47 範例 LP 發射器 … 69

Figure 48 V-I Characteristic for LP Transmitter Driving Logic High … 70
圖 48 LP 發射器驅動邏輯高的 V-I 特性… 70

Figure 49 V-I Characteristic for LP Transmitter Driving Logic Low … 70
圖 49 LP 發射器驅動邏輯低的 V-I 特性… 70

Figure 50 LP Transmitter V-I Characteristic Measurement Setup … 70
圖 50 LP 發射器 V-I 特性測量設置 … 70

Figure 51 HS Receiver Implementation Example … 73
圖 51 HS 接收器實現範例 … 73

Figure 52 Input Glitch Rejection of Low-Power Receivers … 75
圖 52 低功耗接收器的輸入故障拒絕 … 75

Figure 53 Signaling and Contention Voltage Levels … 76
圖 53 信號和競爭電壓水平 … 76

Figure 54 Pin Leakage Measurement Example Circuit … 77
圖 54 引腳漏電測量示例電路 … 77

Figure 55 Conceptual D-PHY Data and Clock Timing Compliance Measurement Planes … 78
圖 55 概念性 D-PHY 數據和時鐘時序合規性測量平面… 78

Figure 56 DDR Clock Definition … 79
圖 56 DDR 時鐘定義 … 79

Figure 57 Data to Clock Timing Definitions … 80
圖 57 數據到時鐘定義 … 80

Figure 58 TX Eye Diagram Specification … 83
圖 58 TX 眼圖規範 … 83

Figure 59 Transmitter Eye Diagram Validation Setup … 83
圖 59 發射器眼圖驗證設置 … 83

Figure 60 Receiver Eye Diagram Specification … 84
圖 60 接收器眼圖規範 … 84

Figure 61 Receiver Eye Diagram Validation Setup … 85
圖 61 接收器眼圖驗證設置 … 85

Figure 62 Conceptual View of HS Data Transmission in Reverse Direction … 85
圖 62 HS 數據反向傳輸的概念視圖 … 85

Figure 63 Reverse High-Speed Data Transmission Timing at Slave Side … 86
圖 63 從屬端的反向高速數據傳輸時序 … 86

Figure 64 Testing with Pattern Checkers and Generators … 89
圖 64 使用模式檢查器和生成器進行測試 … 89

Figure 65 Alternative Testing with Loopback Mode … 89
圖 65 迴路模式的替代測試 … 89

Figure 66 Example High-Speed Transmission from the Master Side (One-Byte Bus Width) … 104
圖 66 來自主端的高速度傳輸示例(單字節總線寬度)… 104

Figure 67 Example High-Speed Receive at the Slave Side (One-Byte Bus Width) … 104
圖 67 範例 高速接收在從屬端(單字節總線寬度)… 104

Figure 68 Example High-Speed Transmit from the Slave Side (One-Byte Bus Width). … 105
圖 68 例子 高速從從屬端傳輸(單字節總線寬度)。 … 105

Figure 69 Example High-Speed Receive at the Master Side (One-Byte Bus Width). … 105
圖 69 範例 高速接收在主端(單字節總線寬度)。 … 105

Figure 70 Low-Power Data Transmission … 106
圖 70 低功耗數據傳輸 … 106

Figure 71 Example Low-Power Data Reception … 106
圖 71 低功耗數據接收示例 … 106

Figure 72 Example Turn-around Actions Transmit-to-Receive and Back to Transmit … 107
圖 72 例子 轉換動作 從發送到接收再回到發送 … 107

Figure 73 Periodic Skew Calibration - PPI Signal in Normal Mode. … 108
圖 73 週期性偏斜校準 - 正常模式下的 PPI 信號。… 108

Figure 74 Periodic Skew Calibration - PPI Signal during Skew Calibration … 109
圖 74 週期性偏斜校準 - 偏斜校準期間的 PPI 信號 … 109

Figure 75 Typical System Setup with Optical Interconnect … 109
圖 75 典型系統設置與光互連 … 109

Figure 76 Block Diagram of Typical Serializer for Optical Link. … 110
圖 76 光學連接典型序列器的框圖。… 110

Figure 77 Block Diagram of Typical De-Serializer for Optical Link. … 110
圖 77 光纖連接典型反序列化器的方塊圖。… 110

Figure 78 Delay Between Start of HS Clock and HS Data Transmission Without Optical Link. 111
圖 78 HS 時鐘啟動與 HS 數據傳輸之間的延遲(無光學連接)。111

Figure 79 Delay Between Start of HS Clock and HS Data Transmission With Optical Link. … 111
圖 79 HS 時鐘啟動與 HS 數據傳輸之間的延遲,使用光纖連接。… 111

Figure 80 Line Coding Layer Example … 115
圖 80 行編碼層範例 … 115

Tables 表格

Table 1 Lane Type Descriptors … 13
表 1 車道類型描述 … 13

Table 2 Lane State Descriptions … 20
表 2 車道狀態描述 … 20

Table 3 Start-of-Transmission Sequence … 21
表 3 傳輸開始序列 … 21

Table 4 End-of-Transmission Sequence … 22
表 4 傳輸結束序列 … 22

Table 5 High-Speed Data Transmission State Machine Description … 23
表 5 高速數據傳輸狀態機描述 … 23

Table 6 Link Turnaround Sequence … 24
表 6 連結周轉序列 … 24

Table 7 Turnaround State Machine Description … 26
表 7 轉換狀態機描述 … 26

Table 8 Escape Entry Codes … 28
表 8 逃生進入代碼 … 28

Table 9 Escape Mode State Machine Description … 30
表 9 逃脫模式狀態機描述 … 30

Table 10 Procedure to Switch Clock Lane to Low-Power Mode … 34
表 10 切換時鐘通道至低功耗模式的程序 … 34

Table 11 Procedure to Initiate High-Speed Clock Transmission … 34
表 11 高速時鐘傳輸啟動程序 … 34

Table 12 Description of High-Speed Clock Transmission State Machine … 35
表 12 高速時鐘傳輸狀態機的描述 … 35

Table 13 Clock Lane Ultra-Low Power State State Machine Description … 36
表 13 時鐘巷超低功耗狀態狀態機描述 … 36

Table 14 Global Operation Timing Parameters … 38
表 14 全球操作時間參數 … 38

Table 15 Initialization States … 41
表 15 初始化狀態 … 41

Table 16 Start-of-Skew Calibration Sequence … 43
表 16 偏斜校準序列開始 … 43

Table 17 End-of-Skew Calibration Sequence … 44
表 17 偏斜校準序列 … 44

Table 18 Skew-Calibration Timing Parameters … 45
表 18 偏斜校準時間參數 … 45

Table 19 D-PHY Version Integration and Downward Compatibility … 49
表 19 D-PHY 版本整合與向下相容性 … 49

Table 20 HS Transmitter DC Specifications … 68
表 20 HS 發射器直流規格 … 68

Table 21 HS Transmitter AC Specifications … 69
表 21 HS 發射器交流規格 … 69

Table 22 LP Transmitter DC Specifications … 71
表 22 LP 發射器直流規格 … 71

Table 23 LP Transmitter AC Specifications … 71
表 23 LP 發射器交流規格 … 71

Table 24 HS Receiver DC Specifications … 73
表 24 HS 接收器直流規格 … 73

Table 25 HS Receiver AC Specifications … 74
表 25 HS 接收器交流規格 … 74

Table 26 LP Receiver DC specifications … 75
表 26 LP 接收器直流規格 … 75

Table 27 LP Receiver AC Specifications … 75
表 27 LP 接收器交流規格 … 75

Table 28 Contention Detector (LP-CD) DC Specifications … 76
表 28 競爭檢測器 (LP-CD) 直流規格 … 76

Table 29 Pin Characteristic Specifications … 77
表 29 引腳特性規格 … 77

Table 30 Clock Signal Specification … 79
表 30 時鐘信號規範 … 79

Table 31 Data-Clock Timing Specifications for 0.08 Gbps 0.08 Gbps >= 0.08Gbps\geq 0.08 \mathrm{Gbps} and 1 Gbps 1 Gbps <= 1Gbps\leq 1 \mathrm{Gbps} … 80
表 31 數據時鐘時序規範 0.08 Gbps 0.08 Gbps >= 0.08Gbps\geq 0.08 \mathrm{Gbps} 1 Gbps 1 Gbps <= 1Gbps\leq 1 \mathrm{Gbps} … 80

Table 32 Data-Clock Timing Specifications for > 1 > 1 > 1>1 Gbps and 1.5 Gbps 1.5 Gbps <= 1.5Gbps\leq 1.5 \mathrm{Gbps} … 81
表 32 > 1 > 1 > 1>1 Gbps 和 1.5 Gbps 1.5 Gbps <= 1.5Gbps\leq 1.5 \mathrm{Gbps} 的數據時鐘時序規範 … 81

Table 33 Data-Clock Timing Specifications for > 1.5 Gbps > 1.5 Gbps > 1.5Gbps>1.5 \mathrm{Gbps} and 4.5 Gbps 4.5 Gbps <= 4.5Gbps\leq 4.5 \mathrm{Gbps} … 81
表 33 數據時鐘時序規範 > 1.5 Gbps > 1.5 Gbps > 1.5Gbps>1.5 \mathrm{Gbps} 4.5 Gbps 4.5 Gbps <= 4.5Gbps\leq 4.5 \mathrm{Gbps} … 81

Table 34 Spread Spectrum Clocking Requirements … 82
表 34 擴頻時鐘要求 … 82

Table 35 Transmitter Eye Diagram Specification. … 83
表 35 發射器眼圖規範。… 83

Table 36 Receiver Eye Diagram Specification. … 84
表 36 接收器眼圖規範。… 84

Table 37 Operating Modes and Guidance … 86
表 37 操作模式和指導 … 86

Table 38 PPI Signals … 94
表 38 PPI 信號 … 94

Table 39 Tx HS PPI Signals, Impact of Data Path Width … 103
表 39 Tx HS PPI 信號,數據通路寬度的影響……103

Table 40 Rx HS PPI Signals, Impact of Data Path Width … 103
表 40 Rx HS PPI 信號,數據通路寬度的影響 … 103

Table 41 Timing with Optical Link … 112
表 41 光學連接的時序 … 112

Table 42 Encoding Table for 8b9b Line Coding of Data Words … 117
表 42 8b9b 行編碼數據字的編碼表 … 117

Table 43 Comma Codes. … 118
表 43 逗號代碼。… 118

Table 44 Regular Exception Code Structure … 118
表 44 正常例外代碼結構 … 118

Table 45 Additional Signals for (Functional) PPI … 120
表 45 附加信號 (功能) PPI … 120

Table 46 Code Set (8b9b Line Coding). … 121
表 46 代碼集 (8b9b 行編碼)。… 121

Release History 發行歷史

Date 日期 Version 版本 Description 描述
2016 03 08 2016 03 08 2016-03-082016-03-08 V2.0 Initial Board adopted release.
初步董事會通過的發布。
Date Version Description 2016-03-08 V2.0 Initial Board adopted release.| Date | Version | Description | | :---: | :--- | :--- | | $2016-03-08$ | V2.0 | Initial Board adopted release. |

1 Introduction 1 介紹

This specification provides a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized with very low power consumption.
此規範提供了一種靈活、低成本的高速串行介面解決方案,用於移動設備內部組件之間的通信互連。傳統上,這些介面是低位速率的 CMOS 平行匯流排,因為電磁干擾的原因,邊緣變化緩慢。D-PHY 解決方案使介面帶寬得以顯著擴展,以支持更先進的應用。D-PHY 解決方案可以實現非常低的功耗。

1.1 Scope 1.1 範圍

The scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to be applied by MIPI Alliance application or protocol level specifications. This includes the physical interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken together are known as D-PHY.
本文件的範圍是指定由 MIPI 聯盟應用或協議層級規範所應用的高速源同步介面的最低層。這包括物理介面、電氣介面、低級時序和 PHY 層協議。這些功能區域合在一起被稱為 D-PHY。
The D-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Any other use of the D-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors.
D-PHY 規範必須始終與引用此規範的更高層 MIPI 規範結合使用。除非事先獲得 MIPI 董事會的批准,否則嚴禁以其他方式使用 D-PHY 規範。

The following topics are outside the scope of this document:
以下主題不在本文件的範疇內:
  • Explicit specification of signals of the clock generator unit. Of course, the D-PHY specification does implicitly require some minimum performance from the clock signals. Intentionally, only the behavior on the interface pins is constrained. Therefore, the clock generation unit is excluded from this specification, and will be a separate functional unit that provides the required clock signals to the D-PHY in order to meet the specification. This allows all kinds of implementation trade-offs as long as these do not violate this specification. More information can be found in Section 5.
    時鐘產生單元的信號明確規範。當然,D-PHY 規範隱含地要求時鐘信號具備某些最低性能。故意地,僅對介面引腳的行為進行約束。因此,時鐘產生單元不在此規範之內,將作為一個獨立的功能單元,為 D-PHY 提供所需的時鐘信號,以滿足規範。這允許各種實現上的權衡,只要這些不違反此規範。更多信息可以在第 5 節找到。
  • Test modes, patterns, and configurations. Obviously testability is very important, but because the items to test are mostly application specific or implementation related, the specification of tests is deferred to either the higher layer specifications or the product specification. Furthermore MIPI D-PHY compliance testing is not included in this specification.
    測試模式、模式和配置。顯然,測試性非常重要,但因為要測試的項目大多是應用特定或實現相關的,因此測試的規範被推遲到更高層的規範或產品規範。此外,MIPI D-PHY 合規性測試不包括在此規範中。
  • Procedure to resolve contention situations. The D-PHY contains several mechanisms to detect Link contention. However, certain contention situations can only be detected at higher levels and are therefore not included in this specification.
    解決爭用情況的程序。D-PHY 包含幾種檢測鏈路爭用的機制。然而,某些爭用情況只能在更高的層次上檢測到,因此未包含在本規範中。
  • Ensure proper operation of a connection between different Lane Module types. There are several different Lane Module types to optimally support the different functional requirements of several applications. This means that next to some base-functionality there are optional features which can be included or excluded. This specification only ensures correct operation for a connection between matched Lane Modules types, which means: Modules that support the same features and have complementary functionality. In case the two sides of the Lane are not the same type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the Lane Module(s) that the provided additional functionality does not corrupt operation. This can be easiest accomplished if the additional functionality can be disabled by other means independent of the MIPI D-PHY interface, such that the Lane Modules behave as if they were the same type.
    確保不同通道模組類型之間的連接正常運作。有幾種不同的通道模組類型,以最佳支持多個應用的不同功能需求。這意味著除了某些基本功能外,還有可選的功能可以包含或排除。本規範僅確保匹配的通道模組類型之間的連接正常運作,這意味著:支持相同功能並具有互補功能的模組。如果通道的兩側不是相同類型,並且這些模組應該正常運作,則應由通道模組的製造商確保所提供的附加功能不會損害運作。如果附加功能可以通過其他獨立於 MIPI D-PHY 介面的方式禁用,則可以最輕鬆地實現這一點,使通道模組的行為如同它們是相同類型。
  • ESD protection level of the IO. The required level will depend on a particular application environment and product type.
    IO 的 ESD 保護級別。所需的級別將取決於特定的應用環境和產品類型。
  • Exact Bit-Error-Rate (BER) value. The actual value of the achieved BER depends on the total system integration and the hostility of the environment. Therefore, it is impossible to specify a BER for individual parts of the Link. This specification allows for implementations with a BER < 10 12 < 10 12 < 10^(-12)<10^{-12}.
    精確的位元錯誤率(BER)值。實際達成的 BER 值取決於整體系統整合和環境的惡劣程度。因此,無法為鏈路的各個部分指定 BER。此規範允許實現 BER < 10 12 < 10 12 < 10^(-12)<10^{-12}
  • Specification of the PHY-Protocol Interface. The D-PHY specification includes a PHY-Protocol Interface (PPI) annex that provides one possible solution for this interface. This annex is limited to the essential signals for normal operation in order to clarify the kind of signals needed at this
    PHY 協議介面的規範。D-PHY 規範包括一個 PHY 協議介面(PPI)附錄,提供了這個介面的一種可能解決方案。這個附錄僅限於正常操作所需的基本信號,以便澄清在此所需的信號類型。

    interface. For power reasons this interface will be internal for most applications. Practical implementations may be different without being inconsistent with the D-PHY specification.
    介面。出於功率原因,這個介面對於大多數應用將是內部的。實際實現可能會有所不同,但不會與 D-PHY 規範不一致。
  • Implementations. This specification is intended to restrict the implementation as little as possible. Various sections of this specification use block diagrams or example circuits to illustrate the concept and are not in any way claimed to be the preferred or required implementation. Only the behavior on the D-PHY interface pins is normative.
    實現。此規範旨在盡可能少地限制實現。此規範的各個部分使用方塊圖或示例電路來說明概念,並不以任何方式聲稱是首選或必需的實現。只有 D-PHY 介面引腳上的行為是規範性的。
D-PHY Specification evolution is primarily driven by the need to achieve higher data rates and better efficiency, while at the same time respecting backward compatibility. In this process the previous version of the specification is taken and modifications are added, without compromising backward compatibility. Each new version of the specification that is derived both preserves all the specification components of the previous version, and adds the new changes. Due to technology evolution, some parameters are changed to optimize for newer technologies.
D-PHY 規範的演變主要是由於需要實現更高的數據傳輸速率和更好的效率,同時尊重向後兼容性。在這個過程中,會採用先前版本的規範並添加修改,而不會妥協向後兼容性。每個衍生的新版本規範都保留了前一版本的所有規範組件,並添加了新的變更。由於技術的演變,一些參數被更改以優化新技術。

It is recommended to always follow the latest version of the D-PHY Specification, irrespective of the targeted data rate. The product data sheet should mention both the targeted D-PHY Specification version and data rates. This will enable the system integrator to make proper decisions to achieve interoperability goals.
建議始終遵循最新版本的 D-PHY 規範,無論目標數據速率為何。產品數據表應提及目標的 D-PHY 規範版本和數據速率。這將使系統集成商能夠做出適當的決策,以實現互操作性目標。
Regulatory compliance methods are not within the scope of this document. It is the responsibility of product manufacturers to ensure that their designs comply with all applicable regulatory requirements.
本文件不包括合規性方法。產品製造商有責任確保其設計符合所有適用的法規要求。

1.2 Purpose 1.2 目的

The D-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface specifications for mobile device such as, but not limited to, camera, display and unified protocol interfaces.
D-PHY 規範被製造商用來設計符合 MIPI 聯盟介面規範的移動設備產品,例如但不限於相機、顯示器和統一協議介面。
Implementing this specification reduces the time-to-market and design cost of mobile devices by standardizing the interface between products from different manufacturers. In addition, richer feature sets requiring high bit rates can be realized by implementing this specification. Finally, adding new features to mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications.
實施此規範可通過標準化不同製造商產品之間的介面,減少行動裝置的上市時間和設計成本。此外,通過實施此規範,可以實現需要高比特率的更豐富功能集。最後,由於 MIPI 聯盟規範的可擴展性,為行動裝置添加新功能變得更加簡單。

2 Terminology 2 術語

2.1 Use of Special Terms
2.1 特殊術語的使用

The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:
MIPI 聯盟已採納 IEEE 標準風格手冊第 13.1 節,該節規定在文件開發中使用“應”、“應該”、“可以”和“能夠”這些詞語,如下所示:
The word shall is used to indicate mandatory requirements strictly to be followed in order to conform to the Specification and from which no deviation is permitted (shall equals is required to).
“shall”這個詞用來表示必須嚴格遵循的強制性要求,以符合規範,並且不允許任何偏離(shall 等於必須)。

The use of the word must is deprecated and shall not be used when stating mandatory requirements; must is used only to describe unavoidable situations.
使用“必須”一詞已被棄用,並且在陳述強制性要求時不得使用;“必須”僅用於描述不可避免的情況。
The use of the word will is deprecated and shall not be used when stating mandatory requirements; will is only used in statements of fact.
使用“will”一詞已被棄用,並且在陳述強制性要求時不得使用;“will”僅用於事實陳述中。
The word should is used to indicate that among several possibilities one is recommended as particularly suitable, without mentioning or excluding others; or that a certain course of action is preferred but not necessarily required; or that (in the negative form) a certain course of action is deprecated but not prohibited (should equals is recommended that).
“應該”這個詞用來表示在幾種可能性中,推薦其中一種作為特別合適的選擇,而不提及或排除其他選擇;或者表示某種行動方案是首選,但不一定是必需的;或者在否定形式中,表示某種行動方案是不被贊成的,但並不被禁止(應該等於建議這樣做)。

The word may is used to indicate a course of action permissible within the limits of the Specification (may equals is permitted to).
“may”這個詞用來表示在規範的範圍內允許的行動(may 等於被允許)。

The word can is used for statements of possibility and capability, whether material, physical, or causal (can equals is able to).
「can」這個詞用於表示可能性和能力的陳述,無論是物質的、物理的還是因果的(can 等於能夠)。

All sections are normative, unless they are explicitly indicated to be informative.
所有部分都是規範性的,除非明確指示為資訊性。

2.2 Definitions 2.2 定義

Bi-directional: A single Data Lane that supports communication in both the Forward and Reverse directions.
雙向:一個單一數據通道,支持前向和反向的通信。

DDR Clock: Half rate clock used for dual-edged data transmission.
DDR 時鐘:用於雙邊數據傳輸的半速時鐘。

D-PHY: The source synchronous PHY defined in this document. D-PHYs communicate on the order of 500 Mbit / s 500 Mbit / s 500Mbit//s500 \mathrm{Mbit} / \mathrm{s} hence the Roman numeral for 500 or “D.”
D-PHY:本文件中定義的源同步 PHY。D-PHY 的通信速度約為 500 Mbit / s 500 Mbit / s 500Mbit//s500 \mathrm{Mbit} / \mathrm{s} ,因此羅馬數字為 500 或“D”。

Escape Mode: An optional mode of operation for Data Lanes that allows low bit-rate commands and data to be transferred at very low power.
逃逸模式:數據通道的一種可選操作模式,允許以非常低的功率傳輸低比特率的命令和數據。

Forward Direction: The signal direction is defined relative to the direction of the High-Speed DDR clock. Transmission from the side sending the clock to the side receiving the clock is the Forward direction.
前進方向:信號方向是相對於高速 DDR 時鐘的方向定義的。從發送時鐘的一側到接收時鐘的一側的傳輸是前進方向。

Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane Interconnects. Sometimes Lane is also used to denote interconnect only. A Lane can be used for either Data or Clock signal transmission.
通道:由兩個互補的通道模組通過雙線點對點通道互連進行通信。有時通道也用來僅表示互連。通道可以用於數據或時鐘信號傳輸。

Lane Interconnect: Two-line, point-to-point interconnect used for both differential High-Speed signaling and Low-Power, single-ended signaling.
通道互連:用於差分高速信號和低功耗單端信號的雙線點對點互連。

Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane.
車道模組:位於車道兩側的模組,用於駕駛和/或接收車道上的信號。

Line: An interconnect wire used to connect a driver to a receiver. Two Lines are required to create a Lane Interconnect.
用於將驅動器連接到接收器的互連線。創建通道互連需要兩條線。

Link: A connection between two devices containing one Clock Lane and at least one Data Lane. A Link consists of at least two PHYs and two Lane Interconnects.
鏈接:兩個設備之間的連接,包含一個時鐘通道和至少一個數據通道。鏈接由至少兩個 PHY 和兩個通道互連組成。

Master: The Master side of a Link is defined as the side that transmits the High-Speed Clock. The Master side transmits data in the Forward direction.
主控端:鏈路的主控端定義為傳輸高速時鐘的端。主控端以正向方向傳輸數據。
PHY: A functional block that implements the features necessary to communicate over the Lane Interconnect. A PHY consists of one Lane Module configured as a Clock Lane, one or more Lane Modules configured as Data Lanes and a PHY Adapter Layer.
PHY:一個功能區塊,實現了在通道互連上進行通信所需的特性。PHY 由一個配置為時鐘通道的通道模組、一個或多個配置為數據通道的通道模組和一個 PHY 適配層組成。

PHY Adapter: A protocol layer that converts symbols from an APPI to the signals used by a specific PHY PPI.
PHY 轉接器:一個協議層,將 APPI 的符號轉換為特定 PHY PPI 使用的信號。

PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a minimum of two Lanes, one Clock Lane and one or more Data Lanes.
PHY 配置:一組代表可能鏈路的通道。PHY 配置至少由兩個通道組成,一個時鐘通道和一個或多個數據通道。
Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for Forward Direction.
反向方向:反向方向是前進方向的相反方向。請參閱前進方向的描述。
Slave: The Slave side of a Link is defined as the side that does not transmit the High-Speed Clock. The Slave side may transmit data in the Reverse direction.
從屬設備:鏈路的從屬設備端定義為不傳輸高速時鐘的那一側。從屬設備端可以以反向方向傳輸數據。
Turnaround: Reversing the direction of communication on a Data Lane.
轉向:在數據通道上反轉通信方向。

Unidirectional: A single Lane that supports communication in the Forward direction only.
單向:一條僅支持向前方向通信的單車道。

2.3 Abbreviations 2.3 縮寫

e.g. For example (Latin: exempli gratia)
例如 (拉丁文:exempli gratia)

i.e. That is (Latin: id est)
即是(拉丁文:id est)

2.4 Acronyms 2.4 縮寫詞

APPI
BER Bit Error Rate
比特錯誤率

CIL Control and Interface Logic
CIL 控制與介面邏輯

DDR Double Data Rate
DDR 雙倍數據速率

DUT
EMI
EoT
HS
HS-RX
HS-TX
IO
ISTO Industry Standards and Technology Organization
ISTO 行業標準與技術組織

LP Low-Power: identifier for operation mode
LP 低功耗:操作模式的識別碼

LP-CD Low-Power Contention Detector
LP-CD 低功耗爭用檢測器

LPDT Low-Power Data Transmission
LPDT 低功耗數據傳輸

LP-RX Low-Power Receiver (Large-Swing Single-Ended)
LP-RX 低功耗接收器(大擺幅單端)

LP-TX Low-Power Transmitter (Large-Swing Single-Ended)
LP-TX 低功耗發射器(大擺幅單端)

LPS Low-Power State(s) LPS 低功耗狀態
LSB Least Significant Bit
LSB 最低有效位
Version 2.0 版本 2.0 Specification for D-PHY D-PHY 規範
23-Nov-2015
144 Mbps Megabits per second 每秒兆位元
145 MSB Most Significant Bit 最重要位元
146 PHY Physical Layer 物理層
147 PLL Phase-Locked Loop 相位鎖定迴路
148 PPI PHY-Protocol Interface
149 RF Radio Frequency 無線電頻率
150 RX Receiver 接收器
151 SE Single-Ended 單端
152 SoT Start of Transmission 傳輸開始
153 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master
傳輸線互連結構:主控之間的物理互連實現
154 and Slave 和奴隸
155 TX Transmitter 發射器
156 UI Unit Interval, equal to the duration of any HS state on the Clock Lane
單位間隔,等於時鐘線上任何高電平狀態的持續時間
157 ULPS Ultra-Low Power State 超低功耗狀態
Version 2.0 Specification for D-PHY 23-Nov-2015 144 Mbps Megabits per second 145 MSB Most Significant Bit 146 PHY Physical Layer 147 PLL Phase-Locked Loop 148 PPI PHY-Protocol Interface 149 RF Radio Frequency 150 RX Receiver 151 SE Single-Ended 152 SoT Start of Transmission 153 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master 154 and Slave 155 TX Transmitter 156 UI Unit Interval, equal to the duration of any HS state on the Clock Lane 157 ULPS Ultra-Low Power State| | Version 2.0 | Specification for D-PHY | | :--- | :--- | :--- | | | 23-Nov-2015 | | | 144 | Mbps | Megabits per second | | 145 | MSB | Most Significant Bit | | 146 | PHY | Physical Layer | | 147 | PLL | Phase-Locked Loop | | 148 | PPI | PHY-Protocol Interface | | 149 | RF | Radio Frequency | | 150 | RX | Receiver | | 151 | SE | Single-Ended | | 152 | SoT | Start of Transmission | | 153 | TLIS | Transmission-Line Interconnect Structure: physical interconnect realization between Master | | 154 | | and Slave | | 155 | TX | Transmitter | | 156 | UI | Unit Interval, equal to the duration of any HS state on the Clock Lane | | 157 | ULPS | Ultra-Low Power State |

3 References 3 參考文獻

[MIPI01] MIPI Alliance Specification for D-PHY, Version 1.0, MIPI Alliance, Inc., 22 September 2009.
[MIPI01] MIPI 聯盟 D-PHY 規範,版本 1.0,MIPI 聯盟公司,2009 年 9 月 22 日。

[MIPI02] MIPI Alliance Specification for C-PHY, Version 1.0, MIPI Alliance, Inc., 7 October 2014.
[MIPI02] MIPI 聯盟 C-PHY 規範,版本 1.0,MIPI 聯盟公司,2014 年 10 月 7 日。

4 D-PHY Overview 4 D-PHY 概述

D-PHY describes a source synchronous, high speed, low power, low cost PHY, especially suited for mobile applications. This D-PHY specification has been written primarily for the connection of camera and display applications to a host processor. Nevertheless, it can be applied to many other applications. It is envisioned that the same type of PHY will also be used in a dual-simplex configuration for interconnections in a more generic communication network. Operation and available data-rates for a Link are asymmetrical due to a master-slave relationship between the two sides of the Link. The asymmetrical design significantly reduces the complexity of the Link. Some features like bi-directional, half-duplex operation are optional. Exploiting this feature is attractive for applications that have asymmetrical data traffic requirements and when the cost of separate interconnects for a return channel is too high. While this feature is optional, it avoids mandatory overhead costs for applications that do not have return traffic requirements or want to apply physically distinct return communication channels.
D-PHY 描述了一種源同步、高速、低功耗、低成本的 PHY,特別適合於移動應用。這個 D-PHY 規範主要是為了將相機和顯示應用連接到主處理器而編寫的。然而,它也可以應用於許多其他應用。預期同類型的 PHY 也將在雙簡單配置中用於更通用的通信網絡中的互連。由於鏈路兩側之間的主從關係,鏈路的操作和可用數據速率是不對稱的。不對稱設計顯著降低了鏈路的複雜性。一些特性,如雙向、半雙工操作是可選的。利用這一特性對於具有不對稱數據流量需求的應用是有吸引力的,尤其是在返回通道的單獨互連成本過高的情況下。雖然這一特性是可選的,但它避免了對於沒有返回流量需求或希望應用物理上不同的返回通信通道的應用的強制性開銷成本。

4.1 Summary of PHY Functionality
4.1 PHY 功能摘要

The D-PHY provides a synchronous connection between Master and Slave. A practical PHY Configuration consists of a clock signal and one or more data signals. The clock signal is unidirectional, originating at the Master and terminating at the Slave. The data signals can either be unidirectional or bi-directional depending on the selected options. For half-duplex operation, the reverse direction bandwidth is one-fourth of the forward direction bandwidth. Token passing is used to control the communication direction of the Link.
D-PHY 提供了主設備和從設備之間的同步連接。實際的 PHY 配置由時鐘信號和一個或多個數據信號組成。時鐘信號是單向的,起源於主設備並終止於從設備。數據信號可以是單向或雙向,具體取決於所選擇的選項。對於半雙工操作,反向帶寬是正向帶寬的四分之一。令牌傳遞用於控制鏈路的通信方向。

The Link includes a High-Speed signaling mode for fast-data traffic and a Low-Power signaling mode for control purposes. Optionally, a Low-Power Escape mode can be used for low speed asynchronous data communication. High speed data communication appears in bursts with an arbitrary number of payload data bytes.
該鏈接包括一種高速信號模式,用於快速數據流量,以及一種低功耗信號模式,用於控制目的。可選擇使用低功耗逃逸模式進行低速異步數據通信。高速數據通信以突發形式出現,具有任意數量的有效載荷數據字節。

The PHY uses two wires per Data Lane plus two wires for the Clock Lane. This gives four wires for the minimum PHY configuration. In High-Speed mode each Lane is terminated on both sides and driven by a low-swing, differential signal. In Low-Power mode all wires are operated single-ended and non-terminated. For EMI reasons, the drivers for this mode shall be slew-rate controlled and current limited.
PHY 使用每個數據通道兩根線,外加兩根時鐘通道的線。這樣最小的 PHY 配置就有四根線。在高速模式下,每個通道在兩側都有終端,並由低擺幅的差分信號驅動。在低功耗模式下,所有線路均為單端操作且不終端。出於電磁干擾的原因,該模式的驅動器應受限於斜率控制和電流限制。

The actual maximum achievable bit rate in High-Speed mode is determined by the performance of transmitter, receiver and interconnect implementations. Therefore, the maximum bit rate is not specified in this document. However, this specification is primarily intended to define a solution for a data rate range of 80 to 1500 Mbps per Lane without deskew calibration, up to 2500 Mbps with deskew calibration, and up to 4500 Mbps with equalization. When the implementation supports a data rate greater than 1500 Mbps , it shall also support deskew capability. When a Phy implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available. Although PHY Configurations are not limited to this range, practical constraints make it the most suitable range for the intended applications. For a fixed clock frequency, the available data capacity of a PHY Configuration can be increased by using more Data Lanes. Effective data throughput can be reduced by employing burst mode communication. The maximum data rate in Low-Power mode is 10 Mbps .
在高速模式下,實際可達到的最大比特率由發射器、接收器和互連實現的性能決定。因此,本文件中未指定最大比特率。然而,本規範主要旨在定義一種解決方案,適用於每條通道 80 至 1500 Mbps 的數據速率範圍,無需去偏校準,最高可達 2500 Mbps,並且在進行均衡時可達 4500 Mbps。當實現支持超過 1500 Mbps 的數據速率時,還必須支持去偏能力。當物理實現支持超過 2500 Mbps 的數據速率時,還必須支持均衡,並且應提供擴頻時鐘。雖然 PHY 配置不僅限於此範圍,但實際限制使其成為最適合的範圍,適用於預期的應用。對於固定的時鐘頻率,可以通過使用更多數據通道來增加 PHY 配置的可用數據容量。通過採用突發模式通信,有效數據吞吐量可能會降低。低功耗模式下的最大數據速率為 10 Mbps。
The features introduced by this specification (Spread Spectrum Clocking, Transmit Equalization, and Deskew) can be applied to any HS data rate.
本規範所引入的特性(擴頻時鐘、傳輸均衡和去偏移)可以應用於任何 HS 數據速率。

4.2 Mandatory Functionality
4.2 強制功能

All functionality that is specified in this document and which is not explicitly stated in Section 5.5 shall be implemented for all D-PHY configurations.
本文件中指定的所有功能,未在第 5.5 節中明確說明的,應適用於所有 D-PHY 配置。

5 Architecture 5 建築學

This section describes the internal structure of the PHY including its functions at the behavioral level. Furthermore, several possible PHY configurations are given. Each configuration can be considered as a suitable combination from a set of basic modules.
本節描述了 PHY 的內部結構,包括其在行為層面的功能。此外,還提供了幾種可能的 PHY 配置。每種配置可以被視為從一組基本模塊中選擇的合適組合。

5.1 Lane Modules 5.1 車道模組

A PHY configuration contains a Clock Lane Module and one or more Data Lane Modules. Each of these PHY Lane Modules communicates via two Lines to a complementary part at the other side of the Lane Interconnect.
一個 PHY 配置包含一個時鐘通道模組和一個或多個數據通道模組。這些 PHY 通道模組中的每一個通過兩條線與通道互連另一側的互補部分進行通信。

Each Lane Module consists of one or more differential High-Speed functions utilizing both interconnect wires simultaneously, one or more single-ended Low-Power functions operating on each of the interconnect wires individually, and control & interface logic. An overview of all functions is shown in Figure 1. HighSpeed signals have a low voltage swing, e.g. 200 mV , while Low-Power signals have a large swing, e.g. 1.2V. High-Speed functions are used for High-Speed Data transmission. The Low-Power functions are mainly used for Control, but have other, optional, use cases. The I/O functions are controlled by a Lane Control and Interface Logic block. This block interfaces with the Protocol and determines the global operation of the Lane Module.
每個通道模組由一個或多個差分高速功能組成,這些功能同時利用兩根互連線,還有一個或多個單端低功耗功能,分別在每根互連線上運作,以及控制和介面邏輯。所有功能的概述如圖 1 所示。高速信號具有低電壓擺幅,例如 200 毫伏,而低功耗信號則具有較大的擺幅,例如 1.2 伏。高速功能用於高速數據傳輸。低功耗功能主要用於控制,但也有其他可選的使用案例。I/O 功能由通道控制和介面邏輯區塊控制。該區塊與協議介面並確定通道模組的全局操作。
High-Speed functions include a differential transmitter (HS-TX) and a differential receiver (HS-RX).
高速功能包括差分發射器(HS-TX)和差分接收器(HS-RX)。

A Lane Module may contain a HS-TX, a HS-RX, or both. A HS-TX and a HS-RX within a single Lane Module are never enabled simultaneously during normal operation. An enabled High-Speed function shall terminate the Lane on its side of the Lane Interconnect as defined in Section 9.1.1 and Section 9.2.1. If a
一個通道模組可以包含一個 HS-TX、一個 HS-RX 或兩者皆有。在正常操作期間,單一通道模組內的 HS-TX 和 HS-RX 不會同時啟用。啟用的高速功能應根據第 9.1.1 節和第 9.2.1 節的定義,在通道互連的一側終止通道。若一個
High-Speed function in the Lane Module is not enabled then the function shall be put into a high impedance state.
如果車道模組中的高速功能未啟用,則該功能將進入高阻抗狀態。
Low-Power functions include single-ended transmitters (LP-TX), receivers (LP-RX) and Low-Power Contention-Detectors (LP-CD). Low-Power functions are always present in pairs as these are single-ended functions operating on each of the two interconnect wires individually.
低功耗功能包括單端發射器(LP-TX)、接收器(LP-RX)和低功耗競爭檢測器(LP-CD)。低功耗功能總是成對出現,因為這些是單端功能,分別在兩根互連線上運作。

Presence of High-Speed and Low-Power functions is correlated. That is, if a Lane Module contains a HSTX it shall also contain a LP-TX. A similar constraint holds for HS-RX and LP-RX.
高速度和低功耗功能的存在是相關的。也就是說,如果一個通道模組包含 HSTX,它也必須包含 LP-TX。HS-RX 和 LP-RX 也有類似的限制。
If a Lane Module containing a LP-RX is powered, that LP-RX shall always be active and continuously monitor line levels. A LP-TX shall only be enabled when driving Low-Power states. The LP-CD function is only required for bi-directional operation. If present, the LP-CD function is enabled to detect contention situations while the LP-TX is driving Low-Power states. The LP-CD checks for contention before driving a new state on the line except in ULPS.
如果包含 LP-RX 的通道模組通電,該 LP-RX 將始終處於活動狀態並持續監控線路電平。只有在驅動低功耗狀態時,LP-TX 才會啟用。LP-CD 功能僅在雙向操作時需要。如果存在,LP-CD 功能將啟用以檢測競爭情況,當 LP-TX 驅動低功耗狀態時。LP-CD 在驅動新狀態到線路之前檢查競爭情況,ULPS 除外。
The activities of LP-TX, HS-TX, and HS-RX in a single Lane Module are mutually exclusive, except for some short crossover periods. For detailed specification of the Line side Clock and Data signals, and the HS-TX, HS-RX, LP-TX, LP-RX and LP-CD functions, see Section 9 and Section 10.
LP-TX、HS-TX 和 HS-RX 在單一通道模組中的活動是互斥的,除了某些短暫的交叉期間。關於線側時鐘和數據信號的詳細規範,以及 HS-TX、HS-RX、LP-TX、LP-RX 和 LP-CD 功能,請參見第 9 節和第 10 節。
For proper operation, the set of functions in the Lane Modules on both sides of the Lane Interconnect has to be matched. This means for each HS and LP transmit or receive function on one side of the Lane Interconnect, a complementary HS or LP receive or transmit function must be present on the other side. In addition, a Contention Detector is needed in any Lane Module that combines TX and RX functions.
為了正常運作,通道互連兩側的通道模組中的功能集必須匹配。這意味著在通道互連一側的每個 HS 和 LP 發送或接收功能,另一側必須存在一個互補的 HS 或 LP 接收或發送功能。此外,任何結合 TX 和 RX 功能的通道模組都需要一個爭用檢測器。

5.2 Master and Slave
5.2 主從

Each Link has a Master and a Slave side. The Master provides the High-Speed DDR Clock signal to the Clock Lane and is the main data source. The Slave receives the clock signal at the Clock Lane and is the main data sink. The main direction of data communication, from source to sink, is denoted as the Forward direction. Data communication in the opposite direction is called Reverse transmission. Only bi-directional Data Lanes can transmit in the Reverse direction. In all cases, the Clock Lane remains in the Forward direction, but bi-directional Data Lane(s) can be turned around, sourcing data from the Slave side.
每個連接都有主端和從端。主端向時鐘通道提供高速 DDR 時鐘信號,並且是主要數據源。從端在時鐘通道接收時鐘信號,並且是主要數據接收端。數據通信的主要方向,從源到接收端,稱為前向方向。相反方向的數據通信稱為反向傳輸。只有雙向數據通道可以在反向方向上傳輸。在所有情況下,時鐘通道保持在前向方向,但雙向數據通道可以反向,從從端獲取數據。

5.3 High Frequency Clock Generation
5.3 高頻時鐘生成

In many cases a PLL Clock Multiplier is needed for the high frequency clock generation at the Master Side. The D-PHY specification uses an architectural model where a separate Clock Multiplier Unit outside the PHY generates the required high frequency clock signals for the PHY. Whether this Clock Multiplier Unit in practice is integrated inside the PHY is left to the implementer.
在許多情況下,主端需要一個 PLL 時鐘倍增器來生成高頻時鐘。D-PHY 規範使用一種架構模型,其中 PHY 外部的獨立時鐘倍增器單元生成 PHY 所需的高頻時鐘信號。這個時鐘倍增器單元在實際上是否集成在 PHY 內部則由實施者決定。

5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface
5.4 時鐘通道、數據通道和 PHY 協議介面

A complete Link contains, beside Lane Modules, a PHY Adapter Layer that ties all Lanes, the Clock Multiplier Unit, and the PHY Protocol Interface together. Figure 2 shows a PHY configuration example for a Link with two Data Lanes plus a separate Clock Multiplier Unit. The PHY Adapter Layer, though a component of a PHY, is not within the scope of this specification.
一個完整的連結除了通道模組外,還包含一個將所有通道、時鐘倍增單元和 PHY 協議介面連接在一起的 PHY 適配層。圖 2 顯示了一個具有兩個數據通道和一個單獨時鐘倍增單元的連結的 PHY 配置示例。雖然 PHY 適配層是 PHY 的一個組件,但不在本規範的範疇內。

The logical PHY-Protocol interface (PPI) for each individual Lane includes a set of signals to cover the functionality of that Lane. As shown in Figure 2, Clock signals may be shared for all Lanes. The reference clock and control signals for the Clock Multiplier Unit are not within the scope of this specification.
每個獨立通道的邏輯 PHY 協議介面(PPI)包括一組信號,以涵蓋該通道的功能。如圖 2 所示,時鐘信號可以在所有通道之間共享。時鐘倍增單元的參考時鐘和控制信號不在本規範的範疇內。

Figure 2 Two Data Lane PHY Configuration
圖 2 兩個數據通道 PHY 配置

5.5 Selectable Lane Options
5.5 可選車道選項

A PHY configuration consists of one Clock Lane and one or more Data Lanes. All Data Lanes shall support High-Speed transmission and Escape mode in the Forward direction.
PHY 配置由一個時鐘通道和一個或多個數據通道組成。所有數據通道應支持高速傳輸和正向逃逸模式。

There are two main types of Data Lanes:
有兩種主要的數據通道:
  • Bi-directional (featuring Turnaround and some Reverse communication functionality)
    雙向(具備回轉和某些反向通信功能)
  • Unidirectional (without Turnaround or any kind of Reverse communication functionality)
    單向(不帶回轉或任何形式的反向通信功能)
Bi-directional Data Lanes shall include one or both of the following Reverse communication options:
雙向數據通道應包括以下一種或兩種反向通信選項:
  • High-Speed Reverse data communication
    高速反向數據通信
  • Low-Power Reverse Escape mode (including or excluding LPDT)
    低功耗反向逃逸模式(包括或不包括 LPDT)
All Lanes shall include Escape mode support for ULPS and Triggers in the Forward direction. Other Escape mode functionality is optional; all possible Escape mode features are described in Section 6.6. Applications shall define what additional Escape mode functionality is required and, for bi-directional Lanes, shall select Escape mode functionality for each direction individually.
所有通道應包括對 ULPS 和向前方向觸發的逃逸模式支持。其他逃逸模式功能是可選的;所有可能的逃逸模式特性在第 6.6 節中描述。應用程序應定義所需的其他逃逸模式功能,並且對於雙向通道,應分別選擇每個方向的逃逸模式功能。
This results in many options for complete PHY Configurations. The degrees of freedom are:
這導致了許多完整的 PHY 配置選項。自由度為:
  • Single or Multiple Data Lanes
    單一或多個數據通道
  • Bi-directional and/or Unidirectional Data Lane (per Lane)
    雙向和/或單向數據通道(每通道)
  • Supported types of Reverse communication (per Lane)
    支持的反向通信類型(按通道)
  • Functionality supported by Escape mode (for each direction per Lane)
    逃脫模式支持的功能(每條車道的每個方向)
  • Data transmission can be with 8-bit raw data (default) or using 8b9b encoded symbol (see Annex C)
    數據傳輸可以使用 8 位原始數據(默認)或使用 8b9b 編碼符號(見附錄 C)
Figure 3 is a flow graph of the option selection process. Practical configuration examples can be found in Section 5.7.
圖 3 是選項選擇過程的流程圖。實際配置示例可以在第 5.7 節找到。

Figure 3 Option Selection Flow Graph
圖 3 選項選擇流程圖

Copyright (©) 2007-2016 MIPI Alliance, Inc.
版權所有 (©) 2007-2016 MIPI 聯盟公司。

5.6 Lane Module Types
5.6 車道模組類型

The required functions in a Lane Module depend on the Lane type and which side of the Lane Interconnect the Lane Module is located. There are three main Lane types: Clock Lane, Unidirectional Data Lane and Bi-directional Data Lane. Several PHY configurations can be constructed with these Lane types. See Figure 3 for more information on selecting Lane options.
Lane 模組中所需的功能取決於 Lane 類型以及 Lane 模組位於 Lane 互連的哪一側。主要有三種 Lane 類型:時鐘 Lane、單向數據 Lane 和雙向數據 Lane。可以使用這些 Lane 類型構建幾種 PHY 配置。請參見圖 3 以獲取有關選擇 Lane 選項的更多信息。
Figure 4 shows a Universal Lane Module Diagram with a global overview of internal functionality of the CIL function. This Universal Module can be used for all Lane Types. The requirements for the ‘Control and Interface Logic’ (CIL) function depend on the Lane type and Lane side. Section 6 and Annex A implicitly specify the contents of the CIL function. The actual realization is left to the implementer.
圖 4 顯示了一個通用車道模組圖,提供了 CIL 功能內部功能的全球概覽。這個通用模組可以用於所有車道類型。對於“控制和介面邏輯”(CIL)功能的要求取決於車道類型和車道側。第 6 節和附錄 A 隱含地指定了 CIL 功能的內容。實際實現則留給實施者。

Figure 4 Universal Lane Module Architecture
圖 4 通用車道模組架構

Of course, stripped-down versions of the Universal Lane Module that just support the required functionality for a particular Lane type are possible. These stripped-down versions are identified by the acronyms in Table 1. For simplification reasons, any of the four identification characters can be replaced by an X, which means that this can be any of the available options. For example, a CIL-MFEN is therefore a stripped-down CIL function for the Master Side of a Unidirectional Lane with Escape mode functionality only in the Forward direction. A CIL-SRXX is a CIL function for the Slave Side of a Lane with support for Bidirectional High-Speed communication and any allowed subset of Escape mode.
當然,僅支持特定通道類型所需功能的簡化版通用通道模組是可能的。這些簡化版通過表 1 中的縮寫來識別。出於簡化原因,四個識別字符中的任何一個都可以用 X 替換,這意味著這可以是任何可用選項。例如,CIL-MFEN 因此是一個僅在前進方向上具有逃逸模式功能的單向通道主側的簡化 CIL 功能。CIL-SRXX 是一個支持雙向高速通信和任何允許的逃逸模式子集的通道從側的 CIL 功能。
Note that a CIL-XFXN implies a unidirectional Link, while either a CIL-XRXX or CIL-XXXY block implies a bidirectional Link. Note that Forward 'Escape’ (ULPS) entry for Clock Lanes is different than Escape mode entry for Data Lanes.
請注意,CIL-XFXN 表示單向鏈接,而 CIL-XRXX 或 CIL-XXXY 區塊則表示雙向鏈接。請注意,時鐘通道的前向「逃逸」(ULPS)進入與數據通道的逃逸模式進入不同。
Table 1 Lane Type Descriptors
表 1 車道類型描述
Prefix 前綴
 通道互連側
Lane
Interconnect Side
Lane Interconnect Side| Lane | | :--- | | Interconnect Side |
High-Speed Capabilities 高速能力

前進方向逃脫模式支援的功能
Forward
Direction Escape Mode Features Supported
Forward Direction Escape Mode Features Supported| Forward | | :--- | | Direction Escape Mode Features Supported |

反向方向逃逸模式支持的功能 1 1 ^(1){ }^{1}
Reverse
Direction Escape
Mode Features Supported 1 1 ^(1){ }^{1}
Reverse Direction Escape Mode Features Supported ^(1)| Reverse | | :--- | | Direction Escape | | Mode Features Supported ${ }^{1}$ |
CIL-

M - 主控 S - 從屬 X - 不在乎
M - Master
S - Slave
X - Don't Care
M - Master S - Slave X - Don't Care| M - Master | | :--- | | S - Slave | | X - Don't Care |

F - 僅前進 R R RR - 反向和前進 X - 不在乎 2 2 ^(2){ }^{2}
F - Forward Only
R R RR - Reverse and Forward
X - Don't Care 2 2 ^(2){ }^{2}
F - Forward Only R - Reverse and Forward X - Don't Care ^(2)| F - Forward Only | | :--- | | $R$ - Reverse and Forward | | X - Don't Care ${ }^{2}$ |

A - 全部(包括 LPDT) E - 事件 觸發器和 ULPS 只有 X - 不在乎
A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care
A - All (including LPDT) E - events Triggers and ULPS Only X - Don't Care| A - All (including LPDT) | | :--- | | E - events Triggers and ULPS Only X - Don't Care |
A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock N - Not Applicable
N - 不適用
N - Not Applicable
N - 不適用
Prefix "Lane Interconnect Side" High-Speed Capabilities "Forward Direction Escape Mode Features Supported" "Reverse Direction Escape Mode Features Supported ^(1)" CIL- "M - Master S - Slave X - Don't Care" "F - Forward Only R - Reverse and Forward X - Don't Care ^(2)" "A - All (including LPDT) E - events Triggers and ULPS Only X - Don't Care" A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care C-Clock N - Not Applicable N - Not Applicable| Prefix | Lane <br> Interconnect Side | High-Speed Capabilities | Forward <br> Direction Escape Mode Features Supported | Reverse <br> Direction Escape <br> Mode Features Supported ${ }^{1}$ | | :---: | :---: | :---: | :---: | :---: | | CIL- | M - Master <br> S - Slave <br> X - Don't Care | F - Forward Only <br> $R$ - Reverse and Forward <br> X - Don't Care ${ }^{2}$ | A - All (including LPDT) <br> E - events Triggers and ULPS Only X - Don't Care | ```A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care``` | | | | C-Clock | N - Not Applicable | N - Not Applicable |
Note: 注意:
  1. “Any” is any combination of one or more functions.
    “任何”是由一個或多個函數的任意組合。
  2. Only valid for Data Lanes, means “F” or “R”.
    僅適用於數據通道,表示“F”或“R”。
The recommend PHY Protocol Interface contains Data-in and Data-out in byte format, Input and/or output Clock signals and Control signals. Control signals include requests, handshakes, test settings, and initialization. A proposal for a logical internal interface is described in Annex A. Although not a requirement it may be very useful to use the proposed PPI. For external use on IC’s an implementation may multiplex many signals on the same pins. However, for power efficiency reasons, the PPI is normally within an IC.
推薦的 PHY 協議介面包含以位元組格式的數據輸入和數據輸出、輸入和/或輸出時鐘信號以及控制信號。控制信號包括請求、握手、測試設置和初始化。附錄 A 中描述了一個邏輯內部介面的提案。雖然這不是一個要求,但使用提議的 PPI 可能非常有用。對於 IC 的外部使用,實現可能會在相同的引腳上多路復用許多信號。然而,出於功率效率的原因,PPI 通常位於 IC 內部。

5.6.1 Unidirectional Data Lane
5.6.1 單向數據通道

For a Unidirectional Data Lane the Master Module shall contain at least a HS-TX, a LP-TX, and a CILMFXN function. The Slave side shall contain at least a HS-RX, a LP-RX and a CIL-SFXN.
對於單向數據通道,主模塊應至少包含一個 HS-TX、一個 LP-TX 和一個 CILMFXN 功能。從屬端應至少包含一個 HS-RX、一個 LP-RX 和一個 CIL-SFXN。

5.6.2 Bi-directional Data Lanes
5.6.2 雙向數據通道

A bi-directional Data Lane Module includes some form of reverse communication; either High-Speed Reverse Communication, Reverse Escape mode, or both. The functions required depend on what methods of Reverse communication are included in the Lane Module.
雙向數據通道模組包括某種形式的反向通信;無論是高速反向通信、反向逃逸模式,還是兩者皆有。所需的功能取決於通道模組中包含的反向通信方法。

5.6.2.1 Bi-directional Data Lane without High-Speed Reverse Communication
5.6.2.1 雙向數據通道無高速反向通信

A bi-directional Data Lane Module without High-Speed Reverse Communication shall include a Reverse Escape mode. The Master-side Lane Module includes a HS-TX, LP-TX, LP-RX, LP-CD, and CIL-MFXY. The Slave-side consists of a HS-RX, LP-RX, LP-TX, LP-CD and a CIL-SFXY.
一個不具備高速反向通信的雙向數據通道模塊應包括一個反向逃逸模式。主端通道模塊包括 HS-TX、LP-TX、LP-RX、LP-CD 和 CIL-MFXY。從端則由 HS-RX、LP-RX、LP-TX、LP-CD 和 CIL-SFXY 組成。

5.6.2.2 Bi-directional Data Lane with High-Speed Reverse Communication
5.6.2.2 雙向數據通道與高速反向通信

A bi-directional Data Lane Module with High-Speed Reverse Communication shall include a Reverse Escape mode. The Master-side Lane Module includes a HS-TX, HS-RX, LP-TX, LP-RX, LP-CD, and CILMRXX. The Slave-side consists of a HS-RX, HS-TX, LP-RX, LP-TX, LP-CD and a CIL-SRXX.
一個具有高速反向通信的雙向數據通道模塊應包括一個反向逃逸模式。主端通道模塊包括 HS-TX、HS-RX、LP-TX、LP-RX、LP-CD 和 CILMRXX。從端則由 HS-RX、HS-TX、LP-RX、LP-TX、LP-CD 和 CIL-SRXX 組成。
This type of Lane Module may seem suitable for both Master and Slave side but because of the asymmetry of the Link one side shall be configured as Master and the other side as Slave.
這種類型的通道模組可能看起來適合主端和從端,但由於鏈接的不對稱性,一側應配置為主端,另一側則配置為從端。

5.6.3 Clock Lane 5.6.3 鐘路

For the Clock Lane, only a limited set of line states is used. However, for Clock Transmission and LowPower mode the same TX and RX functions are required as for Unidirectional Data Lanes. A Clock Lane Module for the Master Side therefore contains a HS-TX, LP-TX, and a CIL-MCNN function, while the Slave Side Module includes a HS-RX, a LP-RX and a CIL-SCNN function.
對於時鐘通道,只使用有限的一組線狀態。然而,對於時鐘傳輸和低功耗模式,與單向數據通道相同的 TX 和 RX 功能是必需的。因此,主端的時鐘通道模組包含 HS-TX、LP-TX 和 CIL-MCNN 功能,而從端模組則包括 HS-RX、LP-RX 和 CIL-SCNN 功能。

Note that the required functionality for a Clock Lane is similar, but not identical, to a Unidirectional Data Lane. The High-Speed DDR clock is transmitted in quadrature phase with Data signals instead of in-phase. In addition, the Clock Lane Escape mode entry is different than that used for Data Lanes. Furthermore, since a Clock Lane only supports ULPS, an Escape mode entry code is not required.
請注意,時鐘通道所需的功能與單向數據通道相似,但並不相同。高速 DDR 時鐘以與數據信號正交相位而非同相位的方式傳輸。此外,時鐘通道的逃逸模式進入方式與數據通道使用的方式不同。此外,由於時鐘通道僅支持 ULPS,因此不需要逃逸模式進入代碼。
The internal clock signals with the appropriate phases are generated outside the PHY and delivered to the individual Lanes. The realization of the Clock generation unit is outside the scope of this specification. The quality of the internal clock signals shall be sufficient to meet the timing requirement for the signals as specified in Section 10.
內部時鐘信號與適當的相位是在 PHY 外部生成並傳遞到各個通道。時鐘生成單元的實現不在本規範的範疇內。內部時鐘信號的質量應足以滿足第 10 節中規定的信號時序要求。

5.7 Configurations 5.7 配置

This section outlines several common PHY configurations but should not be considered an exhaustive list of all possible arrangements. Any other configuration that does not violate the requirements of this document is also allowed.
本節概述了幾種常見的 PHY 配置,但不應被視為所有可能安排的詳盡列表。任何其他不違反本文件要求的配置也都是允許的。
In order to create an abstraction level, the Lane Modules are represented in this section by Lane Module Symbols. Figure 5 shows the syntax and meaning of symbols.
為了創建一個抽象層級,本節中用車道模組符號表示車道模組。圖 5 顯示了符號的語法和含義。

This 這個 Other Options 其他選項 Meaning 意義
C1CCCCCCC1
Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional)
支持的高速數據傳輸方向(雙向或單向)
C1[I-][In][IH]1I-InIH
C1C[I-][I-]1I-I-
Clock Lane 時鐘巷
longleftrightarrow\longleftrightarrow longrightarrow\longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only)
支持的逃逸模式方向,排除 LPDT(雙向或僅前進)
⊮⟶ ⊮⟶ ⊮ longrightarrow\nVdash \longrightarrow ⋙≪ ⋙≪ ⋙≪\ggg \ll

支持的逃逸模式方向包括 LPDT(雙向、僅向前或僅向後)
Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)
Supported Directions for Escape mode including LPDT (Bi-directional, Forward Only or Reverse Only)| Supported Directions for Escape mode including LPDT | | :--- | | (Bi-directional, Forward Only or Reverse Only) |
rarr\rightarrow larr\leftarrow

時鐘方向(根據定義從主設備到從設備,必須指向與“僅時鐘通道”箭頭相同的方向)
Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)
Clock Direction (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)| Clock Direction | | :--- | | (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
PPI: PHY-Protocol Interface
PPI:PHY-協議介面
This Other Options Meaning C1CCCCCCC1 https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792 Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) C1[I-][In][IH]1 C1C[I-][I-]1 Clock Lane longleftrightarrow longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) ⊮ longrightarrow ⋙≪ "Supported Directions for Escape mode including LPDT (Bi-directional, Forward Only or Reverse Only)" rarr larr "Clock Direction (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)" https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607 PPI: PHY-Protocol Interface| This | Other Options | Meaning | | :---: | :---: | :---: | | <smiles>C1CCCCCCC1</smiles> | ![](https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792) | Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) | | <smiles>C1[I-][In][IH]1</smiles> | <smiles>C1C[I-][I-]1</smiles> | Clock Lane | | $\longleftrightarrow$ | $\longrightarrow$ | Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) | | $\nVdash \longrightarrow$ | $\ggg \ll$ | Supported Directions for Escape mode including LPDT <br> (Bi-directional, Forward Only or Reverse Only) | | $\rightarrow$ | $\leftarrow$ | Clock Direction <br> (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) | | ![](https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607) | | PPI: PHY-Protocol Interface |
Figure 5 Lane Symbol Macros and Symbols Legend
圖 5 車道符號宏和符號圖例
For multiple Data Lanes a large variety of configurations is possible. Figure 6 shows an overview of symbolic representations for different Lane types. The acronyms mentioned for each Lane type represent the functionality of each module in a short way. This also sets the requirements for the CIL function inside each Module.
對於多個數據通道,可以有多種配置。圖 6 顯示了不同通道類型的符號表示概述。提到的每個通道類型的縮寫簡要表示了每個模塊的功能。這也設置了每個模塊內部 CIL 功能的要求。

Figure 6 All Possible Data Lane Types and a Basic Unidirectional Clock Lane
圖 6 所有可能的數據通道類型和一個基本的單向時鐘通道

5.7.1 Unidirectional Configurations
5.7.1 單向配置

All unidirectional configurations are constructed with a Clock Lane and one or more Unidirectional Data Lanes. Two basic configurations can be distinguished: Single Data Lane and Multiple Data Lanes. For completeness a Dual-Simplex configuration is also shown. At the PHY level there is no difference between a Dual-Simplex configuration and two independent unidirectional configurations.
所有單向配置都是由一條時鐘通道和一條或多條單向數據通道構成的。可以區分兩種基本配置:單數據通道和多數據通道。為了完整性,還顯示了雙簡單配置。在 PHY 層面,雙簡單配置與兩個獨立的單向配置之間沒有區別。

5.7.1.1 PHY Configuration with a Single Data Lane
5.7.1.1 單數據通道的 PHY 配置

This configuration includes one Clock Lane and one Unidirectional Data Lane from Master to Slave. Communication is therefore only possible in the Forward direction. Figure 7 shows an example configuration without LPDT. This configuration requires four interconnect signal wires.
此配置包括一個時鐘通道和一個單向數據通道,從主設備到從設備。因此,通信僅能在前向方向進行。圖 7 顯示了一個不包含 LPDT 的示例配置。此配置需要四條互連信號線。

Figure 7 Unidirectional Single Data Lane Configuration
圖 7 單向單數據通道配置

5.7.1.2 PHY Configuration with Multiple Data Lanes
5.7.1.2 多數據通道的 PHY 配置

This configuration includes one Clock Lane and multiple Unidirectional Data Lanes from Master to Slave. Bandwidth is extended, but communication is only possible in the Forward direction. The PHY specification does not require all Data Lanes to be active simultaneously. In fact, the Protocol layer controls all Data Lanes individually. Figure 8 shows an example of this configuration for three Data Lanes. If N is the number of Data Lanes, this configuration requires 2 ( N + 1 ) 2 ( N + 1 ) 2**(N+1)2 *(\mathrm{~N}+1) interconnect wires.
此配置包括一個時鐘通道和多個從主設備到從設備的單向數據通道。帶寬得以擴展,但通信僅能在前向方向進行。PHY 規範並不要求所有數據通道同時處於活動狀態。事實上,協議層單獨控制所有數據通道。圖 8 顯示了三個數據通道的此配置示例。如果 N 是數據通道的數量,則此配置需要 2 ( N + 1 ) 2 ( N + 1 ) 2**(N+1)2 *(\mathrm{~N}+1) 互連線。

Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT
圖 8 單向多數據通道配置,無 LPDT

5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes)
5.7.1.3 雙簡單路徑(雙向單向車道)

This case is the same as two independent (dual), unidirectional (simplex) Links: one for each direction. Each direction has its own Clock Lane and may contain either a single, or multiple, Data Lanes. Please note that the Master and Slave side for the two different directions are opposite. The PHY configuration for each
此案例與兩個獨立的(雙向)單向(簡單)鏈路相同:每個方向各有一個。每個方向都有自己的時鐘通道,並且可以包含單個或多個數據通道。請注意,兩個不同方向的主端和從端是相對的。每個的 PHY 配置

direction shall comply with the D-PHY specifications. As both directions are conceptually independent, the bit rates for each direction do not have to match. However, for practical implementations, it is attractive to match rates and share some internal signals as long as both Links fulfill all specifications externally. Figure 9 shows an example of this dual PHY configuration.
方向應遵循 D-PHY 規範。由於兩個方向在概念上是獨立的,因此每個方向的比特率不必匹配。然而,對於實際實現,匹配速率並共享一些內部信號是有吸引力的,只要兩個鏈路在外部滿足所有規範。圖 9 顯示了這種雙 PHY 配置的示例。

Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT
圖 9 兩個方向使用兩個獨立的單向 PHY 而不使用 LPDT

5.7.2 Bi-Directional Half-Duplex Configurations
5.7.2 雙向半雙工配置

Bi-directional configurations consist of a Clock Lane and one or more bi-directional Data Lanes. Halfduplex operation enables bi-directional traffic across shared interconnect wires. This configuration saves wires compared to the Dual-Simplex configuration. However, time on the Link is shared between Forward and Reverse traffic and Link Turnaround. The High-Speed bit rate in the Reverse direction is, by definition, one-fourth of the bit rate in the Forward direction. LPDT can have similar rates in the Forward and Reverse directions. This configuration is especially useful for cases with asymmetrical data traffic.
雙向配置由一條時鐘通道和一條或多條雙向數據通道組成。半雙工操作使得共享互連線路上的雙向流量成為可能。與雙簡單配置相比,這種配置節省了線路。然而,鏈路上的時間在正向和反向流量以及鏈路周轉之間共享。反向方向的高速比特率根據定義是正向方向比特率的四分之一。LPDT 在正向和反向方向上可以具有相似的比率。這種配置對於不對稱數據流量的情況特別有用。

5.7.2.1 PHY Configurations with a Single Data Lane
5.7.2.1 單數據通道的 PHY 配置

This configuration includes one Clock Lane and one of any kind of bi-directional Data Lane. This allows time-multiplexed data traffic in both Forward and Reverse directions. Figure 10 shows this configuration with a Data Lane that supports both High-Speed and Escape (without LPDT) communication in both directions. Other possibilities are that only one type of reverse communication is supported or LPDT is also included in one or both directions. All these configurations require four interconnect wires.
此配置包括一個時鐘通道和一個任意類型的雙向數據通道。這允許在前向和反向方向上進行時間多路復用的數據流量。圖 10 顯示了此配置,其中數據通道支持雙向的高速和逃逸(不帶 LPDT)通信。其他可能性是僅支持一種類型的反向通信,或在一個或兩個方向上也包括 LPDT。所有這些配置都需要四根互連線。

Figure 10 Bidirectional Single Data Lane Configuration
圖 10 雙向單數據通道配置

5.7.2.2 PHY Configurations with Multiple Data Lanes
5.7.2.2 多數據通道的 PHY 配置

This configuration includes one Clock Lane and multiple bi-directional Data Lanes. Communication is possible in both the Forward and Reverse direction for each individual Lane. The maximum available bandwidth scales with the number of Lanes for each direction. The PHY specification does not require all Data Lanes to be active simultaneously or even to be operating in the same direction. In fact, the Protocol layer controls all Data Lanes individually. Figure 11 shows an example configuration with two Data Lanes. If N is the number of Data Lanes, this configuration requires 2 ( N + 1 ) 2 ( N + 1 ) 2**(N+1)2 *(\mathrm{~N}+1) interconnect wires.
此配置包括一個時鐘通道和多個雙向數據通道。每個通道都可以在前向和反向方向上進行通信。每個方向的最大可用帶寬隨通道數量的增加而增加。PHY 規範不要求所有數據通道同時處於活動狀態,甚至不要求它們在相同方向上運行。事實上,協議層單獨控制所有數據通道。圖 11 顯示了具有兩個數據通道的示例配置。如果 N 是數據通道的數量,則此配置需要 2 ( N + 1 ) 2 ( N + 1 ) 2**(N+1)2 *(\mathrm{~N}+1) 互連線。

Figure 11 Bi-directional Multiple Data Lane Configuration
圖 11 雙向多數據通道配置

5.7.3 Mixed Data Lane Configurations
5.7.3 混合數據通道配置

Instead of using only one Data Lane type, PHY configurations may combine different unidirectional and bidirectional Data Lane types. Figure 12 shows an example configuration with one bi-directional and one unidirectional Data Lane, both without LPDT.
除了使用單一的數據通道類型外,PHY 配置可以結合不同的單向和雙向數據通道類型。圖 12 顯示了一個配置示例,其中包含一個雙向和一個單向數據通道,兩者均不使用 LPDT。

Figure 12 Mixed Type Multiple Data Lane Configuration
圖 12 混合型多數據通道配置

6 Global Operation 6 全球運營

This section specifies operation of the D-PHY including signaling types, communication mechanisms, operating modes and coding schemes. Detailed specifications of the required electrical functions can be found in Section 9.
本節規定了 D-PHY 的操作,包括信號類型、通信機制、操作模式和編碼方案。所需電氣功能的詳細規範可以在第 9 節找到。

6.1 Transmission Data Structure
6.1 傳輸數據結構

During High-Speed, or Low-Power, transmission, the Link transports payload data provided by the protocol layer to the other side of the Link. This section specifies the restrictions for the transmitted and received payload data.
在高速或低功耗傳輸期間,鏈路將協議層提供的有效載荷數據傳輸到鏈路的另一端。本節規定了傳輸和接收的有效載荷數據的限制。

6.1.1 Data Units 6.1.1 數據單位

The minimum payload data unit shall be one byte. Data provided to a TX and taken from a RX on any Lane shall be an integer number of bytes. This restriction holds for both High-Speed and Low-Power data transmission in any direction.
最小有效載荷數據單位應為一個字節。提供給 TX 並從任何通道的 RX 接收的數據應為整數字節數。此限制適用於任何方向的高速和低功耗數據傳輸。

6.1.2 Bit order, Serialization, and De-Serialization
6.1.2 位元順序、序列化和反序列化

For serial transmission, the data shall be serialized in the transmitting PHY and de-serialized in the receiving PHY. The PHY assumes no particular meaning, value or order of incoming and outgoing data.
對於串行傳輸,數據應在發送的物理層中進行序列化,並在接收的物理層中進行反序列化。物理層不假設進出數據的特定含義、值或順序。

6.1.3 Encoding and Decoding
6.1.3 編碼與解碼

Line coding is not required by this specification. However, if line coding is used, it shall be implemented according to Annex C.
本規範不要求行編碼。然而,如果使用行編碼,則應根據附錄 C 實施。

6.1.4 Data Buffering 6.1.4 數據緩衝

Data transmission takes place on protocol request. As soon as communication starts, the protocol layer at the transmit side shall provide valid data as long as it does not stop its transmission request. For Lanes that use line coding, control symbols can also be inserted into the transmission. The protocol on the receive side shall take the data as soon as delivered by the receiving PHY. The signaling concept, and therefore the PHY protocol handshake, does not allow data throttling. Any data buffering for this purpose shall be inside the protocol layer.
數據傳輸在協議請求上進行。一旦通信開始,發送端的協議層應提供有效數據,只要它不停止其傳輸請求。對於使用行編碼的通道,控制符號也可以插入到傳輸中。接收端的協議應在接收 PHY 交付數據後立即接收數據。信號概念,因此 PHY 協議握手,不允許數據節流。為此目的的任何數據緩衝應在協議層內部。

6.2 Lane States and Line Levels
6.2 車道狀態和線級

Transmitter functions determine the Lane state by driving certain Line levels. During normal operation either a HS-TX or a LP-TX is driving a Lane. A HS-TX always drives the Lane differentially. The two LPTX’s drive the two Lines of a Lane independently and single-ended. This results in two possible HighSpeed Lane states and four possible Low-Power Lane states. The High-Speed Lane states are Differential-0 and Differential-1. The interpretation of Low-Power Lane states depends on the mode of operation. The LP-Receivers shall always interpret both High-Speed differential states as LP-00.
發射器功能通過驅動某些線路電平來確定通道狀態。在正常操作中,無論是 HS-TX 還是 LP-TX 都在驅動一個通道。HS-TX 始終以差分方式驅動通道。兩個 LPTX 獨立且單端地驅動一個通道的兩條線。這導致兩種可能的高速通道狀態和四種可能的低功耗通道狀態。高速通道狀態為差分-0 和差分-1。低功耗通道狀態的解釋取決於操作模式。LP 接收器應始終將兩個高速差分狀態解釋為 LP-00。
State Code 州代碼 Line Voltage Levels 線電壓水平 High-Speed 高速 Low-Power 低功耗
Dp-Line Dn-Line Burst Mode 爆炸模式 Control Mode 控制模式 Escape Mode 逃脫模式
HS-0 HS Low HS High Differential-0 N/A, Note 1 N/A, 注意 1 N/A, Note 1 N/A, 注意 1
HS-1 HS High HS Low Differential-1 N/A, Note 1 N/A, 注意 1 N/A, Note 1 N/A, 注意 1
LP-00 LP Low LP Low N/A Bridge  Space 太空
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop 停止 N/A, Note 2 不適用,註釋 2
State Code Line Voltage Levels High-Speed Low-Power Dp-Line Dn-Line Burst Mode Control Mode Escape Mode HS-0 HS Low HS High Differential-0 N/A, Note 1 N/A, Note 1 HS-1 HS High HS Low Differential-1 N/A, Note 1 N/A, Note 1 LP-00 LP Low LP Low N/A Bridge Space LP-01 LP Low LP High N/A HS-Rqst Mark-0 LP-10 LP High LP Low N/A LP-Rqst Mark-1 LP-11 LP High LP High N/A Stop N/A, Note 2| State Code | Line Voltage Levels | | High-Speed | | Low-Power | | :--- | :--- | :--- | :--- | :--- | :--- | | | Dp-Line | Dn-Line | Burst Mode | Control Mode | Escape Mode | | HS-0 | HS Low | HS High | Differential-0 | N/A, Note 1 | N/A, Note 1 | | HS-1 | HS High | HS Low | Differential-1 | N/A, Note 1 | N/A, Note 1 | | LP-00 | LP Low | LP Low | N/A | Bridge | Space | | LP-01 | LP Low | LP High | N/A | HS-Rqst | Mark-0 | | LP-10 | LP High | LP Low | N/A | LP-Rqst | Mark-1 | | LP-11 | LP High | LP High | N/A | Stop | N/A, Note 2 |
Note: 注意:
  1. During High-Speed transmission the Low-Power Receivers observe LP-00 on the Lines.
    在高速傳輸期間,低功耗接收器在信號線上觀察到 LP-00。
  2. If LP-11 occurs during Escape mode the Lane returns to Stop state (Control Mode LP-11).
    如果在逃生模式下發生 LP-11,車道將返回停止狀態(控制模式 LP-11)。

6.3 Operating Modes: Control, High-Speed, and Escape
6.3 操作模式:控制、高速和逃逸

During normal operation a Data Lane will be either in Control or High-Speed mode. High-Speed Data transmission happens in bursts and starts from and ends at a Stop state (LP-11), which is by definition in Control mode. The Lane is only in High-Speed mode during Data bursts. The sequence to enter High-Speed mode is: LP-11, LP-01, LP-00 at which point the Data Lane remains in High-Speed mode until a LP-11 is received. The Escape mode can only be entered via a request within Control mode. The Data Lane shall always exit Escape mode and return to Control mode after detection of a Stop state. If not in High-Speed or Escape mode the Data Lane shall stay in Control mode. For Data Lanes and for Clock Lanes the Stop state serves as general standby state and may last for any period of time > T LPx > T LPx  > T_("LPx ")>T_{\text {LPx }}. Possible events starting from the Stop state are High-Speed Data Transmission request (LP-11, LP-01, LP-00), Escape mode request (LP-11, LP-10, LP-00, LP-01, LP-00) or Turnaround request (LP-11, LP-10, LP-00, LP-10, LP-00).
在正常操作中,數據通道將處於控制模式或高速模式。高速數據傳輸以突發方式進行,並從停止狀態(LP-11)開始和結束,根據定義,這是控制模式。通道僅在數據突發期間處於高速模式。進入高速模式的序列為:LP-11,LP-01,LP-00,此時數據通道將保持在高速模式,直到接收到 LP-11。逃逸模式只能通過控制模式中的請求進入。數據通道在檢測到停止狀態後,應始終退出逃逸模式並返回控制模式。如果不在高速或逃逸模式中,數據通道將保持在控制模式。對於數據通道和時鐘通道,停止狀態作為一般待機狀態,並且可以持續任何時間 > T LPx > T LPx  > T_("LPx ")>T_{\text {LPx }} 。從停止狀態開始的可能事件包括高速數據傳輸請求(LP-11,LP-01,LP-00)、逃逸模式請求(LP-11,LP-10,LP-00,LP-01,LP-00)或轉向請求(LP-11,LP-10,LP-00,LP-10,LP-00)。

6.4 High-Speed Data Transmission
6.4 高速數據傳輸

High-Speed Data Transmission occurs in bursts. To aid receiver synchronization, data bursts shall be extended on the transmitter side with a leader and trailer sequence and shall be eliminated on the receiver side. These leader and trailer sequences can therefore only be observed on the transmission lines.
高速數據傳輸以突發方式進行。為了幫助接收器同步,數據突發應在發射器端用前導和尾隨序列進行擴展,並在接收器端消除這些序列。因此,這些前導和尾隨序列只能在傳輸線上觀察到。
Transmission starts from, and ends with, a Stop state. During the intermediate time between bursts a Data Lane shall remain in the Stop state, unless a Turnaround or Escape request is presented on the Lane. During a HS Data Burst the Clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave side.
傳輸從停止狀態開始,並以停止狀態結束。在突發之間的中間時間,數據通道應保持在停止狀態,除非在通道上提出了轉換或逃逸請求。在高速度數據突發期間,時鐘通道應處於高速模式,為從屬端提供 DDR 時鐘。

6.4.1 Burst Payload Data
6.4.1 突發有效載荷數據

The payload data of a burst shall always represent an integer number of payload data bytes with a minimum length of one byte. Note that for short bursts the Start and End overhead consumes much more time than the actual transfer of the payload data. There is no maximum number of bytes implied by the PHY. However, in the PHY there is no autonomous way of error recovery during a HS data burst and the practical BER will not be zero. Therefore, it is important to consider for every individual protocol what the best choice is for maximum burst length.
突發的有效載荷數據應始終表示一個整數數量的有效載荷數據字節,最小長度為一個字節。請注意,對於短突發,開始和結束的開銷消耗的時間遠遠超過實際的有效載荷數據傳輸。PHY 並未暗示最大字節數。然而,在 PHY 中,HS 數據突發期間沒有自動錯誤恢復的方法,實際的比特錯誤率不會為零。因此,對於每個單獨的協議,考慮最大突發長度的最佳選擇是很重要的。

6.4.2 Start-of-Transmission
6.4.2 傳輸開始

After a Transmit request, a Data Lane leaves the Stop state and prepares for High-Speed mode by means of a Start-of-Transmission (SoT) procedure. Table 3 describes the sequence of events on TX and RX side.
在傳輸請求之後,數據通道離開停止狀態,通過傳輸開始(SoT)程序準備進入高速模式。表 3 描述了 TX 和 RX 端的事件序列。
Table 3 Start-of-Transmission Sequence
表 3 傳輸開始序列
TX Side TX 端 RX Side RX 端
Drives Stop state (LP-11)
驅動器停止狀態 (LP-11)
Observes Stop state 觀察停止狀態
Drives HS-Rqst state (LP-01) for time TLPX
驅動 HS-Rqst 狀態 (LP-01) 於時間 TLPX

觀察從 LP-11 到 LP-01 的過渡情況
Observes transition from LP-11 to LP-01 on the
Lines
Observes transition from LP-11 to LP-01 on the Lines| Observes transition from LP-11 to LP-01 on the | | :--- | | Lines |
Drives Bridge state (LP-00) for time THS-PREPARE
驅動橋樑狀態 (LP-00) 於時間 THS-PREPARE

觀察從 LP-01 到 LP-00 的轉換,並在時間 TD-TERM-EN 之後啟用線路終止
Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN
Observes transition form LP-01 to LP-00 on the Lines, enables Line Termination after time TD-TERM-EN| Observes transition form LP-01 to LP-00 on the | | :--- | | Lines, enables Line Termination after time TD-TERM-EN |

同時啟用高速驅動程式並禁用低功耗驅動程式。
Enables High-Speed driver and disables Low-Power
drivers simultaneously.
Enables High-Speed driver and disables Low-Power drivers simultaneously.| Enables High-Speed driver and disables Low-Power | | :--- | | drivers simultaneously. |

啟用 HS-RX 並等待計時器 THS-SETTLE 到期,以忽略過渡效應
Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects
Enables HS-RX and waits for timer THS-SETTLE to expire in order to neglect transition effects| Enables HS-RX and waits for timer THS-SETTLE to | | :--- | | expire in order to neglect transition effects |
Drives HS-0 for a time THS-ZERO
驅動器 HS-0 持續時間 THS-ZERO
Starts looking for Leader-Sequence
開始尋找領導序列

在識別到領導序列 'O11101' 時進行同步
Synchronizes upon recognition of Leader Sequence
'O11101'
Synchronizes upon recognition of Leader Sequence 'O11101'| Synchronizes upon recognition of Leader Sequence | | :--- | | 'O11101' |
on a rising Clock edge
在上升時鐘邊緣
TX Side RX Side Drives Stop state (LP-11) Observes Stop state Drives HS-Rqst state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the Lines" Drives Bridge state (LP-00) for time THS-PREPARE "Observes transition form LP-01 to LP-00 on the Lines, enables Line Termination after time TD-TERM-EN" "Enables High-Speed driver and disables Low-Power drivers simultaneously." "Enables HS-RX and waits for timer THS-SETTLE to expire in order to neglect transition effects" Drives HS-0 for a time THS-ZERO Starts looking for Leader-Sequence "Synchronizes upon recognition of Leader Sequence 'O11101'" on a rising Clock edge | TX Side | RX Side | | :--- | :--- | | Drives Stop state (LP-11) | Observes Stop state | | Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines | | Drives Bridge state (LP-00) for time THS-PREPARE | Observes transition form LP-01 to LP-00 on the <br> Lines, enables Line Termination after time TD-TERM-EN | | Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. | Enables HS-RX and waits for timer THS-SETTLE to <br> expire in order to neglect transition effects | | Drives HS-0 for a time THS-ZERO | Starts looking for Leader-Sequence | | | Synchronizes upon recognition of Leader Sequence <br> 'O11101' | | on a rising Clock edge | |

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6.4.3 End-of-Transmission
6.4.3 傳輸結束

TX Side TX 端 RX Side RX 端
Completes Transmission of payload data
完成有效載荷數據的傳輸
Receives payload data 接收有效載荷數據

在最後一個有效載荷數據位之後立即切換差分狀態,並保持該狀態一段時間 THS-TRAIL
Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL
Toggles differential state immediately after last payload data bit and keeps that state for a time THS-TRAIL| Toggles differential state immediately after last | | :--- | | payload data bit and keeps that state for a time | | THS-TRAIL |

禁用 HS-TX,啟用 LP-TX,並驅動停止狀態 (LP-11) 持續時間 THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables the LP-TX, and drives | | :--- | | Stop state (LP-11) for a time THS-EXIT |

檢測離開 LP-00 狀態並進入停止狀態 (LP-11) 的線路並禁用終止
Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination
Detects the Lines leaving LP-00 state and entering Stop state (LP-11) and disables Termination| Detects the Lines leaving LP-00 state and entering | | :--- | | Stop state (LP-11) and disables Termination |

忽略上個時期的 THS-SKIP 位元以隱藏過渡效果
Neglect bits of last period THS-SKIP to hide transition
effects
Neglect bits of last period THS-SKIP to hide transition effects| Neglect bits of last period THS-SKIP to hide transition | | :--- | | effects |

檢測有效數據中的最後過渡,確定最後有效數據字節並跳過尾部序列
Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence
Detect last transition in valid Data, determine last valid Data byte and skip trailer sequence| Detect last transition in valid Data, determine last | | :--- | | valid Data byte and skip trailer sequence |
TX Side RX Side Completes Transmission of payload data Receives payload data "Toggles differential state immediately after last payload data bit and keeps that state for a time THS-TRAIL" "Disables the HS-TX, enables the LP-TX, and drives Stop state (LP-11) for a time THS-EXIT" "Detects the Lines leaving LP-00 state and entering Stop state (LP-11) and disables Termination" "Neglect bits of last period THS-SKIP to hide transition effects" "Detect last transition in valid Data, determine last valid Data byte and skip trailer sequence"| TX Side | RX Side | | :--- | :--- | | Completes Transmission of payload data | Receives payload data | | Toggles differential state immediately after last <br> payload data bit and keeps that state for a time <br> THS-TRAIL | | | Disables the HS-TX, enables the LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines leaving LP-00 state and entering <br> Stop state (LP-11) and disables Termination | | | Neglect bits of last period THS-SKIP to hide transition <br> effects | | | Detect last transition in valid Data, determine last <br> valid Data byte and skip trailer sequence |

6.4.4 HS Data Transmission Burst
6.4.4 HS 數據傳輸突發

At the end of a Data Burst, a Data Lane leaves High-Speed Transmission mode and enters the Stop state by means of an End-of-Transmission (EoT) procedure. Table 4 shows a possible sequence of events during the EoT procedure. Note, EoT processing may be handled by the protocol or by the D-PHY.
在數據突發結束時,數據通道離開高速傳輸模式,通過結束傳輸(EoT)程序進入停止狀態。表 4 顯示了 EoT 程序中可能的事件序列。請注意,EoT 處理可以由協議或 D-PHY 處理。
Table 4 End-of-Transmission Sequence
表 4 傳輸結束序列
Figure 14 shows the sequence of events during the transmission of a Data Burst. Transmission can be started and ended independently for any Lane by the protocol. However, for most applications the Lanes will start synchronously but may end at different times due to an unequal amount of transmitted bytes per Lane. The handshake with the protocol-layer is described in Annex A.
圖 14 顯示了數據突發傳輸過程中的事件序列。根據協議,任何通道的傳輸可以獨立開始和結束。然而,對於大多數應用來說,通道將同步開始,但由於每個通道傳輸的字節數不等,可能會在不同的時間結束。與協議層的握手在附錄 A 中描述。

Figure 14 High-Speed Data Transmission in Bursts
圖 14 高速數據突發傳輸

Figure 15 shows the state machine for High-Speed data transmission that is described in Table 5.
圖 15 顯示了表 5 中描述的高速數據傳輸的狀態機。

Figure 15 TX and RX State Machines for High-Speed Data Transmission
圖 15 高速數據傳輸的 TX 和 RX 狀態機

Table 5 High-Speed Data Transmission State Machine Description
表 5 高速數據傳輸狀態機描述
State 
 線條狀態
Line
Condition/State
Line Condition/State| Line | | :---: | | Condition/State |
Exit State 退出狀態 Exit Conditions 退出條件
TX-Stop Transmit LP-11 傳輸 LP-11 TX-HS-Rqst

高速度傳輸協議的要求
On request of Protocol for High-Speed
Transmission
On request of Protocol for High-Speed Transmission| On request of Protocol for High-Speed | | :--- | | Transmission |
TX-HS-Rqst Transmit LP-01 傳輸 LP-01 TX-HS-Prpr End of timed interval TLPX
結束計時區間 TLPX
TX-HS-Prpr Transmit LP-00 傳輸 LP-00 TX-HS-Go End of timed interval THS-PREPARE
定時區間結束 THS-PREPARE
TX-HS-Go Transmit HS-0 傳輸 HS-0 TX-HS-Sync End of timed interval THS-zERO
結束計時區間 THS-zERO
TX-HS-Sync

傳輸序列 HS-00011101
Transmit
sequence
HS-00011101
Transmit sequence HS-00011101| Transmit | | :--- | | sequence | | HS-00011101 |
TX-HS-0 After Sync sequence if first payload data bit is 0
在同步序列之後,如果第一個有效載荷數據位是 0
TX-HS-1 After Sync sequence if first payload data bit is 1
在同步序列之後,如果第一個有效載荷數據位是 1
TX-HS-0 Transmit HS-0 傳輸 HS-0 TX-HS-0 Send another HS-0 bit after a HS-0 bit
在 HS-0 位元之後再發送一個 HS-0 位元
TX-HS-1 Send a HS-1 bit after a HS-0 bit
在 HS-0 位元之後發送一個 HS-1 位元
TX-HS-1 Transmit HS-1 傳輸 HS-1 TX-HS-0 Send a HS-1 bit after a HS-0 bit
在 HS-0 位元之後發送一個 HS-1 位元
TX-HS-1 Send another HS-1 bit after a HS-1
在一個 HS-1 之後發送另一個 HS-1 位元
Trail-HS-0 Last payload bit is HS-1, trailer sequence is HS-0
最後的有效載荷位元是 HS-1,尾部序列是 HS-0
Trail-HS-0 Transmit HS-0 傳輸 HS-0 TX-Stop End of timed interval THS-TRAlL
結束計時區間 THS-TRAlL
Trail-HS-1 Transmit HS-1 傳輸 HS-1 TX-Stop End of timed interval THS-TRAlL
結束計時區間 THS-TRAlL
RX-Stop Receive LP-11 接收 LP-11 RX-HS-Rqst Line transition to LP-01
線路過渡到 LP-01
RX- HS-Rqst Receive LP-01 接收 LP-01 RX-HS-Prpr Line transition to LP-00
線路過渡到 LP-00
State "Line Condition/State" Exit State Exit Conditions TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol for High-Speed Transmission" TX-HS-Rqst Transmit LP-01 TX-HS-Prpr End of timed interval TLPX TX-HS-Prpr Transmit LP-00 TX-HS-Go End of timed interval THS-PREPARE TX-HS-Go Transmit HS-0 TX-HS-Sync End of timed interval THS-zERO TX-HS-Sync "Transmit sequence HS-00011101" TX-HS-0 After Sync sequence if first payload data bit is 0 TX-HS-1 After Sync sequence if first payload data bit is 1 TX-HS-0 Transmit HS-0 TX-HS-0 Send another HS-0 bit after a HS-0 bit TX-HS-1 Send a HS-1 bit after a HS-0 bit TX-HS-1 Transmit HS-1 TX-HS-0 Send a HS-1 bit after a HS-0 bit TX-HS-1 Send another HS-1 bit after a HS-1 Trail-HS-0 Last payload bit is HS-1, trailer sequence is HS-0 Trail-HS-0 Transmit HS-0 TX-Stop End of timed interval THS-TRAlL Trail-HS-1 Transmit HS-1 TX-Stop End of timed interval THS-TRAlL RX-Stop Receive LP-11 RX-HS-Rqst Line transition to LP-01 RX- HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00| State | Line <br> Condition/State | Exit State | Exit Conditions | | :--- | :--- | :--- | :--- | | TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol for High-Speed <br> Transmission | | TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval TLPX | | TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval THS-PREPARE | | TX-HS-Go | Transmit HS-0 | TX-HS-Sync | End of timed interval THS-zERO | | TX-HS-Sync | Transmit <br> sequence <br> HS-00011101 | TX-HS-0 | After Sync sequence if first payload data bit is 0 | | | | TX-HS-1 | After Sync sequence if first payload data bit is 1 | | TX-HS-0 | Transmit HS-0 | TX-HS-0 | Send another HS-0 bit after a HS-0 bit | | | | TX-HS-1 | Send a HS-1 bit after a HS-0 bit | | TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-1 bit after a HS-0 bit | | | | TX-HS-1 | Send another HS-1 bit after a HS-1 | | | | Trail-HS-0 | Last payload bit is HS-1, trailer sequence is HS-0 | | Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval THS-TRAlL | | Trail-HS-1 | Transmit HS-1 | TX-Stop | End of timed interval THS-TRAlL | | RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 | | RX- HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
State 
 線條狀態
Line
Condition/State
Line Condition/State| Line | | :---: | | Condition/State |
Exit State 退出狀態 Exit Conditions 退出條件
RX-HS- Prpr Receive LP-00 接收 LP-00 RX-HS-Term End of timed interval TD-TERM-EN
定時區間結束 TD-TERM-EN
RX-HS-Term Receive LP-00 接收 LP-00 RX-HS-Sync End of timed interval THS-SETTLE
定時區間結束 THS-SETTLE
RX-HS-Sync

接收 HS 序列...00000011101
Receive HS
sequence
...00000011101
Receive HS sequence ...00000011101| Receive HS | | :--- | | sequence | | ...00000011101 |
RX-HS-0

在 HS 流中找到合適的匹配(如果未使用去偏校準功能,則允許任何單個位元錯誤),以下位元為有效載荷數據。
Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data.
Proper match found (any single bit error allowed if deskew calibration feature is not used) for Sync sequence in HS stream, the following bits are payload data.| Proper match found (any single bit error allowed if | | :--- | | deskew calibration feature is not used) for Sync | | sequence in HS stream, the following bits are | | payload data. |
RX-HS-1
RX-HS-0 Receive HS-0 接收 HS-0 RX-HS-0 Receive payload data bit or trailer bit
接收有效載荷數據位或尾部位
RX-HS-1
RX-HS-1 Receive HS-1 接收 HS-1 RX-HS-0 Receive payload data bit or trailer bit
接收有效載荷數據位或尾部位
RX-HS-1
RX-Stop Line transition to LP-11
線路過渡到 LP-11
State "Line Condition/State" Exit State Exit Conditions RX-HS- Prpr Receive LP-00 RX-HS-Term End of timed interval TD-TERM-EN RX-HS-Term Receive LP-00 RX-HS-Sync End of timed interval THS-SETTLE RX-HS-Sync "Receive HS sequence ...00000011101" RX-HS-0 "Proper match found (any single bit error allowed if deskew calibration feature is not used) for Sync sequence in HS stream, the following bits are payload data." RX-HS-1 RX-HS-0 Receive HS-0 RX-HS-0 Receive payload data bit or trailer bit RX-HS-1 RX-HS-1 Receive HS-1 RX-HS-0 Receive payload data bit or trailer bit RX-HS-1 RX-Stop Line transition to LP-11| State | Line <br> Condition/State | Exit State | Exit Conditions | | :--- | :--- | :--- | :--- | | RX-HS- Prpr | Receive LP-00 | RX-HS-Term | End of timed interval TD-TERM-EN | | RX-HS-Term | Receive LP-00 | RX-HS-Sync | End of timed interval THS-SETTLE | | RX-HS-Sync | Receive HS <br> sequence <br> ...00000011101 | RX-HS-0 | Proper match found (any single bit error allowed if <br> deskew calibration feature is not used) for Sync <br> sequence in HS stream, the following bits are <br> payload data. | | | | RX-HS-1 | | | RX-HS-0 | Receive HS-0 | RX-HS-0 | Receive payload data bit or trailer bit | | | | RX-HS-1 | | | RX-HS-1 | Receive HS-1 | RX-HS-0 | Receive payload data bit or trailer bit | | | | RX-HS-1 | | | | | RX-Stop | Line transition to LP-11 |
Note: 注意:
Stop states (TX-Stop, RX-Stop) have multiple valid exit states.
停止狀態(TX-停止,RX-停止)具有多個有效的退出狀態。

6.5 Bi-directional Data Lane Turnaround
6.5 雙向數據通道轉換

The transmission direction of a bi-directional Data Lane can be swapped by means of a Link Turnaround procedure. This procedure enables information transfer in the opposite direction of the current direction. The procedure is the same for either a change from Forward-to-Reverse direction or Reverse-to-Forward direction. Notice that Master and Slave side shall not be changed by Turnaround. Link Turnaround shall be handled completely in Control mode. Table 6 lists the sequence of events during Turnaround.
雙向數據通道的傳輸方向可以通過鏈路轉換程序進行切換。此程序使信息能夠以與當前方向相反的方向進行傳輸。無論是從前向轉為反向還是從反向轉為前向,程序都是相同的。請注意,主端和從端在轉換過程中不應改變。鏈路轉換應完全在控制模式下處理。表 6 列出了轉換過程中的事件序列。
Table 6 Link Turnaround Sequence
表 6 連結周轉序列
Initial TX Side = Final RX Side
初始 TX 端 = 最終 RX 端
Initial RX Side = Final TX Side
初始 RX 端 = 最終 TX 端
Drives Stop state (LP-11)
驅動器停止狀態 (LP-11)
Observes Stop state 觀察停止狀態
Drives LP-Rqst state (LP-10) for a time TLPX
驅動 LP-Rqst 狀態 (LP-10) 持續時間 TLPX
Observes transition from LP-11 to LP-10 states
觀察從 LP-11 到 LP-10 狀態的過渡
Drives Bridge state (LP-00) for a time T TPX
驅動橋狀態 (LP-00) 持續時間 T TPX
Observes transition from LP-10 to LP-00 states
觀察從 LP-10 到 LP-00 狀態的過渡
Drives LP-10 for a time T TPX
驅動器 LP-10 持續時間 T TPX
Observes transition from LP-00 to LP-10 states
觀察從 LP-00 到 LP-10 狀態的過渡
Drives Bridge state (LP-00) for a time TTA-GO
驅動橋樑狀態 (LP-00) 持續時間 TTA-GO

觀察從 LP-10 到橋接狀態的過渡,並等待一段時間 TAA-SURE。在正確完成此超時後,這一方知道它已經掌控。
Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control.
Observes the transition from LP-10 to Bridge state and waits for a time TAA-SURE. After correct completion of this time-out this side knows it is in control.| Observes the transition from LP-10 to Bridge state | | :--- | | and waits for a time TAA-SURE. After correct | | completion of this time-out this side knows it is in | | control. |

停止駕駛線路,並使用其 LP-RX 觀察線路狀態,以便查看確認。
Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement.
Stops driving the Lines and observes the Line states with its LP-RX in order to see an acknowledgement.| Stops driving the Lines and observes the Line states | | :--- | | with its LP-RX in order to see an acknowledgement. |
Drives Bridge state (LP-00) for a period TTA-GET
驅動橋樑狀態 (LP-00) 持續時間 TTA-GET
Drives LP-10 for a period TLPX
驅動器 LP-10 持續時間 TLPX

觀察 LP-10 在線上,解釋為承認對方確實已經掌控。等待停止狀態完成周轉程序。
Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure.
Observes LP-10 on the Lines, interprets this as acknowledge that the other side has indeed taken control. Waits for Stop state to complete Turnaround procedure.| Observes LP-10 on the Lines, interprets this as | | :--- | | acknowledge that the other side has indeed taken | | control. Waits for Stop state to complete Turnaround | | procedure. |
Initial TX Side = Final RX Side Initial RX Side = Final TX Side Drives Stop state (LP-11) Observes Stop state Drives LP-Rqst state (LP-10) for a time TLPX Observes transition from LP-11 to LP-10 states Drives Bridge state (LP-00) for a time T TPX Observes transition from LP-10 to LP-00 states Drives LP-10 for a time T TPX Observes transition from LP-00 to LP-10 states Drives Bridge state (LP-00) for a time TTA-GO "Observes the transition from LP-10 to Bridge state and waits for a time TAA-SURE. After correct completion of this time-out this side knows it is in control." "Stops driving the Lines and observes the Line states with its LP-RX in order to see an acknowledgement." Drives Bridge state (LP-00) for a period TTA-GET Drives LP-10 for a period TLPX "Observes LP-10 on the Lines, interprets this as acknowledge that the other side has indeed taken control. Waits for Stop state to complete Turnaround procedure." | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side | | :--- | :--- | | Drives Stop state (LP-11) | Observes Stop state | | Drives LP-Rqst state (LP-10) for a time TLPX | Observes transition from LP-11 to LP-10 states | | Drives Bridge state (LP-00) for a time T TPX | Observes transition from LP-10 to LP-00 states | | Drives LP-10 for a time T TPX | Observes transition from LP-00 to LP-10 states | | Drives Bridge state (LP-00) for a time TTA-GO | Observes the transition from LP-10 to Bridge state <br> and waits for a time TAA-SURE. After correct <br> completion of this time-out this side knows it is in <br> control. | | Stops driving the Lines and observes the Line states <br> with its LP-RX in order to see an acknowledgement. | Drives Bridge state (LP-00) for a period TTA-GET | | | Drives LP-10 for a period TLPX | | Observes LP-10 on the Lines, interprets this as <br> acknowledge that the other side has indeed taken <br> control. Waits for Stop state to complete Turnaround <br> procedure. | |
Initial TX Side = Final RX Side
初始 TX 端 = 最終 RX 端
Initial RX Side = Final TX Side
初始 RX 端 = 最終 TX 端
Observes transition to Stop state (LP-11) on the
觀察到轉換到停止狀態(LP-11)在
Lines, interprets this as Turnaround completion