Further technical changes to this document are expected as work continues in the Phy Working Group. 隨著物理工作組的持續工作，預期對本文件將進一步進行技術變更。
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The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI ^(®){ }^{\circledR}. The material contained herein is provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. 本文件所含材料並不構成對任何作者或開發者擁有或控制的知識產權的明示或暗示的許可。所含材料以“現狀”提供，並在適用法律允許的最大範圍內，該材料以“現狀”及“所有缺陷”提供，作者和開發者以及 MIPI 特此聲明所有其他保證和條件，無論是明示、暗示或法定的，包括但不限於任何（如有）暗示的保證、商業適銷性、特定用途的適用性、回應的準確性或完整性、結果、專業努力的缺乏、病毒的缺乏以及疏忽的缺乏。
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. 本文件中包含的所有材料均受著作權法保護，未經 MIPI 聯盟事先書面許可，不得以任何方式複製、重新出版、分發、傳輸、展示、廣播或以其他方式利用。MIPI、MIPI 聯盟及其點狀彩虹拱門和所有相關商標、商號及其他智慧財產均為 MIPI 聯盟的專有財產，未經其事先書面許可不得使用。
Date Version Description
2016-03-08 V2.0 Initial Board adopted release.| Date | Version | Description |
| :---: | :--- | :--- |
| $2016-03-08$ | V2.0 | Initial Board adopted release. |
1 Introduction 1 介紹
This specification provides a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized with very low power consumption. 此規範提供了一種靈活、低成本的高速串行介面解決方案，用於移動設備內部組件之間的通信互連。傳統上，這些介面是低位速率的 CMOS 平行匯流排，因為電磁干擾的原因，邊緣變化緩慢。D-PHY 解決方案使介面帶寬得以顯著擴展，以支持更先進的應用。D-PHY 解決方案可以實現非常低的功耗。
1.1 Scope 1.1 範圍
The scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to be applied by MIPI Alliance application or protocol level specifications. This includes the physical interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken together are known as D-PHY. 本文件的範圍是指定由 MIPI 聯盟應用或協議層級規範所應用的高速源同步介面的最低層。這包括物理介面、電氣介面、低級時序和 PHY 層協議。這些功能區域合在一起被稱為 D-PHY。
The D-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Any other use of the D-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors. D-PHY 規範必須始終與引用此規範的更高層 MIPI 規範結合使用。除非事先獲得 MIPI 董事會的批准，否則嚴禁以其他方式使用 D-PHY 規範。
The following topics are outside the scope of this document: 以下主題不在本文件的範疇內：
Explicit specification of signals of the clock generator unit. Of course, the D-PHY specification does implicitly require some minimum performance from the clock signals. Intentionally, only the behavior on the interface pins is constrained. Therefore, the clock generation unit is excluded from this specification, and will be a separate functional unit that provides the required clock signals to the D-PHY in order to meet the specification. This allows all kinds of implementation trade-offs as long as these do not violate this specification. More information can be found in Section 5. 時鐘產生單元的信號明確規範。當然，D-PHY 規範隱含地要求時鐘信號具備某些最低性能。故意地，僅對介面引腳的行為進行約束。因此，時鐘產生單元不在此規範之內，將作為一個獨立的功能單元，為 D-PHY 提供所需的時鐘信號，以滿足規範。這允許各種實現上的權衡，只要這些不違反此規範。更多信息可以在第 5 節找到。
Test modes, patterns, and configurations. Obviously testability is very important, but because the items to test are mostly application specific or implementation related, the specification of tests is deferred to either the higher layer specifications or the product specification. Furthermore MIPI D-PHY compliance testing is not included in this specification. 測試模式、模式和配置。顯然，測試性非常重要，但因為要測試的項目大多是應用特定或實現相關的，因此測試的規範被推遲到更高層的規範或產品規範。此外，MIPI D-PHY 合規性測試不包括在此規範中。
Procedure to resolve contention situations. The D-PHY contains several mechanisms to detect Link contention. However, certain contention situations can only be detected at higher levels and are therefore not included in this specification. 解決爭用情況的程序。D-PHY 包含幾種檢測鏈路爭用的機制。然而，某些爭用情況只能在更高的層次上檢測到，因此未包含在本規範中。
Ensure proper operation of a connection between different Lane Module types. There are several different Lane Module types to optimally support the different functional requirements of several applications. This means that next to some base-functionality there are optional features which can be included or excluded. This specification only ensures correct operation for a connection between matched Lane Modules types, which means: Modules that support the same features and have complementary functionality. In case the two sides of the Lane are not the same type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the Lane Module(s) that the provided additional functionality does not corrupt operation. This can be easiest accomplished if the additional functionality can be disabled by other means independent of the MIPI D-PHY interface, such that the Lane Modules behave as if they were the same type. 確保不同通道模組類型之間的連接正常運作。有幾種不同的通道模組類型，以最佳支持多個應用的不同功能需求。這意味著除了某些基本功能外，還有可選的功能可以包含或排除。本規範僅確保匹配的通道模組類型之間的連接正常運作，這意味著：支持相同功能並具有互補功能的模組。如果通道的兩側不是相同類型，並且這些模組應該正常運作，則應由通道模組的製造商確保所提供的附加功能不會損害運作。如果附加功能可以通過其他獨立於 MIPI D-PHY 介面的方式禁用，則可以最輕鬆地實現這一點，使通道模組的行為如同它們是相同類型。
ESD protection level of the IO. The required level will depend on a particular application environment and product type. IO 的 ESD 保護級別。所需的級別將取決於特定的應用環境和產品類型。
Exact Bit-Error-Rate (BER) value. The actual value of the achieved BER depends on the total system integration and the hostility of the environment. Therefore, it is impossible to specify a BER for individual parts of the Link. This specification allows for implementations with a BER < 10^(-12)<10^{-12}. 精確的位元錯誤率（BER）值。實際達成的 BER 值取決於整體系統整合和環境的惡劣程度。因此，無法為鏈路的各個部分指定 BER。此規範允許實現 BER < 10^(-12)<10^{-12} 。
Specification of the PHY-Protocol Interface. The D-PHY specification includes a PHY-Protocol Interface (PPI) annex that provides one possible solution for this interface. This annex is limited to the essential signals for normal operation in order to clarify the kind of signals needed at this PHY 協議介面的規範。D-PHY 規範包括一個 PHY 協議介面（PPI）附錄，提供了這個介面的一種可能解決方案。這個附錄僅限於正常操作所需的基本信號，以便澄清在此所需的信號類型。
interface. For power reasons this interface will be internal for most applications. Practical implementations may be different without being inconsistent with the D-PHY specification. 介面。出於功率原因，這個介面對於大多數應用將是內部的。實際實現可能會有所不同，但不會與 D-PHY 規範不一致。
Implementations. This specification is intended to restrict the implementation as little as possible. Various sections of this specification use block diagrams or example circuits to illustrate the concept and are not in any way claimed to be the preferred or required implementation. Only the behavior on the D-PHY interface pins is normative. 實現。此規範旨在盡可能少地限制實現。此規範的各個部分使用方塊圖或示例電路來說明概念，並不以任何方式聲稱是首選或必需的實現。只有 D-PHY 介面引腳上的行為是規範性的。
D-PHY Specification evolution is primarily driven by the need to achieve higher data rates and better efficiency, while at the same time respecting backward compatibility. In this process the previous version of the specification is taken and modifications are added, without compromising backward compatibility. Each new version of the specification that is derived both preserves all the specification components of the previous version, and adds the new changes. Due to technology evolution, some parameters are changed to optimize for newer technologies. D-PHY 規範的演變主要是由於需要實現更高的數據傳輸速率和更好的效率，同時尊重向後兼容性。在這個過程中，會採用先前版本的規範並添加修改，而不會妥協向後兼容性。每個衍生的新版本規範都保留了前一版本的所有規範組件，並添加了新的變更。由於技術的演變，一些參數被更改以優化新技術。
It is recommended to always follow the latest version of the D-PHY Specification, irrespective of the targeted data rate. The product data sheet should mention both the targeted D-PHY Specification version and data rates. This will enable the system integrator to make proper decisions to achieve interoperability goals. 建議始終遵循最新版本的 D-PHY 規範，無論目標數據速率為何。產品數據表應提及目標的 D-PHY 規範版本和數據速率。這將使系統集成商能夠做出適當的決策，以實現互操作性目標。
Regulatory compliance methods are not within the scope of this document. It is the responsibility of product manufacturers to ensure that their designs comply with all applicable regulatory requirements. 本文件不包括合規性方法。產品製造商有責任確保其設計符合所有適用的法規要求。
1.2 Purpose 1.2 目的
The D-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface specifications for mobile device such as, but not limited to, camera, display and unified protocol interfaces. D-PHY 規範被製造商用來設計符合 MIPI 聯盟介面規範的移動設備產品，例如但不限於相機、顯示器和統一協議介面。
Implementing this specification reduces the time-to-market and design cost of mobile devices by standardizing the interface between products from different manufacturers. In addition, richer feature sets requiring high bit rates can be realized by implementing this specification. Finally, adding new features to mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications. 實施此規範可通過標準化不同製造商產品之間的介面，減少行動裝置的上市時間和設計成本。此外，通過實施此規範，可以實現需要高比特率的更豐富功能集。最後，由於 MIPI 聯盟規範的可擴展性，為行動裝置添加新功能變得更加簡單。
2 Terminology 2 術語
2.1 Use of Special Terms 2.1 特殊術語的使用
The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the words “shall”, “should”, “may”, and “can” in the development of documentation, as follows: MIPI 聯盟已採納 IEEE 標準風格手冊第 13.1 節，該節規定在文件開發中使用“應”、“應該”、“可以”和“能夠”這些詞語，如下所示：
The word shall is used to indicate mandatory requirements strictly to be followed in order to conform to the Specification and from which no deviation is permitted (shall equals is required to). “shall”這個詞用來表示必須嚴格遵循的強制性要求，以符合規範，並且不允許任何偏離（shall 等於必須）。
The use of the word must is deprecated and shall not be used when stating mandatory requirements; must is used only to describe unavoidable situations. 使用“必須”一詞已被棄用，並且在陳述強制性要求時不得使用；“必須”僅用於描述不可避免的情況。
The use of the word will is deprecated and shall not be used when stating mandatory requirements; will is only used in statements of fact. 使用“will”一詞已被棄用，並且在陳述強制性要求時不得使用；“will”僅用於事實陳述中。
The word should is used to indicate that among several possibilities one is recommended as particularly suitable, without mentioning or excluding others; or that a certain course of action is preferred but not necessarily required; or that (in the negative form) a certain course of action is deprecated but not prohibited (should equals is recommended that). “應該”這個詞用來表示在幾種可能性中，推薦其中一種作為特別合適的選擇，而不提及或排除其他選擇；或者表示某種行動方案是首選，但不一定是必需的；或者在否定形式中，表示某種行動方案是不被贊成的，但並不被禁止（應該等於建議這樣做）。
The word may is used to indicate a course of action permissible within the limits of the Specification (may equals is permitted to). “may”這個詞用來表示在規範的範圍內允許的行動（may 等於被允許）。
The word can is used for statements of possibility and capability, whether material, physical, or causal (can equals is able to). 「can」這個詞用於表示可能性和能力的陳述，無論是物質的、物理的還是因果的（can 等於能夠）。
All sections are normative, unless they are explicitly indicated to be informative. 所有部分都是規範性的，除非明確指示為資訊性。
2.2 Definitions 2.2 定義
Bi-directional: A single Data Lane that supports communication in both the Forward and Reverse directions. 雙向：一個單一數據通道，支持前向和反向的通信。
DDR Clock: Half rate clock used for dual-edged data transmission. DDR 時鐘：用於雙邊數據傳輸的半速時鐘。
D-PHY: The source synchronous PHY defined in this document. D-PHYs communicate on the order of 500Mbit//s500 \mathrm{Mbit} / \mathrm{s} hence the Roman numeral for 500 or “D.” D-PHY：本文件中定義的源同步 PHY。D-PHY 的通信速度約為 500Mbit//s500 \mathrm{Mbit} / \mathrm{s} ，因此羅馬數字為 500 或“D”。
Escape Mode: An optional mode of operation for Data Lanes that allows low bit-rate commands and data to be transferred at very low power. 逃逸模式：數據通道的一種可選操作模式，允許以非常低的功率傳輸低比特率的命令和數據。
Forward Direction: The signal direction is defined relative to the direction of the High-Speed DDR clock. Transmission from the side sending the clock to the side receiving the clock is the Forward direction. 前進方向：信號方向是相對於高速 DDR 時鐘的方向定義的。從發送時鐘的一側到接收時鐘的一側的傳輸是前進方向。
Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane Interconnects. Sometimes Lane is also used to denote interconnect only. A Lane can be used for either Data or Clock signal transmission. 通道：由兩個互補的通道模組通過雙線點對點通道互連進行通信。有時通道也用來僅表示互連。通道可以用於數據或時鐘信號傳輸。
Lane Interconnect: Two-line, point-to-point interconnect used for both differential High-Speed signaling and Low-Power, single-ended signaling. 通道互連：用於差分高速信號和低功耗單端信號的雙線點對點互連。
Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane. 車道模組：位於車道兩側的模組，用於駕駛和/或接收車道上的信號。
Line: An interconnect wire used to connect a driver to a receiver. Two Lines are required to create a Lane Interconnect. 用於將驅動器連接到接收器的互連線。創建通道互連需要兩條線。
Link: A connection between two devices containing one Clock Lane and at least one Data Lane. A Link consists of at least two PHYs and two Lane Interconnects. 鏈接：兩個設備之間的連接，包含一個時鐘通道和至少一個數據通道。鏈接由至少兩個 PHY 和兩個通道互連組成。
Master: The Master side of a Link is defined as the side that transmits the High-Speed Clock. The Master side transmits data in the Forward direction. 主控端：鏈路的主控端定義為傳輸高速時鐘的端。主控端以正向方向傳輸數據。
PHY: A functional block that implements the features necessary to communicate over the Lane Interconnect. A PHY consists of one Lane Module configured as a Clock Lane, one or more Lane Modules configured as Data Lanes and a PHY Adapter Layer. PHY：一個功能區塊，實現了在通道互連上進行通信所需的特性。PHY 由一個配置為時鐘通道的通道模組、一個或多個配置為數據通道的通道模組和一個 PHY 適配層組成。
PHY Adapter: A protocol layer that converts symbols from an APPI to the signals used by a specific PHY PPI. PHY 轉接器：一個協議層，將 APPI 的符號轉換為特定 PHY PPI 使用的信號。
PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a minimum of two Lanes, one Clock Lane and one or more Data Lanes. PHY 配置：一組代表可能鏈路的通道。PHY 配置至少由兩個通道組成，一個時鐘通道和一個或多個數據通道。
Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for Forward Direction. 反向方向：反向方向是前進方向的相反方向。請參閱前進方向的描述。
Slave: The Slave side of a Link is defined as the side that does not transmit the High-Speed Clock. The Slave side may transmit data in the Reverse direction. 從屬設備：鏈路的從屬設備端定義為不傳輸高速時鐘的那一側。從屬設備端可以以反向方向傳輸數據。
Turnaround: Reversing the direction of communication on a Data Lane. 轉向：在數據通道上反轉通信方向。
Unidirectional: A single Lane that supports communication in the Forward direction only. 單向：一條僅支持向前方向通信的單車道。
2.3 Abbreviations 2.3 縮寫
e.g. For example (Latin: exempli gratia) 例如 (拉丁文：exempli gratia)
i.e. That is (Latin: id est) 即是（拉丁文：id est）
2.4 Acronyms 2.4 縮寫詞
APPI
BER Bit Error Rate 比特錯誤率
CIL Control and Interface Logic CIL 控制與介面邏輯
DDR Double Data Rate DDR 雙倍數據速率
DUT
EMI
EoT
HS
HS-RX
HS-TX
IO
ISTO Industry Standards and Technology Organization ISTO 行業標準與技術組織
LP Low-Power: identifier for operation mode LP 低功耗：操作模式的識別碼
LP-CD Low-Power Contention Detector LP-CD 低功耗爭用檢測器
LPDT Low-Power Data Transmission LPDT 低功耗數據傳輸
LP-RX Low-Power Receiver (Large-Swing Single-Ended) LP-RX 低功耗接收器（大擺幅單端）
LP-TX Low-Power Transmitter (Large-Swing Single-Ended) LP-TX 低功耗發射器（大擺幅單端）
LPS Low-Power State(s) LPS 低功耗狀態
LSB Least Significant Bit LSB 最低有效位
Version 2.0 版本 2.0
Specification for D-PHY D-PHY 規範
23-Nov-2015
144
Mbps
Megabits per second 每秒兆位元
145
MSB
Most Significant Bit 最重要位元
146
PHY
Physical Layer 物理層
147
PLL
Phase-Locked Loop 相位鎖定迴路
148
PPI
PHY-Protocol Interface
149
RF
Radio Frequency 無線電頻率
150
RX
Receiver 接收器
151
SE
Single-Ended 單端
152
SoT
Start of Transmission 傳輸開始
153
TLIS
Transmission-Line Interconnect Structure: physical interconnect realization between Master 傳輸線互連結構：主控之間的物理互連實現
154
and Slave 和奴隸
155
TX
Transmitter 發射器
156
UI
Unit Interval, equal to the duration of any HS state on the Clock Lane 單位間隔，等於時鐘線上任何高電平狀態的持續時間
157
ULPS
Ultra-Low Power State 超低功耗狀態
Version 2.0 Specification for D-PHY
23-Nov-2015
144 Mbps Megabits per second
145 MSB Most Significant Bit
146 PHY Physical Layer
147 PLL Phase-Locked Loop
148 PPI PHY-Protocol Interface
149 RF Radio Frequency
150 RX Receiver
151 SE Single-Ended
152 SoT Start of Transmission
153 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master
154 and Slave
155 TX Transmitter
156 UI Unit Interval, equal to the duration of any HS state on the Clock Lane
157 ULPS Ultra-Low Power State| | Version 2.0 | Specification for D-PHY |
| :--- | :--- | :--- |
| | 23-Nov-2015 | |
| 144 | Mbps | Megabits per second |
| 145 | MSB | Most Significant Bit |
| 146 | PHY | Physical Layer |
| 147 | PLL | Phase-Locked Loop |
| 148 | PPI | PHY-Protocol Interface |
| 149 | RF | Radio Frequency |
| 150 | RX | Receiver |
| 151 | SE | Single-Ended |
| 152 | SoT | Start of Transmission |
| 153 | TLIS | Transmission-Line Interconnect Structure: physical interconnect realization between Master |
| 154 | | and Slave |
| 155 | TX | Transmitter |
| 156 | UI | Unit Interval, equal to the duration of any HS state on the Clock Lane |
| 157 | ULPS | Ultra-Low Power State |
3 References 3 參考文獻
[MIPI01] MIPI Alliance Specification for D-PHY, Version 1.0, MIPI Alliance, Inc., 22 September 2009. [MIPI01] MIPI 聯盟 D-PHY 規範，版本 1.0，MIPI 聯盟公司，2009 年 9 月 22 日。
[MIPI02] MIPI Alliance Specification for C-PHY, Version 1.0, MIPI Alliance, Inc., 7 October 2014. [MIPI02] MIPI 聯盟 C-PHY 規範，版本 1.0，MIPI 聯盟公司，2014 年 10 月 7 日。
4 D-PHY Overview 4 D-PHY 概述
D-PHY describes a source synchronous, high speed, low power, low cost PHY, especially suited for mobile applications. This D-PHY specification has been written primarily for the connection of camera and display applications to a host processor. Nevertheless, it can be applied to many other applications. It is envisioned that the same type of PHY will also be used in a dual-simplex configuration for interconnections in a more generic communication network. Operation and available data-rates for a Link are asymmetrical due to a master-slave relationship between the two sides of the Link. The asymmetrical design significantly reduces the complexity of the Link. Some features like bi-directional, half-duplex operation are optional. Exploiting this feature is attractive for applications that have asymmetrical data traffic requirements and when the cost of separate interconnects for a return channel is too high. While this feature is optional, it avoids mandatory overhead costs for applications that do not have return traffic requirements or want to apply physically distinct return communication channels. D-PHY 描述了一種源同步、高速、低功耗、低成本的 PHY，特別適合於移動應用。這個 D-PHY 規範主要是為了將相機和顯示應用連接到主處理器而編寫的。然而，它也可以應用於許多其他應用。預期同類型的 PHY 也將在雙簡單配置中用於更通用的通信網絡中的互連。由於鏈路兩側之間的主從關係，鏈路的操作和可用數據速率是不對稱的。不對稱設計顯著降低了鏈路的複雜性。一些特性，如雙向、半雙工操作是可選的。利用這一特性對於具有不對稱數據流量需求的應用是有吸引力的，尤其是在返回通道的單獨互連成本過高的情況下。雖然這一特性是可選的，但它避免了對於沒有返回流量需求或希望應用物理上不同的返回通信通道的應用的強制性開銷成本。
4.1 Summary of PHY Functionality 4.1 PHY 功能摘要
The D-PHY provides a synchronous connection between Master and Slave. A practical PHY Configuration consists of a clock signal and one or more data signals. The clock signal is unidirectional, originating at the Master and terminating at the Slave. The data signals can either be unidirectional or bi-directional depending on the selected options. For half-duplex operation, the reverse direction bandwidth is one-fourth of the forward direction bandwidth. Token passing is used to control the communication direction of the Link. D-PHY 提供了主設備和從設備之間的同步連接。實際的 PHY 配置由時鐘信號和一個或多個數據信號組成。時鐘信號是單向的，起源於主設備並終止於從設備。數據信號可以是單向或雙向，具體取決於所選擇的選項。對於半雙工操作，反向帶寬是正向帶寬的四分之一。令牌傳遞用於控制鏈路的通信方向。
The Link includes a High-Speed signaling mode for fast-data traffic and a Low-Power signaling mode for control purposes. Optionally, a Low-Power Escape mode can be used for low speed asynchronous data communication. High speed data communication appears in bursts with an arbitrary number of payload data bytes. 該鏈接包括一種高速信號模式，用於快速數據流量，以及一種低功耗信號模式，用於控制目的。可選擇使用低功耗逃逸模式進行低速異步數據通信。高速數據通信以突發形式出現，具有任意數量的有效載荷數據字節。
The PHY uses two wires per Data Lane plus two wires for the Clock Lane. This gives four wires for the minimum PHY configuration. In High-Speed mode each Lane is terminated on both sides and driven by a low-swing, differential signal. In Low-Power mode all wires are operated single-ended and non-terminated. For EMI reasons, the drivers for this mode shall be slew-rate controlled and current limited. PHY 使用每個數據通道兩根線，外加兩根時鐘通道的線。這樣最小的 PHY 配置就有四根線。在高速模式下，每個通道在兩側都有終端，並由低擺幅的差分信號驅動。在低功耗模式下，所有線路均為單端操作且不終端。出於電磁干擾的原因，該模式的驅動器應受限於斜率控制和電流限制。
The actual maximum achievable bit rate in High-Speed mode is determined by the performance of transmitter, receiver and interconnect implementations. Therefore, the maximum bit rate is not specified in this document. However, this specification is primarily intended to define a solution for a data rate range of 80 to 1500 Mbps per Lane without deskew calibration, up to 2500 Mbps with deskew calibration, and up to 4500 Mbps with equalization. When the implementation supports a data rate greater than 1500 Mbps , it shall also support deskew capability. When a Phy implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available. Although PHY Configurations are not limited to this range, practical constraints make it the most suitable range for the intended applications. For a fixed clock frequency, the available data capacity of a PHY Configuration can be increased by using more Data Lanes. Effective data throughput can be reduced by employing burst mode communication. The maximum data rate in Low-Power mode is 10 Mbps . 在高速模式下，實際可達到的最大比特率由發射器、接收器和互連實現的性能決定。因此，本文件中未指定最大比特率。然而，本規範主要旨在定義一種解決方案，適用於每條通道 80 至 1500 Mbps 的數據速率範圍，無需去偏校準，最高可達 2500 Mbps，並且在進行均衡時可達 4500 Mbps。當實現支持超過 1500 Mbps 的數據速率時，還必須支持去偏能力。當物理實現支持超過 2500 Mbps 的數據速率時，還必須支持均衡，並且應提供擴頻時鐘。雖然 PHY 配置不僅限於此範圍，但實際限制使其成為最適合的範圍，適用於預期的應用。對於固定的時鐘頻率，可以通過使用更多數據通道來增加 PHY 配置的可用數據容量。通過採用突發模式通信，有效數據吞吐量可能會降低。低功耗模式下的最大數據速率為 10 Mbps。
The features introduced by this specification (Spread Spectrum Clocking, Transmit Equalization, and Deskew) can be applied to any HS data rate. 本規範所引入的特性（擴頻時鐘、傳輸均衡和去偏移）可以應用於任何 HS 數據速率。
4.2 Mandatory Functionality 4.2 強制功能
All functionality that is specified in this document and which is not explicitly stated in Section 5.5 shall be implemented for all D-PHY configurations. 本文件中指定的所有功能，未在第 5.5 節中明確說明的，應適用於所有 D-PHY 配置。
5 Architecture 5 建築學
This section describes the internal structure of the PHY including its functions at the behavioral level. Furthermore, several possible PHY configurations are given. Each configuration can be considered as a suitable combination from a set of basic modules. 本節描述了 PHY 的內部結構，包括其在行為層面的功能。此外，還提供了幾種可能的 PHY 配置。每種配置可以被視為從一組基本模塊中選擇的合適組合。
5.1 Lane Modules 5.1 車道模組
A PHY configuration contains a Clock Lane Module and one or more Data Lane Modules. Each of these PHY Lane Modules communicates via two Lines to a complementary part at the other side of the Lane Interconnect. 一個 PHY 配置包含一個時鐘通道模組和一個或多個數據通道模組。這些 PHY 通道模組中的每一個通過兩條線與通道互連另一側的互補部分進行通信。
Each Lane Module consists of one or more differential High-Speed functions utilizing both interconnect wires simultaneously, one or more single-ended Low-Power functions operating on each of the interconnect wires individually, and control & interface logic. An overview of all functions is shown in Figure 1. HighSpeed signals have a low voltage swing, e.g. 200 mV , while Low-Power signals have a large swing, e.g. 1.2V. High-Speed functions are used for High-Speed Data transmission. The Low-Power functions are mainly used for Control, but have other, optional, use cases. The I/O functions are controlled by a Lane Control and Interface Logic block. This block interfaces with the Protocol and determines the global operation of the Lane Module. 每個通道模組由一個或多個差分高速功能組成，這些功能同時利用兩根互連線，還有一個或多個單端低功耗功能，分別在每根互連線上運作，以及控制和介面邏輯。所有功能的概述如圖 1 所示。高速信號具有低電壓擺幅，例如 200 毫伏，而低功耗信號則具有較大的擺幅，例如 1.2 伏。高速功能用於高速數據傳輸。低功耗功能主要用於控制，但也有其他可選的使用案例。I/O 功能由通道控制和介面邏輯區塊控制。該區塊與協議介面並確定通道模組的全局操作。
High-Speed functions include a differential transmitter (HS-TX) and a differential receiver (HS-RX). 高速功能包括差分發射器（HS-TX）和差分接收器（HS-RX）。
A Lane Module may contain a HS-TX, a HS-RX, or both. A HS-TX and a HS-RX within a single Lane Module are never enabled simultaneously during normal operation. An enabled High-Speed function shall terminate the Lane on its side of the Lane Interconnect as defined in Section 9.1.1 and Section 9.2.1. If a 一個通道模組可以包含一個 HS-TX、一個 HS-RX 或兩者皆有。在正常操作期間，單一通道模組內的 HS-TX 和 HS-RX 不會同時啟用。啟用的高速功能應根據第 9.1.1 節和第 9.2.1 節的定義，在通道互連的一側終止通道。若一個
High-Speed function in the Lane Module is not enabled then the function shall be put into a high impedance state. 如果車道模組中的高速功能未啟用，則該功能將進入高阻抗狀態。
Low-Power functions include single-ended transmitters (LP-TX), receivers (LP-RX) and Low-Power Contention-Detectors (LP-CD). Low-Power functions are always present in pairs as these are single-ended functions operating on each of the two interconnect wires individually. 低功耗功能包括單端發射器（LP-TX）、接收器（LP-RX）和低功耗競爭檢測器（LP-CD）。低功耗功能總是成對出現，因為這些是單端功能，分別在兩根互連線上運作。
Presence of High-Speed and Low-Power functions is correlated. That is, if a Lane Module contains a HSTX it shall also contain a LP-TX. A similar constraint holds for HS-RX and LP-RX. 高速度和低功耗功能的存在是相關的。也就是說，如果一個通道模組包含 HSTX，它也必須包含 LP-TX。HS-RX 和 LP-RX 也有類似的限制。
If a Lane Module containing a LP-RX is powered, that LP-RX shall always be active and continuously monitor line levels. A LP-TX shall only be enabled when driving Low-Power states. The LP-CD function is only required for bi-directional operation. If present, the LP-CD function is enabled to detect contention situations while the LP-TX is driving Low-Power states. The LP-CD checks for contention before driving a new state on the line except in ULPS. 如果包含 LP-RX 的通道模組通電，該 LP-RX 將始終處於活動狀態並持續監控線路電平。只有在驅動低功耗狀態時，LP-TX 才會啟用。LP-CD 功能僅在雙向操作時需要。如果存在，LP-CD 功能將啟用以檢測競爭情況，當 LP-TX 驅動低功耗狀態時。LP-CD 在驅動新狀態到線路之前檢查競爭情況，ULPS 除外。
The activities of LP-TX, HS-TX, and HS-RX in a single Lane Module are mutually exclusive, except for some short crossover periods. For detailed specification of the Line side Clock and Data signals, and the HS-TX, HS-RX, LP-TX, LP-RX and LP-CD functions, see Section 9 and Section 10. LP-TX、HS-TX 和 HS-RX 在單一通道模組中的活動是互斥的，除了某些短暫的交叉期間。關於線側時鐘和數據信號的詳細規範，以及 HS-TX、HS-RX、LP-TX、LP-RX 和 LP-CD 功能，請參見第 9 節和第 10 節。
For proper operation, the set of functions in the Lane Modules on both sides of the Lane Interconnect has to be matched. This means for each HS and LP transmit or receive function on one side of the Lane Interconnect, a complementary HS or LP receive or transmit function must be present on the other side. In addition, a Contention Detector is needed in any Lane Module that combines TX and RX functions. 為了正常運作，通道互連兩側的通道模組中的功能集必須匹配。這意味著在通道互連一側的每個 HS 和 LP 發送或接收功能，另一側必須存在一個互補的 HS 或 LP 接收或發送功能。此外，任何結合 TX 和 RX 功能的通道模組都需要一個爭用檢測器。
5.2 Master and Slave 5.2 主從
Each Link has a Master and a Slave side. The Master provides the High-Speed DDR Clock signal to the Clock Lane and is the main data source. The Slave receives the clock signal at the Clock Lane and is the main data sink. The main direction of data communication, from source to sink, is denoted as the Forward direction. Data communication in the opposite direction is called Reverse transmission. Only bi-directional Data Lanes can transmit in the Reverse direction. In all cases, the Clock Lane remains in the Forward direction, but bi-directional Data Lane(s) can be turned around, sourcing data from the Slave side. 每個連接都有主端和從端。主端向時鐘通道提供高速 DDR 時鐘信號，並且是主要數據源。從端在時鐘通道接收時鐘信號，並且是主要數據接收端。數據通信的主要方向，從源到接收端，稱為前向方向。相反方向的數據通信稱為反向傳輸。只有雙向數據通道可以在反向方向上傳輸。在所有情況下，時鐘通道保持在前向方向，但雙向數據通道可以反向，從從端獲取數據。
5.3 High Frequency Clock Generation 5.3 高頻時鐘生成
In many cases a PLL Clock Multiplier is needed for the high frequency clock generation at the Master Side. The D-PHY specification uses an architectural model where a separate Clock Multiplier Unit outside the PHY generates the required high frequency clock signals for the PHY. Whether this Clock Multiplier Unit in practice is integrated inside the PHY is left to the implementer. 在許多情況下，主端需要一個 PLL 時鐘倍增器來生成高頻時鐘。D-PHY 規範使用一種架構模型，其中 PHY 外部的獨立時鐘倍增器單元生成 PHY 所需的高頻時鐘信號。這個時鐘倍增器單元在實際上是否集成在 PHY 內部則由實施者決定。
5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface 5.4 時鐘通道、數據通道和 PHY 協議介面
A complete Link contains, beside Lane Modules, a PHY Adapter Layer that ties all Lanes, the Clock Multiplier Unit, and the PHY Protocol Interface together. Figure 2 shows a PHY configuration example for a Link with two Data Lanes plus a separate Clock Multiplier Unit. The PHY Adapter Layer, though a component of a PHY, is not within the scope of this specification. 一個完整的連結除了通道模組外，還包含一個將所有通道、時鐘倍增單元和 PHY 協議介面連接在一起的 PHY 適配層。圖 2 顯示了一個具有兩個數據通道和一個單獨時鐘倍增單元的連結的 PHY 配置示例。雖然 PHY 適配層是 PHY 的一個組件，但不在本規範的範疇內。
The logical PHY-Protocol interface (PPI) for each individual Lane includes a set of signals to cover the functionality of that Lane. As shown in Figure 2, Clock signals may be shared for all Lanes. The reference clock and control signals for the Clock Multiplier Unit are not within the scope of this specification. 每個獨立通道的邏輯 PHY 協議介面（PPI）包括一組信號，以涵蓋該通道的功能。如圖 2 所示，時鐘信號可以在所有通道之間共享。時鐘倍增單元的參考時鐘和控制信號不在本規範的範疇內。
Figure 2 Two Data Lane PHY Configuration 圖 2 兩個數據通道 PHY 配置
5.5 Selectable Lane Options 5.5 可選車道選項
A PHY configuration consists of one Clock Lane and one or more Data Lanes. All Data Lanes shall support High-Speed transmission and Escape mode in the Forward direction. PHY 配置由一個時鐘通道和一個或多個數據通道組成。所有數據通道應支持高速傳輸和正向逃逸模式。
There are two main types of Data Lanes: 有兩種主要的數據通道：
Bi-directional (featuring Turnaround and some Reverse communication functionality) 雙向（具備回轉和某些反向通信功能）
Unidirectional (without Turnaround or any kind of Reverse communication functionality) 單向（不帶回轉或任何形式的反向通信功能）
Bi-directional Data Lanes shall include one or both of the following Reverse communication options: 雙向數據通道應包括以下一種或兩種反向通信選項：
High-Speed Reverse data communication 高速反向數據通信
Low-Power Reverse Escape mode (including or excluding LPDT) 低功耗反向逃逸模式（包括或不包括 LPDT）
All Lanes shall include Escape mode support for ULPS and Triggers in the Forward direction. Other Escape mode functionality is optional; all possible Escape mode features are described in Section 6.6. Applications shall define what additional Escape mode functionality is required and, for bi-directional Lanes, shall select Escape mode functionality for each direction individually. 所有通道應包括對 ULPS 和向前方向觸發的逃逸模式支持。其他逃逸模式功能是可選的；所有可能的逃逸模式特性在第 6.6 節中描述。應用程序應定義所需的其他逃逸模式功能，並且對於雙向通道，應分別選擇每個方向的逃逸模式功能。
This results in many options for complete PHY Configurations. The degrees of freedom are: 這導致了許多完整的 PHY 配置選項。自由度為：
Single or Multiple Data Lanes 單一或多個數據通道
Bi-directional and/or Unidirectional Data Lane (per Lane) 雙向和/或單向數據通道（每通道）
Supported types of Reverse communication (per Lane) 支持的反向通信類型（按通道）
Functionality supported by Escape mode (for each direction per Lane) 逃脫模式支持的功能（每條車道的每個方向）
Data transmission can be with 8-bit raw data (default) or using 8b9b encoded symbol (see Annex C) 數據傳輸可以使用 8 位原始數據（默認）或使用 8b9b 編碼符號（見附錄 C）
Figure 3 is a flow graph of the option selection process. Practical configuration examples can be found in Section 5.7. 圖 3 是選項選擇過程的流程圖。實際配置示例可以在第 5.7 節找到。
The required functions in a Lane Module depend on the Lane type and which side of the Lane Interconnect the Lane Module is located. There are three main Lane types: Clock Lane, Unidirectional Data Lane and Bi-directional Data Lane. Several PHY configurations can be constructed with these Lane types. See Figure 3 for more information on selecting Lane options. Lane 模組中所需的功能取決於 Lane 類型以及 Lane 模組位於 Lane 互連的哪一側。主要有三種 Lane 類型：時鐘 Lane、單向數據 Lane 和雙向數據 Lane。可以使用這些 Lane 類型構建幾種 PHY 配置。請參見圖 3 以獲取有關選擇 Lane 選項的更多信息。
Figure 4 shows a Universal Lane Module Diagram with a global overview of internal functionality of the CIL function. This Universal Module can be used for all Lane Types. The requirements for the ‘Control and Interface Logic’ (CIL) function depend on the Lane type and Lane side. Section 6 and Annex A implicitly specify the contents of the CIL function. The actual realization is left to the implementer. 圖 4 顯示了一個通用車道模組圖，提供了 CIL 功能內部功能的全球概覽。這個通用模組可以用於所有車道類型。對於“控制和介面邏輯”（CIL）功能的要求取決於車道類型和車道側。第 6 節和附錄 A 隱含地指定了 CIL 功能的內容。實際實現則留給實施者。
Figure 4 Universal Lane Module Architecture 圖 4 通用車道模組架構
Of course, stripped-down versions of the Universal Lane Module that just support the required functionality for a particular Lane type are possible. These stripped-down versions are identified by the acronyms in Table 1. For simplification reasons, any of the four identification characters can be replaced by an X, which means that this can be any of the available options. For example, a CIL-MFEN is therefore a stripped-down CIL function for the Master Side of a Unidirectional Lane with Escape mode functionality only in the Forward direction. A CIL-SRXX is a CIL function for the Slave Side of a Lane with support for Bidirectional High-Speed communication and any allowed subset of Escape mode. 當然，僅支持特定通道類型所需功能的簡化版通用通道模組是可能的。這些簡化版通過表 1 中的縮寫來識別。出於簡化原因，四個識別字符中的任何一個都可以用 X 替換，這意味著這可以是任何可用選項。例如，CIL-MFEN 因此是一個僅在前進方向上具有逃逸模式功能的單向通道主側的簡化 CIL 功能。CIL-SRXX 是一個支持雙向高速通信和任何允許的逃逸模式子集的通道從側的 CIL 功能。
Note that a CIL-XFXN implies a unidirectional Link, while either a CIL-XRXX or CIL-XXXY block implies a bidirectional Link. Note that Forward 'Escape’ (ULPS) entry for Clock Lanes is different than Escape mode entry for Data Lanes. 請注意，CIL-XFXN 表示單向鏈接，而 CIL-XRXX 或 CIL-XXXY 區塊則表示雙向鏈接。請注意，時鐘通道的前向「逃逸」（ULPS）進入與數據通道的逃逸模式進入不同。
Table 1 Lane Type Descriptors 表 1 車道類型描述
Prefix 前綴
通道互連側
Lane
Interconnect Side
Lane
Interconnect Side| Lane |
| :--- |
| Interconnect Side |
High-Speed Capabilities 高速能力
前進方向逃脫模式支援的功能
Forward
Direction Escape Mode Features Supported
Forward
Direction Escape Mode Features Supported| Forward |
| :--- |
| Direction Escape Mode Features Supported |
反向方向逃逸模式支持的功能 ^(1){ }^{1}
Reverse
Direction Escape
Mode Features Supported ^(1){ }^{1}
Reverse
Direction Escape
Mode Features Supported ^(1)| Reverse |
| :--- |
| Direction Escape |
| Mode Features Supported ${ }^{1}$ |
CIL-
M - 主控 S - 從屬 X - 不在乎
M - Master
S - Slave
X - Don't Care
M - Master
S - Slave
X - Don't Care| M - Master |
| :--- |
| S - Slave |
| X - Don't Care |
F - 僅前進 RR - 反向和前進 X - 不在乎 ^(2){ }^{2}
F - Forward Only
RR - Reverse and Forward
X - Don't Care ^(2){ }^{2}
F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)| F - Forward Only |
| :--- |
| $R$ - Reverse and Forward |
| X - Don't Care ${ }^{2}$ |
A - 全部（包括 LPDT） E - 事件 觸發器和 ULPS 只有 X - 不在乎
A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care
A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care| A - All (including LPDT) |
| :--- |
| E - events Triggers and ULPS Only X - Don't Care |
A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock
N - Not Applicable N - 不適用
N - Not Applicable N - 不適用
Prefix "Lane
Interconnect Side" High-Speed Capabilities "Forward
Direction Escape Mode Features Supported" "Reverse
Direction Escape
Mode Features Supported ^(1)"
CIL- "M - Master
S - Slave
X - Don't Care" "F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)" "A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care" A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock N - Not Applicable N - Not Applicable| Prefix | Lane <br> Interconnect Side | High-Speed Capabilities | Forward <br> Direction Escape Mode Features Supported | Reverse <br> Direction Escape <br> Mode Features Supported ${ }^{1}$ |
| :---: | :---: | :---: | :---: | :---: |
| CIL- | M - Master <br> S - Slave <br> X - Don't Care | F - Forward Only <br> $R$ - Reverse and Forward <br> X - Don't Care ${ }^{2}$ | A - All (including LPDT) <br> E - events Triggers and ULPS Only X - Don't Care | ```A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care``` |
| | | C-Clock | N - Not Applicable | N - Not Applicable |
Note: 注意：
“Any” is any combination of one or more functions. “任何”是由一個或多個函數的任意組合。
Only valid for Data Lanes, means “F” or “R”. 僅適用於數據通道，表示“F”或“R”。
The recommend PHY Protocol Interface contains Data-in and Data-out in byte format, Input and/or output Clock signals and Control signals. Control signals include requests, handshakes, test settings, and initialization. A proposal for a logical internal interface is described in Annex A. Although not a requirement it may be very useful to use the proposed PPI. For external use on IC’s an implementation may multiplex many signals on the same pins. However, for power efficiency reasons, the PPI is normally within an IC. 推薦的 PHY 協議介面包含以位元組格式的數據輸入和數據輸出、輸入和/或輸出時鐘信號以及控制信號。控制信號包括請求、握手、測試設置和初始化。附錄 A 中描述了一個邏輯內部介面的提案。雖然這不是一個要求，但使用提議的 PPI 可能非常有用。對於 IC 的外部使用，實現可能會在相同的引腳上多路復用許多信號。然而，出於功率效率的原因，PPI 通常位於 IC 內部。
5.6.1 Unidirectional Data Lane 5.6.1 單向數據通道
For a Unidirectional Data Lane the Master Module shall contain at least a HS-TX, a LP-TX, and a CILMFXN function. The Slave side shall contain at least a HS-RX, a LP-RX and a CIL-SFXN. 對於單向數據通道，主模塊應至少包含一個 HS-TX、一個 LP-TX 和一個 CILMFXN 功能。從屬端應至少包含一個 HS-RX、一個 LP-RX 和一個 CIL-SFXN。
5.6.2 Bi-directional Data Lanes 5.6.2 雙向數據通道
A bi-directional Data Lane Module includes some form of reverse communication; either High-Speed Reverse Communication, Reverse Escape mode, or both. The functions required depend on what methods of Reverse communication are included in the Lane Module. 雙向數據通道模組包括某種形式的反向通信；無論是高速反向通信、反向逃逸模式，還是兩者皆有。所需的功能取決於通道模組中包含的反向通信方法。
5.6.2.1 Bi-directional Data Lane without High-Speed Reverse Communication 5.6.2.1 雙向數據通道無高速反向通信
A bi-directional Data Lane Module without High-Speed Reverse Communication shall include a Reverse Escape mode. The Master-side Lane Module includes a HS-TX, LP-TX, LP-RX, LP-CD, and CIL-MFXY. The Slave-side consists of a HS-RX, LP-RX, LP-TX, LP-CD and a CIL-SFXY. 一個不具備高速反向通信的雙向數據通道模塊應包括一個反向逃逸模式。主端通道模塊包括 HS-TX、LP-TX、LP-RX、LP-CD 和 CIL-MFXY。從端則由 HS-RX、LP-RX、LP-TX、LP-CD 和 CIL-SFXY 組成。
5.6.2.2 Bi-directional Data Lane with High-Speed Reverse Communication 5.6.2.2 雙向數據通道與高速反向通信
A bi-directional Data Lane Module with High-Speed Reverse Communication shall include a Reverse Escape mode. The Master-side Lane Module includes a HS-TX, HS-RX, LP-TX, LP-RX, LP-CD, and CILMRXX. The Slave-side consists of a HS-RX, HS-TX, LP-RX, LP-TX, LP-CD and a CIL-SRXX. 一個具有高速反向通信的雙向數據通道模塊應包括一個反向逃逸模式。主端通道模塊包括 HS-TX、HS-RX、LP-TX、LP-RX、LP-CD 和 CILMRXX。從端則由 HS-RX、HS-TX、LP-RX、LP-TX、LP-CD 和 CIL-SRXX 組成。
This type of Lane Module may seem suitable for both Master and Slave side but because of the asymmetry of the Link one side shall be configured as Master and the other side as Slave. 這種類型的通道模組可能看起來適合主端和從端，但由於鏈接的不對稱性，一側應配置為主端，另一側則配置為從端。
5.6.3 Clock Lane 5.6.3 鐘路
For the Clock Lane, only a limited set of line states is used. However, for Clock Transmission and LowPower mode the same TX and RX functions are required as for Unidirectional Data Lanes. A Clock Lane Module for the Master Side therefore contains a HS-TX, LP-TX, and a CIL-MCNN function, while the Slave Side Module includes a HS-RX, a LP-RX and a CIL-SCNN function. 對於時鐘通道，只使用有限的一組線狀態。然而，對於時鐘傳輸和低功耗模式，與單向數據通道相同的 TX 和 RX 功能是必需的。因此，主端的時鐘通道模組包含 HS-TX、LP-TX 和 CIL-MCNN 功能，而從端模組則包括 HS-RX、LP-RX 和 CIL-SCNN 功能。
Note that the required functionality for a Clock Lane is similar, but not identical, to a Unidirectional Data Lane. The High-Speed DDR clock is transmitted in quadrature phase with Data signals instead of in-phase. In addition, the Clock Lane Escape mode entry is different than that used for Data Lanes. Furthermore, since a Clock Lane only supports ULPS, an Escape mode entry code is not required. 請注意，時鐘通道所需的功能與單向數據通道相似，但並不相同。高速 DDR 時鐘以與數據信號正交相位而非同相位的方式傳輸。此外，時鐘通道的逃逸模式進入方式與數據通道使用的方式不同。此外，由於時鐘通道僅支持 ULPS，因此不需要逃逸模式進入代碼。
The internal clock signals with the appropriate phases are generated outside the PHY and delivered to the individual Lanes. The realization of the Clock generation unit is outside the scope of this specification. The quality of the internal clock signals shall be sufficient to meet the timing requirement for the signals as specified in Section 10. 內部時鐘信號與適當的相位是在 PHY 外部生成並傳遞到各個通道。時鐘生成單元的實現不在本規範的範疇內。內部時鐘信號的質量應足以滿足第 10 節中規定的信號時序要求。
5.7 Configurations 5.7 配置
This section outlines several common PHY configurations but should not be considered an exhaustive list of all possible arrangements. Any other configuration that does not violate the requirements of this document is also allowed. 本節概述了幾種常見的 PHY 配置，但不應被視為所有可能安排的詳盡列表。任何其他不違反本文件要求的配置也都是允許的。
In order to create an abstraction level, the Lane Modules are represented in this section by Lane Module Symbols. Figure 5 shows the syntax and meaning of symbols. 為了創建一個抽象層級，本節中用車道模組符號表示車道模組。圖 5 顯示了符號的語法和含義。
This 這個
Other Options 其他選項
Meaning 意義
C1CCCCCCC1
Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) 支持的高速數據傳輸方向（雙向或單向）
C1[I-][In][IH]1
C1C[I-][I-]1
Clock Lane 時鐘巷
longleftrightarrow\longleftrightarrow
longrightarrow\longrightarrow
Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) 支持的逃逸模式方向，排除 LPDT（雙向或僅前進）
⊮ longrightarrow\nVdash \longrightarrow
⋙≪\ggg \ll
支持的逃逸模式方向包括 LPDT（雙向、僅向前或僅向後）
Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)
Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)| Supported Directions for Escape mode including LPDT |
| :--- |
| (Bi-directional, Forward Only or Reverse Only) |
rarr\rightarrow
larr\leftarrow
時鐘方向（根據定義從主設備到從設備，必須指向與“僅時鐘通道”箭頭相同的方向）
Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)
Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)| Clock Direction |
| :--- |
| (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
PPI: PHY-Protocol Interface PPI：PHY-協議介面
This Other Options Meaning
C1CCCCCCC1 https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792 Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional)
C1[I-][In][IH]1 C1C[I-][I-]1 Clock Lane
longleftrightarrow longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only)
⊮ longrightarrow ⋙≪ "Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)"
rarr larr "Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)"
https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607 PPI: PHY-Protocol Interface| This | Other Options | Meaning |
| :---: | :---: | :---: |
| <smiles>C1CCCCCCC1</smiles> |  | Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) |
| <smiles>C1[I-][In][IH]1</smiles> | <smiles>C1C[I-][I-]1</smiles> | Clock Lane |
| $\longleftrightarrow$ | $\longrightarrow$ | Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) |
| $\nVdash \longrightarrow$ | $\ggg \ll$ | Supported Directions for Escape mode including LPDT <br> (Bi-directional, Forward Only or Reverse Only) |
| $\rightarrow$ | $\leftarrow$ | Clock Direction <br> (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
|  | | PPI: PHY-Protocol Interface |
Figure 5 Lane Symbol Macros and Symbols Legend 圖 5 車道符號宏和符號圖例
For multiple Data Lanes a large variety of configurations is possible. Figure 6 shows an overview of symbolic representations for different Lane types. The acronyms mentioned for each Lane type represent the functionality of each module in a short way. This also sets the requirements for the CIL function inside each Module. 對於多個數據通道，可以有多種配置。圖 6 顯示了不同通道類型的符號表示概述。提到的每個通道類型的縮寫簡要表示了每個模塊的功能。這也設置了每個模塊內部 CIL 功能的要求。
Figure 6 All Possible Data Lane Types and a Basic Unidirectional Clock Lane 圖 6 所有可能的數據通道類型和一個基本的單向時鐘通道
5.7.1 Unidirectional Configurations 5.7.1 單向配置
All unidirectional configurations are constructed with a Clock Lane and one or more Unidirectional Data Lanes. Two basic configurations can be distinguished: Single Data Lane and Multiple Data Lanes. For completeness a Dual-Simplex configuration is also shown. At the PHY level there is no difference between a Dual-Simplex configuration and two independent unidirectional configurations. 所有單向配置都是由一條時鐘通道和一條或多條單向數據通道構成的。可以區分兩種基本配置：單數據通道和多數據通道。為了完整性，還顯示了雙簡單配置。在 PHY 層面，雙簡單配置與兩個獨立的單向配置之間沒有區別。
5.7.1.1 PHY Configuration with a Single Data Lane 5.7.1.1 單數據通道的 PHY 配置
This configuration includes one Clock Lane and one Unidirectional Data Lane from Master to Slave. Communication is therefore only possible in the Forward direction. Figure 7 shows an example configuration without LPDT. This configuration requires four interconnect signal wires. 此配置包括一個時鐘通道和一個單向數據通道，從主設備到從設備。因此，通信僅能在前向方向進行。圖 7 顯示了一個不包含 LPDT 的示例配置。此配置需要四條互連信號線。
Figure 7 Unidirectional Single Data Lane Configuration 圖 7 單向單數據通道配置
5.7.1.2 PHY Configuration with Multiple Data Lanes 5.7.1.2 多數據通道的 PHY 配置
This configuration includes one Clock Lane and multiple Unidirectional Data Lanes from Master to Slave. Bandwidth is extended, but communication is only possible in the Forward direction. The PHY specification does not require all Data Lanes to be active simultaneously. In fact, the Protocol layer controls all Data Lanes individually. Figure 8 shows an example of this configuration for three Data Lanes. If N is the number of Data Lanes, this configuration requires 2**(N+1)2 *(\mathrm{~N}+1) interconnect wires. 此配置包括一個時鐘通道和多個從主設備到從設備的單向數據通道。帶寬得以擴展，但通信僅能在前向方向進行。PHY 規範並不要求所有數據通道同時處於活動狀態。事實上，協議層單獨控制所有數據通道。圖 8 顯示了三個數據通道的此配置示例。如果 N 是數據通道的數量，則此配置需要 2**(N+1)2 *(\mathrm{~N}+1) 互連線。
Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT 圖 8 單向多數據通道配置，無 LPDT
5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes) 5.7.1.3 雙簡單路徑（雙向單向車道）
This case is the same as two independent (dual), unidirectional (simplex) Links: one for each direction. Each direction has its own Clock Lane and may contain either a single, or multiple, Data Lanes. Please note that the Master and Slave side for the two different directions are opposite. The PHY configuration for each 此案例與兩個獨立的（雙向）單向（簡單）鏈路相同：每個方向各有一個。每個方向都有自己的時鐘通道，並且可以包含單個或多個數據通道。請注意，兩個不同方向的主端和從端是相對的。每個的 PHY 配置
direction shall comply with the D-PHY specifications. As both directions are conceptually independent, the bit rates for each direction do not have to match. However, for practical implementations, it is attractive to match rates and share some internal signals as long as both Links fulfill all specifications externally. Figure 9 shows an example of this dual PHY configuration. 方向應遵循 D-PHY 規範。由於兩個方向在概念上是獨立的，因此每個方向的比特率不必匹配。然而，對於實際實現，匹配速率並共享一些內部信號是有吸引力的，只要兩個鏈路在外部滿足所有規範。圖 9 顯示了這種雙 PHY 配置的示例。
Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT 圖 9 兩個方向使用兩個獨立的單向 PHY 而不使用 LPDT
Bi-directional configurations consist of a Clock Lane and one or more bi-directional Data Lanes. Halfduplex operation enables bi-directional traffic across shared interconnect wires. This configuration saves wires compared to the Dual-Simplex configuration. However, time on the Link is shared between Forward and Reverse traffic and Link Turnaround. The High-Speed bit rate in the Reverse direction is, by definition, one-fourth of the bit rate in the Forward direction. LPDT can have similar rates in the Forward and Reverse directions. This configuration is especially useful for cases with asymmetrical data traffic. 雙向配置由一條時鐘通道和一條或多條雙向數據通道組成。半雙工操作使得共享互連線路上的雙向流量成為可能。與雙簡單配置相比，這種配置節省了線路。然而，鏈路上的時間在正向和反向流量以及鏈路周轉之間共享。反向方向的高速比特率根據定義是正向方向比特率的四分之一。LPDT 在正向和反向方向上可以具有相似的比率。這種配置對於不對稱數據流量的情況特別有用。
5.7.2.1 PHY Configurations with a Single Data Lane 5.7.2.1 單數據通道的 PHY 配置
This configuration includes one Clock Lane and one of any kind of bi-directional Data Lane. This allows time-multiplexed data traffic in both Forward and Reverse directions. Figure 10 shows this configuration with a Data Lane that supports both High-Speed and Escape (without LPDT) communication in both directions. Other possibilities are that only one type of reverse communication is supported or LPDT is also included in one or both directions. All these configurations require four interconnect wires. 此配置包括一個時鐘通道和一個任意類型的雙向數據通道。這允許在前向和反向方向上進行時間多路復用的數據流量。圖 10 顯示了此配置，其中數據通道支持雙向的高速和逃逸（不帶 LPDT）通信。其他可能性是僅支持一種類型的反向通信，或在一個或兩個方向上也包括 LPDT。所有這些配置都需要四根互連線。
Figure 10 Bidirectional Single Data Lane Configuration 圖 10 雙向單數據通道配置
5.7.2.2 PHY Configurations with Multiple Data Lanes 5.7.2.2 多數據通道的 PHY 配置
This configuration includes one Clock Lane and multiple bi-directional Data Lanes. Communication is possible in both the Forward and Reverse direction for each individual Lane. The maximum available bandwidth scales with the number of Lanes for each direction. The PHY specification does not require all Data Lanes to be active simultaneously or even to be operating in the same direction. In fact, the Protocol layer controls all Data Lanes individually. Figure 11 shows an example configuration with two Data Lanes. If N is the number of Data Lanes, this configuration requires 2**(N+1)2 *(\mathrm{~N}+1) interconnect wires. 此配置包括一個時鐘通道和多個雙向數據通道。每個通道都可以在前向和反向方向上進行通信。每個方向的最大可用帶寬隨通道數量的增加而增加。PHY 規範不要求所有數據通道同時處於活動狀態，甚至不要求它們在相同方向上運行。事實上，協議層單獨控制所有數據通道。圖 11 顯示了具有兩個數據通道的示例配置。如果 N 是數據通道的數量，則此配置需要 2**(N+1)2 *(\mathrm{~N}+1) 互連線。
Figure 11 Bi-directional Multiple Data Lane Configuration 圖 11 雙向多數據通道配置
5.7.3 Mixed Data Lane Configurations 5.7.3 混合數據通道配置
Instead of using only one Data Lane type, PHY configurations may combine different unidirectional and bidirectional Data Lane types. Figure 12 shows an example configuration with one bi-directional and one unidirectional Data Lane, both without LPDT. 除了使用單一的數據通道類型外，PHY 配置可以結合不同的單向和雙向數據通道類型。圖 12 顯示了一個配置示例，其中包含一個雙向和一個單向數據通道，兩者均不使用 LPDT。
Figure 12 Mixed Type Multiple Data Lane Configuration 圖 12 混合型多數據通道配置
6 Global Operation 6 全球運營
This section specifies operation of the D-PHY including signaling types, communication mechanisms, operating modes and coding schemes. Detailed specifications of the required electrical functions can be found in Section 9. 本節規定了 D-PHY 的操作，包括信號類型、通信機制、操作模式和編碼方案。所需電氣功能的詳細規範可以在第 9 節找到。
6.1 Transmission Data Structure 6.1 傳輸數據結構
During High-Speed, or Low-Power, transmission, the Link transports payload data provided by the protocol layer to the other side of the Link. This section specifies the restrictions for the transmitted and received payload data. 在高速或低功耗傳輸期間，鏈路將協議層提供的有效載荷數據傳輸到鏈路的另一端。本節規定了傳輸和接收的有效載荷數據的限制。
6.1.1 Data Units 6.1.1 數據單位
The minimum payload data unit shall be one byte. Data provided to a TX and taken from a RX on any Lane shall be an integer number of bytes. This restriction holds for both High-Speed and Low-Power data transmission in any direction. 最小有效載荷數據單位應為一個字節。提供給 TX 並從任何通道的 RX 接收的數據應為整數字節數。此限制適用於任何方向的高速和低功耗數據傳輸。
6.1.2 Bit order, Serialization, and De-Serialization 6.1.2 位元順序、序列化和反序列化
For serial transmission, the data shall be serialized in the transmitting PHY and de-serialized in the receiving PHY. The PHY assumes no particular meaning, value or order of incoming and outgoing data. 對於串行傳輸，數據應在發送的物理層中進行序列化，並在接收的物理層中進行反序列化。物理層不假設進出數據的特定含義、值或順序。
6.1.3 Encoding and Decoding 6.1.3 編碼與解碼
Line coding is not required by this specification. However, if line coding is used, it shall be implemented according to Annex C. 本規範不要求行編碼。然而，如果使用行編碼，則應根據附錄 C 實施。
6.1.4 Data Buffering 6.1.4 數據緩衝
Data transmission takes place on protocol request. As soon as communication starts, the protocol layer at the transmit side shall provide valid data as long as it does not stop its transmission request. For Lanes that use line coding, control symbols can also be inserted into the transmission. The protocol on the receive side shall take the data as soon as delivered by the receiving PHY. The signaling concept, and therefore the PHY protocol handshake, does not allow data throttling. Any data buffering for this purpose shall be inside the protocol layer. 數據傳輸在協議請求上進行。一旦通信開始，發送端的協議層應提供有效數據，只要它不停止其傳輸請求。對於使用行編碼的通道，控制符號也可以插入到傳輸中。接收端的協議應在接收 PHY 交付數據後立即接收數據。信號概念，因此 PHY 協議握手，不允許數據節流。為此目的的任何數據緩衝應在協議層內部。
6.2 Lane States and Line Levels 6.2 車道狀態和線級
Transmitter functions determine the Lane state by driving certain Line levels. During normal operation either a HS-TX or a LP-TX is driving a Lane. A HS-TX always drives the Lane differentially. The two LPTX’s drive the two Lines of a Lane independently and single-ended. This results in two possible HighSpeed Lane states and four possible Low-Power Lane states. The High-Speed Lane states are Differential-0 and Differential-1. The interpretation of Low-Power Lane states depends on the mode of operation. The LP-Receivers shall always interpret both High-Speed differential states as LP-00. 發射器功能通過驅動某些線路電平來確定通道狀態。在正常操作中，無論是 HS-TX 還是 LP-TX 都在驅動一個通道。HS-TX 始終以差分方式驅動通道。兩個 LPTX 獨立且單端地驅動一個通道的兩條線。這導致兩種可能的高速通道狀態和四種可能的低功耗通道狀態。高速通道狀態為差分-0 和差分-1。低功耗通道狀態的解釋取決於操作模式。LP 接收器應始終將兩個高速差分狀態解釋為 LP-00。
State Code 州代碼
Line Voltage Levels 線電壓水平
High-Speed 高速
Low-Power 低功耗
Dp-Line
Dn-Line
Burst Mode 爆炸模式
Control Mode 控制模式
Escape Mode 逃脫模式
HS-0
HS Low
HS High
Differential-0
N/A, Note 1 N/A, 注意 1
N/A, Note 1 N/A, 注意 1
HS-1
HS High
HS Low
Differential-1
N/A, Note 1 N/A, 注意 1
N/A, Note 1 N/A, 注意 1
LP-00
LP Low
LP Low
N/A
Bridge 橋
Space 太空
LP-01
LP Low
LP High
N/A
HS-Rqst
Mark-0
LP-10
LP High
LP Low
N/A
LP-Rqst
Mark-1
LP-11
LP High
LP High
N/A
Stop 停止
N/A, Note 2 不適用，註釋 2
State Code Line Voltage Levels High-Speed Low-Power
Dp-Line Dn-Line Burst Mode Control Mode Escape Mode
HS-0 HS Low HS High Differential-0 N/A, Note 1 N/A, Note 1
HS-1 HS High HS Low Differential-1 N/A, Note 1 N/A, Note 1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop N/A, Note 2| State Code | Line Voltage Levels | | High-Speed | | Low-Power |
| :--- | :--- | :--- | :--- | :--- | :--- |
| | Dp-Line | Dn-Line | Burst Mode | Control Mode | Escape Mode |
| HS-0 | HS Low | HS High | Differential-0 | N/A, Note 1 | N/A, Note 1 |
| HS-1 | HS High | HS Low | Differential-1 | N/A, Note 1 | N/A, Note 1 |
| LP-00 | LP Low | LP Low | N/A | Bridge | Space |
| LP-01 | LP Low | LP High | N/A | HS-Rqst | Mark-0 |
| LP-10 | LP High | LP Low | N/A | LP-Rqst | Mark-1 |
| LP-11 | LP High | LP High | N/A | Stop | N/A, Note 2 |
Note: 注意：
During High-Speed transmission the Low-Power Receivers observe LP-00 on the Lines. 在高速傳輸期間，低功耗接收器在信號線上觀察到 LP-00。
If LP-11 occurs during Escape mode the Lane returns to Stop state (Control Mode LP-11). 如果在逃生模式下發生 LP-11，車道將返回停止狀態（控制模式 LP-11）。
6.3 Operating Modes: Control, High-Speed, and Escape 6.3 操作模式：控制、高速和逃逸
During normal operation a Data Lane will be either in Control or High-Speed mode. High-Speed Data transmission happens in bursts and starts from and ends at a Stop state (LP-11), which is by definition in Control mode. The Lane is only in High-Speed mode during Data bursts. The sequence to enter High-Speed mode is: LP-11, LP-01, LP-00 at which point the Data Lane remains in High-Speed mode until a LP-11 is received. The Escape mode can only be entered via a request within Control mode. The Data Lane shall always exit Escape mode and return to Control mode after detection of a Stop state. If not in High-Speed or Escape mode the Data Lane shall stay in Control mode. For Data Lanes and for Clock Lanes the Stop state serves as general standby state and may last for any period of time > T_("LPx ")>T_{\text {LPx }}. Possible events starting from the Stop state are High-Speed Data Transmission request (LP-11, LP-01, LP-00), Escape mode request (LP-11, LP-10, LP-00, LP-01, LP-00) or Turnaround request (LP-11, LP-10, LP-00, LP-10, LP-00). 在正常操作中，數據通道將處於控制模式或高速模式。高速數據傳輸以突發方式進行，並從停止狀態（LP-11）開始和結束，根據定義，這是控制模式。通道僅在數據突發期間處於高速模式。進入高速模式的序列為：LP-11，LP-01，LP-00，此時數據通道將保持在高速模式，直到接收到 LP-11。逃逸模式只能通過控制模式中的請求進入。數據通道在檢測到停止狀態後，應始終退出逃逸模式並返回控制模式。如果不在高速或逃逸模式中，數據通道將保持在控制模式。對於數據通道和時鐘通道，停止狀態作為一般待機狀態，並且可以持續任何時間 > T_("LPx ")>T_{\text {LPx }} 。從停止狀態開始的可能事件包括高速數據傳輸請求（LP-11，LP-01，LP-00）、逃逸模式請求（LP-11，LP-10，LP-00，LP-01，LP-00）或轉向請求（LP-11，LP-10，LP-00，LP-10，LP-00）。
6.4 High-Speed Data Transmission 6.4 高速數據傳輸
High-Speed Data Transmission occurs in bursts. To aid receiver synchronization, data bursts shall be extended on the transmitter side with a leader and trailer sequence and shall be eliminated on the receiver side. These leader and trailer sequences can therefore only be observed on the transmission lines. 高速數據傳輸以突發方式進行。為了幫助接收器同步，數據突發應在發射器端用前導和尾隨序列進行擴展，並在接收器端消除這些序列。因此，這些前導和尾隨序列只能在傳輸線上觀察到。
Transmission starts from, and ends with, a Stop state. During the intermediate time between bursts a Data Lane shall remain in the Stop state, unless a Turnaround or Escape request is presented on the Lane. During a HS Data Burst the Clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave side. 傳輸從停止狀態開始，並以停止狀態結束。在突發之間的中間時間，數據通道應保持在停止狀態，除非在通道上提出了轉換或逃逸請求。在高速度數據突發期間，時鐘通道應處於高速模式，為從屬端提供 DDR 時鐘。
6.4.1 Burst Payload Data 6.4.1 突發有效載荷數據
The payload data of a burst shall always represent an integer number of payload data bytes with a minimum length of one byte. Note that for short bursts the Start and End overhead consumes much more time than the actual transfer of the payload data. There is no maximum number of bytes implied by the PHY. However, in the PHY there is no autonomous way of error recovery during a HS data burst and the practical BER will not be zero. Therefore, it is important to consider for every individual protocol what the best choice is for maximum burst length. 突發的有效載荷數據應始終表示一個整數數量的有效載荷數據字節，最小長度為一個字節。請注意，對於短突發，開始和結束的開銷消耗的時間遠遠超過實際的有效載荷數據傳輸。PHY 並未暗示最大字節數。然而，在 PHY 中，HS 數據突發期間沒有自動錯誤恢復的方法，實際的比特錯誤率不會為零。因此，對於每個單獨的協議，考慮最大突發長度的最佳選擇是很重要的。
6.4.2 Start-of-Transmission 6.4.2 傳輸開始
After a Transmit request, a Data Lane leaves the Stop state and prepares for High-Speed mode by means of a Start-of-Transmission (SoT) procedure. Table 3 describes the sequence of events on TX and RX side. 在傳輸請求之後，數據通道離開停止狀態，通過傳輸開始（SoT）程序準備進入高速模式。表 3 描述了 TX 和 RX 端的事件序列。
Table 3 Start-of-Transmission Sequence 表 3 傳輸開始序列
TX Side TX 端
RX Side RX 端
Drives Stop state (LP-11) 驅動器停止狀態 (LP-11)
Observes Stop state 觀察停止狀態
Drives HS-Rqst state (LP-01) for time TLPX 驅動 HS-Rqst 狀態 (LP-01) 於時間 TLPX
觀察從 LP-11 到 LP-01 的過渡情況
Observes transition from LP-11 to LP-01 on the
Lines
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
Drives Bridge state (LP-00) for time THS-PREPARE 驅動橋樑狀態 (LP-00) 於時間 THS-PREPARE
觀察從 LP-01 到 LP-00 的轉換，並在時間 TD-TERM-EN 之後啟用線路終止
Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN
Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN| Observes transition form LP-01 to LP-00 on the |
| :--- |
| Lines, enables Line Termination after time TD-TERM-EN |
Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THS-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
Drives HS-0 for a time THS-ZERO 驅動器 HS-0 持續時間 THS-ZERO
Starts looking for Leader-Sequence 開始尋找領導序列
在識別到領導序列 'O11101' 時進行同步
Synchronizes upon recognition of Leader Sequence
'O11101'
Synchronizes upon recognition of Leader Sequence
'O11101'| Synchronizes upon recognition of Leader Sequence |
| :--- |
| 'O11101' |
on a rising Clock edge 在上升時鐘邊緣
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Rqst state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time THS-PREPARE "Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously." "Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects"
Drives HS-0 for a time THS-ZERO Starts looking for Leader-Sequence
"Synchronizes upon recognition of Leader Sequence
'O11101'"
on a rising Clock edge | TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time THS-PREPARE | Observes transition form LP-01 to LP-00 on the <br> Lines, enables Line Termination after time TD-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. | Enables HS-RX and waits for timer THS-SETTLE to <br> expire in order to neglect transition effects |
| Drives HS-0 for a time THS-ZERO | Starts looking for Leader-Sequence |
| | Synchronizes upon recognition of Leader Sequence <br> 'O11101' |
| on a rising Clock edge | |
All rights reserved. 版權所有。
6.4.3 End-of-Transmission 6.4.3 傳輸結束
TX Side TX 端
RX Side RX 端
Completes Transmission of payload data 完成有效載荷數據的傳輸
Receives payload data 接收有效載荷數據
在最後一個有效載荷數據位之後立即切換差分狀態，並保持該狀態一段時間 THS-TRAIL
Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL
Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL| Toggles differential state immediately after last |
| :--- |
| payload data bit and keeps that state for a time |
| THS-TRAIL |
禁用 HS-TX，啟用 LP-TX，並驅動停止狀態 (LP-11) 持續時間 THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables the LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
檢測離開 LP-00 狀態並進入停止狀態 (LP-11) 的線路並禁用終止
Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination
Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination| Detects the Lines leaving LP-00 state and entering |
| :--- |
| Stop state (LP-11) and disables Termination |
忽略上個時期的 THS-SKIP 位元以隱藏過渡效果
Neglect bits of last period THS-SKIP to hide transition
effects
Neglect bits of last period THS-SKIP to hide transition
effects| Neglect bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
檢測有效數據中的最後過渡，確定最後有效數據字節並跳過尾部序列
Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence
Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence| Detect last transition in valid Data, determine last |
| :--- |
| valid Data byte and skip trailer sequence |
TX Side RX Side
Completes Transmission of payload data Receives payload data
"Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL"
"Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination"
"Neglect bits of last period THS-SKIP to hide transition
effects"
"Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence"| TX Side | RX Side |
| :--- | :--- |
| Completes Transmission of payload data | Receives payload data |
| Toggles differential state immediately after last <br> payload data bit and keeps that state for a time <br> THS-TRAIL | |
| Disables the HS-TX, enables the LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines leaving LP-00 state and entering <br> Stop state (LP-11) and disables Termination |
| | Neglect bits of last period THS-SKIP to hide transition <br> effects |
| | Detect last transition in valid Data, determine last <br> valid Data byte and skip trailer sequence |
6.4.4 HS Data Transmission Burst 6.4.4 HS 數據傳輸突發
At the end of a Data Burst, a Data Lane leaves High-Speed Transmission mode and enters the Stop state by means of an End-of-Transmission (EoT) procedure. Table 4 shows a possible sequence of events during the EoT procedure. Note, EoT processing may be handled by the protocol or by the D-PHY. 在數據突發結束時，數據通道離開高速傳輸模式，通過結束傳輸（EoT）程序進入停止狀態。表 4 顯示了 EoT 程序中可能的事件序列。請注意，EoT 處理可以由協議或 D-PHY 處理。
Table 4 End-of-Transmission Sequence 表 4 傳輸結束序列
Figure 14 shows the sequence of events during the transmission of a Data Burst. Transmission can be started and ended independently for any Lane by the protocol. However, for most applications the Lanes will start synchronously but may end at different times due to an unequal amount of transmitted bytes per Lane. The handshake with the protocol-layer is described in Annex A. 圖 14 顯示了數據突發傳輸過程中的事件序列。根據協議，任何通道的傳輸可以獨立開始和結束。然而，對於大多數應用來說，通道將同步開始，但由於每個通道傳輸的字節數不等，可能會在不同的時間結束。與協議層的握手在附錄 A 中描述。
Figure 14 High-Speed Data Transmission in Bursts 圖 14 高速數據突發傳輸
Figure 15 shows the state machine for High-Speed data transmission that is described in Table 5. 圖 15 顯示了表 5 中描述的高速數據傳輸的狀態機。
Figure 15 TX and RX State Machines for High-Speed Data Transmission 圖 15 高速數據傳輸的 TX 和 RX 狀態機
Table 5 High-Speed Data Transmission State Machine Description 表 5 高速數據傳輸狀態機描述
State 州
線條狀態
Line
Condition/State
Line
Condition/State| Line |
| :---: |
| Condition/State |
Exit State 退出狀態
Exit Conditions 退出條件
TX-Stop
Transmit LP-11 傳輸 LP-11
TX-HS-Rqst
高速度傳輸協議的要求
On request of Protocol for High-Speed
Transmission
On request of Protocol for High-Speed
Transmission| On request of Protocol for High-Speed |
| :--- |
| Transmission |
TX-HS-Rqst
Transmit LP-01 傳輸 LP-01
TX-HS-Prpr
End of timed interval TLPX 結束計時區間 TLPX
TX-HS-Prpr
Transmit LP-00 傳輸 LP-00
TX-HS-Go
End of timed interval THS-PREPARE 定時區間結束 THS-PREPARE
After Sync sequence if first payload data bit is 0 在同步序列之後，如果第一個有效載荷數據位是 0
TX-HS-1
After Sync sequence if first payload data bit is 1 在同步序列之後，如果第一個有效載荷數據位是 1
TX-HS-0
Transmit HS-0 傳輸 HS-0
TX-HS-0
Send another HS-0 bit after a HS-0 bit 在 HS-0 位元之後再發送一個 HS-0 位元
TX-HS-1
Send a HS-1 bit after a HS-0 bit 在 HS-0 位元之後發送一個 HS-1 位元
TX-HS-1
Transmit HS-1 傳輸 HS-1
TX-HS-0
Send a HS-1 bit after a HS-0 bit 在 HS-0 位元之後發送一個 HS-1 位元
TX-HS-1
Send another HS-1 bit after a HS-1 在一個 HS-1 之後發送另一個 HS-1 位元
Trail-HS-0
Last payload bit is HS-1, trailer sequence is HS-0 最後的有效載荷位元是 HS-1，尾部序列是 HS-0
Trail-HS-0
Transmit HS-0 傳輸 HS-0
TX-Stop
End of timed interval THS-TRAlL 結束計時區間 THS-TRAlL
Trail-HS-1
Transmit HS-1 傳輸 HS-1
TX-Stop
End of timed interval THS-TRAlL 結束計時區間 THS-TRAlL
RX-Stop
Receive LP-11 接收 LP-11
RX-HS-Rqst
Line transition to LP-01 線路過渡到 LP-01
RX- HS-Rqst
Receive LP-01 接收 LP-01
RX-HS-Prpr
Line transition to LP-00 線路過渡到 LP-00
State "Line
Condition/State" Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr End of timed interval TLPX
TX-HS-Prpr Transmit LP-00 TX-HS-Go End of timed interval THS-PREPARE
TX-HS-Go Transmit HS-0 TX-HS-Sync End of timed interval THS-zERO
TX-HS-Sync "Transmit
sequence
HS-00011101" TX-HS-0 After Sync sequence if first payload data bit is 0
TX-HS-1 After Sync sequence if first payload data bit is 1
TX-HS-0 Transmit HS-0 TX-HS-0 Send another HS-0 bit after a HS-0 bit
TX-HS-1 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Transmit HS-1 TX-HS-0 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Send another HS-1 bit after a HS-1
Trail-HS-0 Last payload bit is HS-1, trailer sequence is HS-0
Trail-HS-0 Transmit HS-0 TX-Stop End of timed interval THS-TRAlL
Trail-HS-1 Transmit HS-1 TX-Stop End of timed interval THS-TRAlL
RX-Stop Receive LP-11 RX-HS-Rqst Line transition to LP-01
RX- HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval TLPX |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval THS-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-Sync | End of timed interval THS-zERO |
| TX-HS-Sync | Transmit <br> sequence <br> HS-00011101 | TX-HS-0 | After Sync sequence if first payload data bit is 0 |
| | | TX-HS-1 | After Sync sequence if first payload data bit is 1 |
| TX-HS-0 | Transmit HS-0 | TX-HS-0 | Send another HS-0 bit after a HS-0 bit |
| | | TX-HS-1 | Send a HS-1 bit after a HS-0 bit |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-1 bit after a HS-0 bit |
| | | TX-HS-1 | Send another HS-1 bit after a HS-1 |
| | | Trail-HS-0 | Last payload bit is HS-1, trailer sequence is HS-0 |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval THS-TRAlL |
| Trail-HS-1 | Transmit HS-1 | TX-Stop | End of timed interval THS-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX- HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
State 州
線條狀態
Line
Condition/State
Line
Condition/State| Line |
| :---: |
| Condition/State |
Exit State 退出狀態
Exit Conditions 退出條件
RX-HS- Prpr
Receive LP-00 接收 LP-00
RX-HS-Term
End of timed interval TD-TERM-EN 定時區間結束 TD-TERM-EN
RX-HS-Term
Receive LP-00 接收 LP-00
RX-HS-Sync
End of timed interval THS-SETTLE 定時區間結束 THS-SETTLE
Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data.
Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data.| Proper match found (any single bit error allowed if |
| :--- |
| deskew calibration feature is not used) for Sync |
| sequence in HS stream, the following bits are |
| payload data. |
RX-HS-1
RX-HS-0
Receive HS-0 接收 HS-0
RX-HS-0
Receive payload data bit or trailer bit 接收有效載荷數據位或尾部位
RX-HS-1
RX-HS-1
Receive HS-1 接收 HS-1
RX-HS-0
Receive payload data bit or trailer bit 接收有效載荷數據位或尾部位
RX-HS-1
RX-Stop
Line transition to LP-11 線路過渡到 LP-11
State "Line
Condition/State" Exit State Exit Conditions
RX-HS- Prpr Receive LP-00 RX-HS-Term End of timed interval TD-TERM-EN
RX-HS-Term Receive LP-00 RX-HS-Sync End of timed interval THS-SETTLE
RX-HS-Sync "Receive HS
sequence
...00000011101" RX-HS-0 "Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data."
RX-HS-1
RX-HS-0 Receive HS-0 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-HS-1 Receive HS-1 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-Stop Line transition to LP-11| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS- Prpr | Receive LP-00 | RX-HS-Term | End of timed interval TD-TERM-EN |
| RX-HS-Term | Receive LP-00 | RX-HS-Sync | End of timed interval THS-SETTLE |
| RX-HS-Sync | Receive HS <br> sequence <br> ...00000011101 | RX-HS-0 | Proper match found (any single bit error allowed if <br> deskew calibration feature is not used) for Sync <br> sequence in HS stream, the following bits are <br> payload data. |
| | | RX-HS-1 | |
| RX-HS-0 | Receive HS-0 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| RX-HS-1 | Receive HS-1 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| | | RX-Stop | Line transition to LP-11 |
Note: 注意：
Stop states (TX-Stop, RX-Stop) have multiple valid exit states. 停止狀態（TX-停止，RX-停止）具有多個有效的退出狀態。
6.5 Bi-directional Data Lane Turnaround 6.5 雙向數據通道轉換
The transmission direction of a bi-directional Data Lane can be swapped by means of a Link Turnaround procedure. This procedure enables information transfer in the opposite direction of the current direction. The procedure is the same for either a change from Forward-to-Reverse direction or Reverse-to-Forward direction. Notice that Master and Slave side shall not be changed by Turnaround. Link Turnaround shall be handled completely in Control mode. Table 6 lists the sequence of events during Turnaround. 雙向數據通道的傳輸方向可以通過鏈路轉換程序進行切換。此程序使信息能夠以與當前方向相反的方向進行傳輸。無論是從前向轉為反向還是從反向轉為前向，程序都是相同的。請注意，主端和從端在轉換過程中不應改變。鏈路轉換應完全在控制模式下處理。表 6 列出了轉換過程中的事件序列。
Table 6 Link Turnaround Sequence 表 6 連結周轉序列
Initial TX Side = Final RX Side 初始 TX 端 = 最終 RX 端
Initial RX Side = Final TX Side 初始 RX 端 = 最終 TX 端
Drives Stop state (LP-11) 驅動器停止狀態 (LP-11)
Observes Stop state 觀察停止狀態
Drives LP-Rqst state (LP-10) for a time TLPX 驅動 LP-Rqst 狀態 (LP-10) 持續時間 TLPX
Observes transition from LP-11 to LP-10 states 觀察從 LP-11 到 LP-10 狀態的過渡
Drives Bridge state (LP-00) for a time T TPX 驅動橋狀態 (LP-00) 持續時間 T TPX
Observes transition from LP-10 to LP-00 states 觀察從 LP-10 到 LP-00 狀態的過渡
Drives LP-10 for a time T TPX 驅動器 LP-10 持續時間 T TPX
Observes transition from LP-00 to LP-10 states 觀察從 LP-00 到 LP-10 狀態的過渡
Drives Bridge state (LP-00) for a time TTA-GO 驅動橋樑狀態 (LP-00) 持續時間 TTA-GO
Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control.
Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control.| Observes the transition from LP-10 to Bridge state |
| :--- |
| and waits for a time TAA-SURE. After correct |
| completion of this time-out this side knows it is in |
| control. |
停止駕駛線路，並使用其 LP-RX 觀察線路狀態，以便查看確認。
Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement.
Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement.| Stops driving the Lines and observes the Line states |
| :--- |
| with its LP-RX in order to see an acknowledgement. |
Drives Bridge state (LP-00) for a period TTA-GET 驅動橋樑狀態 (LP-00) 持續時間 TTA-GET
Drives LP-10 for a period TLPX 驅動器 LP-10 持續時間 TLPX
觀察 LP-10 在線上，解釋為承認對方確實已經掌控。等待停止狀態完成周轉程序。
Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure.
Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure.| Observes LP-10 on the Lines, interprets this as |
| :--- |
| acknowledge that the other side has indeed taken |
| control. Waits for Stop state to complete Turnaround |
| procedure. |
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Drives Stop state (LP-11) Observes Stop state
Drives LP-Rqst state (LP-10) for a time TLPX Observes transition from LP-11 to LP-10 states
Drives Bridge state (LP-00) for a time T TPX Observes transition from LP-10 to LP-00 states
Drives LP-10 for a time T TPX Observes transition from LP-00 to LP-10 states
Drives Bridge state (LP-00) for a time TTA-GO "Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control."
"Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement." Drives Bridge state (LP-00) for a period TTA-GET
Drives LP-10 for a period TLPX
"Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure." | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives LP-Rqst state (LP-10) for a time TLPX | Observes transition from LP-11 to LP-10 states |
| Drives Bridge state (LP-00) for a time T TPX | Observes transition from LP-10 to LP-00 states |
| Drives LP-10 for a time T TPX | Observes transition from LP-00 to LP-10 states |
| Drives Bridge state (LP-00) for a time TTA-GO | Observes the transition from LP-10 to Bridge state <br> and waits for a time TAA-SURE. After correct <br> completion of this time-out this side knows it is in <br> control. |
| Stops driving the Lines and observes the Line states <br> with its LP-RX in order to see an acknowledgement. | Drives Bridge state (LP-00) for a period TTA-GET |
| | Drives LP-10 for a period TLPX |
| Observes LP-10 on the Lines, interprets this as <br> acknowledge that the other side has indeed taken <br> control. Waits for Stop state to complete Turnaround <br> procedure. | |
Initial TX Side = Final RX Side 初始 TX 端 = 最終 RX 端
Initial RX Side = Final TX Side 初始 RX 端 = 最終 TX 端
Observes transition to Stop state (LP-11) on the 觀察到轉換到停止狀態（LP-11）在
Lines, interprets this as Turnaround completion 轉彎完成
acknowledgement, switches to normal LP receive 確認，切換到正常的 LP 接收
mode and waits for further actions from the other 模式並等待其他人的進一步行動
side 側面
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Observes transition to Stop state (LP-11) on the
Lines, interprets this as Turnaround completion
acknowledgement, switches to normal LP receive
mode and waits for further actions from the other
side | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Observes transition to Stop state (LP-11) on the | |
| Lines, interprets this as Turnaround completion | |
| acknowledgement, switches to normal LP receive | |
| mode and waits for further actions from the other | |
| side | |
Figure 16 shows the Turnaround procedure graphically. 圖 16 以圖形方式顯示了周轉程序。
Figure 16 Turnaround Procedure 圖 16 轉向程序
The Low-Power clock timing for both sides of the Link does not have to be the same, but may differ. However, the ratio between the Low-Power State Periods, T_("LPX ")\mathrm{T}_{\text {LPX }}, is constrained to ensure proper Turnaround behavior. See Table 14 for the ratio of T_("LPX(MASTER) ")\mathrm{T}_{\text {LPX(MASTER) }} to T_("LPX(SLAVE) ")\mathrm{T}_{\text {LPX(SLAVE) }}. 鏈路兩側的低功耗時鐘定時不必相同，但可以有所不同。然而，低功耗狀態周期之間的比率 T_("LPX ")\mathrm{T}_{\text {LPX }} 受到限制，以確保適當的轉換行為。請參見表 14 以獲取 T_("LPX(MASTER) ")\mathrm{T}_{\text {LPX(MASTER) }} 與 T_("LPX(SLAVE) ")\mathrm{T}_{\text {LPX(SLAVE) }} 的比率。
The Turnaround procedure can be interrupted if the Lane is not yet driven into TX-LP-Yield by means of driving a Stop state. Driving the Stop state shall abort the Turnaround procedure and return the Lane to the Stop state. The PHY shall ensure against interruption of the procedure after the end of TX-TA-Rqst, RX-TA-Rqst, or TX-TA-GO. Once the PHY drives TX-LP-Yield, it shall not abort the Turnaround procedure. The Protocol may take appropriate action if it determines an error has occurred because the Turnaround procedure did not complete within a certain time. See Section 7.3.5 for more details. Figure 17 shows the Turnaround state machine that is described in Table 7. 如果尚未駛入 TX-LP-Yield，則可以通過駛入停止狀態來中斷回轉程序。駛入停止狀態將中止回轉程序並將車道返回到停止狀態。PHY 應確保在 TX-TA-Rqst、RX-TA-Rqst 或 TX-TA-GO 結束後不會中斷該程序。一旦 PHY 驅動 TX-LP-Yield，則不應中止回轉程序。如果協議確定因回轉程序未在特定時間內完成而發生錯誤，則可以採取適當行動。更多詳細信息請參見第 7.3.5 節。圖 17 顯示了在表 7 中描述的回轉狀態機。
Note: Horizontally aligned states occur simultaneously. 注意：水平對齊的狀態同時發生。
Figure 17 Turnaround State Machine 圖 17 轉換狀態機
Table 7 Turnaround State Machine Description 表 7 轉換狀態機描述
State 州
線條狀態
Line
Condition/State
Line
Condition/State| Line |
| :---: |
| Condition/State |
Exit State 退出狀態
Exit Conditions 退出條件
Any RX state 任何 RX 狀態
Any Received 任何收到的
RX-Stop
Observe LP-11 at Lines 觀察 LP-11 在行上
TX-Stop
Transmit LP-11 傳輸 LP-11
TX-LP-Rqst
On request of Protocol for Turnaround 根據周轉協議的要求
TX-LP-Rqst
Transmit LP-10 傳輸 LP-10
TX-LP-Yield TX-LP-產量
End of timed interval TLPX 結束計時區間 TLPX
TX-LP-Yield TX-LP-產量
Transmit LP-00 傳輸 LP-00
TX-TA-Rqst
End of timed interval TLPX 結束計時區間 TLPX
TX-TA-Rqst
Transmit LP-10 傳輸 LP-10
TX-TA-Go
End of timed interval TLPX 結束計時區間 TLPX
TX-TA-Go
Transmit LP-00 傳輸 LP-00
RX-TA-Look
End of timed interval TTA-GO 計時區間結束 TTA-GO
RX-TA-Look
Receive LP-00 接收 LP-00
RX-TA-Ack
Line transition to LP-10 線路過渡到 LP-10
RX-TA-Ack
Receive LP-10 接收 LP-10
RX-Stop
Line transition to LP-11 線路過渡到 LP-11
RX-Stop
Receive LP-11 接收 LP-11
RX-LP-Rqst
Line transition to LP-10 線路過渡到 LP-10
RX-LP-Rqst
Receive LP-10 接收 LP-10
RX-LP-Yield
Line transition to LP-00 線路過渡到 LP-00
RX-LP-Yield
Receive LP-00 接收 LP-00
RX-TA-Rqst
Line transition to LP-10 線路過渡到 LP-10
RX-TA-Rqst
Receive LP-10 接收 LP-10
RX-TA-Wait
Line transition to LP-00 線路過渡到 LP-00
RX-TA-Wait
Receive LP-00 接收 LP-00
TX-TA-Get
End of timed interval TTA-SURE 定時區間結束 TTA-SURE
TX-TA-Get
Transmit LP-00 傳輸 LP-00
TX-TA-Ack
End of timed interval TTA-GET 計時區間結束 TTA-GET
TX-TA-Ack
Transit LP-10
TX-Stop
End of timed interval TLPX 結束計時區間 TLPX
State "Line
Condition/State" Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Turnaround
TX-LP-Rqst Transmit LP-10 TX-LP-Yield End of timed interval TLPX
TX-LP-Yield Transmit LP-00 TX-TA-Rqst End of timed interval TLPX
TX-TA-Rqst Transmit LP-10 TX-TA-Go End of timed interval TLPX
TX-TA-Go Transmit LP-00 RX-TA-Look End of timed interval TTA-GO
RX-TA-Look Receive LP-00 RX-TA-Ack Line transition to LP-10
RX-TA-Ack Receive LP-10 RX-Stop Line transition to LP-11
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-TA-Rqst Line transition to LP-10
RX-TA-Rqst Receive LP-10 RX-TA-Wait Line transition to LP-00
RX-TA-Wait Receive LP-00 TX-TA-Get End of timed interval TTA-SURE
TX-TA-Get Transmit LP-00 TX-TA-Ack End of timed interval TTA-GET
TX-TA-Ack Transit LP-10 TX-Stop End of timed interval TLPX| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Turnaround |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | End of timed interval TLPX |
| TX-LP-Yield | Transmit LP-00 | TX-TA-Rqst | End of timed interval TLPX |
| TX-TA-Rqst | Transmit LP-10 | TX-TA-Go | End of timed interval TLPX |
| TX-TA-Go | Transmit LP-00 | RX-TA-Look | End of timed interval TTA-GO |
| RX-TA-Look | Receive LP-00 | RX-TA-Ack | Line transition to LP-10 |
| RX-TA-Ack | Receive LP-10 | RX-Stop | Line transition to LP-11 |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-TA-Rqst | Line transition to LP-10 |
| RX-TA-Rqst | Receive LP-10 | RX-TA-Wait | Line transition to LP-00 |
| RX-TA-Wait | Receive LP-00 | TX-TA-Get | End of timed interval TTA-SURE |
| TX-TA-Get | Transmit LP-00 | TX-TA-Ack | End of timed interval TTA-GET |
| TX-TA-Ack | Transit LP-10 | TX-Stop | End of timed interval TLPX |
Note: 注意：
During RX-TA-Look, the protocol may cause the PHY to transition to TX-Stop. 在 RX-TA-Look 期間，協議可能會導致 PHY 轉換到 TX-Stop。
During High-Speed data transmission, Stop states (TX-Stop, RX-Stop) have multiple valid exit states. 在高速數據傳輸期間，停止狀態（TX-Stop，RX-Stop）具有多個有效的退出狀態。
6.6 Escape Mode 6.6 逃脫模式
Escape mode is a special mode of operation for Data Lanes using Low-Power states. With this mode some additional functionality becomes available. Escape mode operation shall be supported in the Forward direction and is optional in the Reverse direction. If supported, Escape mode does not have to include all available features. 逃逸模式是數據通道使用低功耗狀態的一種特殊操作模式。在此模式下，某些額外功能變得可用。逃逸模式操作應在前向方向上得到支持，而在反向方向上則是可選的。如果支持，逃逸模式不必包含所有可用功能。
A Data Lane shall enter Escape mode via an Escape mode Entry procedure (LP-11, LP-10, LP-00, LP-01, LP-00). As soon as the final Bridge state (LP-00) is observed on the Lines the Lane shall enter Escape mode in Space state (LP-00). If an LP-11 is detected at any time before the final Bridge state (LP-00), the Escape mode Entry procedure shall be aborted and the receive side shall wait for, or return to, the Stop state. 數據通道應通過逃逸模式進入程序（LP-11、LP-10、LP-00、LP-01、LP-00）進入逃逸模式。一旦在線路上觀察到最終橋接狀態（LP-00），通道應進入空間狀態的逃逸模式（LP-00）。如果在最終橋接狀態（LP-00）之前的任何時候檢測到 LP-11，則逃逸模式進入程序應中止，接收端應等待或返回停止狀態。
For Data Lanes, once Escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested action. Table 8 lists all currently available Escape mode commands and actions. All unassigned commands are reserved for future expansion. 對於數據通道，一旦進入逃脫模式，發射器應發送一個 8 位的進入命令以指示所請求的操作。表 8 列出了所有當前可用的逃脫模式命令和操作。所有未分配的命令保留用於未來擴展。
The Stop state shall be used to exit Escape mode and cannot occur during Escape mode operation because of the Spaced-One-Hot encoding. Stop state immediately returns the Lane to Control mode. If the entry command doesn’t match a supported command, that particular Escape mode action shall be ignored and the receive side waits until the transmit side returns to the Stop state. 停止狀態將用於退出逃逸模式，並且在逃逸模式操作期間不能發生，因為使用了間隔一熱編碼。停止狀態會立即將通道返回到控制模式。如果進入命令與支持的命令不匹配，則該特定的逃逸模式操作將被忽略，接收端將等待直到發送端返回到停止狀態。
The PHY in Escape mode shall apply Spaced-One-Hot bit encoding for asynchronous communication. Therefore, operation of a Data Lane in this mode does not depend on the Clock Lane. The complete Escape mode action for a Trigger-Reset command is shown in Figure 18. 在逃逸模式下，PHY 將應用間隔一熱位元編碼進行非同步通信。因此，在此模式下，數據通道的操作不依賴於時鐘通道。觸發重置命令的完整逃逸模式操作如圖 18 所示。
Figure 18 Trigger-Reset Command in Escape Mode 圖 18 逃脫模式下的觸發重置命令
Spaced-One-Hot coding means that each Mark state is interleaved with a Space state. Each symbol consists therefore of two parts: a One-Hot phase (Mark-0 or Mark-1) and a Space phase. The TX shall send Mark-0 followed by a Space to transmit a ‘zero-bit’ and it shall send a Mark-1 followed by a Space to transmit a ‘one-bit’. A Mark that is not followed by a Space does not represent a bit. The last phase before exiting Escape mode with a Stop state shall be a Mark-1 state that is not part of the communicated bits, as it is not followed by a Space state. The Clock can be derived from the two Line signals, Dp and Dn, by means of an exclusive-OR function. The length of each individual LP state period shall be at least T_("LPX,MIN ")\mathrm{T}_{\text {LPX,MIN }}. Spaced-One-Hot 編碼意味著每個標記狀態與空白狀態交錯。每個符號因此由兩部分組成：一個 One-Hot 階段（標記-0 或標記-1）和一個空白階段。TX 應該發送標記-0，然後是空白，以傳輸‘零位’，並且應該發送標記-1，然後是空白，以傳輸‘一位’。未跟隨空白的標記不代表位。在退出逃逸模式之前的最後階段應該是標記-1 狀態，這不是傳輸的位的一部分，因為它不跟隨空白狀態。時鐘可以通過排他性或函數從兩個線信號 Dp 和 Dn 中導出。每個單獨的 LP 狀態週期的長度應至少為 T_("LPX,MIN ")\mathrm{T}_{\text {LPX,MIN }} 。
Escape Mode Action 逃脫模式動作
Command Type 命令類型
輸入命令模式（從第一位傳輸到最後一位傳輸）
Entry Command Pattern (first
bit transmitted to last bit
transmitted)
Entry Command Pattern (first
bit transmitted to last bit
transmitted)| Entry Command Pattern (first |
| :---: |
| bit transmitted to last bit |
| transmitted) |
Low-Power Data Transmission 低功耗數據傳輸
mode 模式
11100001
Ultra-Low Power State 超低功耗狀態
mode 模式
00011110
Undefined-1
mode 模式
10011111
Undefined-2
mode 模式
11011110
Reset-Trigger 重置觸發器
Reset-Trigger| Reset-Trigger |
| :--- |
Trigger 觸發器
01100010
Entry sequence for HS Test Mode HS 測試模式的進入序列
Trigger 觸發器
01011101
Unknown-4
Trigger 觸發器
00100001
Unknown-5
Trigger 觸發器
10100000
Escape Mode Action Command Type "Entry Command Pattern (first
bit transmitted to last bit
transmitted)"
Low-Power Data Transmission mode 11100001
Ultra-Low Power State mode 00011110
Undefined-1 mode 10011111
Undefined-2 mode 11011110
"Reset-Trigger" Trigger 01100010
Entry sequence for HS Test Mode Trigger 01011101
Unknown-4 Trigger 00100001
Unknown-5 Trigger 10100000| Escape Mode Action | Command Type | Entry Command Pattern (first <br> bit transmitted to last bit <br> transmitted) |
| :--- | :--- | :---: |
| Low-Power Data Transmission | mode | 11100001 |
| Ultra-Low Power State | mode | 00011110 |
| Undefined-1 | mode | 10011111 |
| Undefined-2 | mode | 11011110 |
| Reset-Trigger | Trigger | 01100010 |
| Entry sequence for HS Test Mode | Trigger | 01011101 |
| Unknown-4 | Trigger | 00100001 |
| Unknown-5 | Trigger | 10100000 |
6.6.1 Remote Triggers 6.6.1 遠程觸發器
Trigger signaling is the mechanism to send a flag to the protocol at the receiving side, on request of the protocol on the transmitting side. This can be either in the Forward or Reverse direction depending on the direction of operation and available Escape mode functionality. Trigger signaling requires Escape mode capability and at least one matching Trigger Escape Entry Command on both sides of the interface. 觸發信號是向接收端協議發送標誌的機制，根據發送端協議的請求。這可以根據操作方向和可用的逃逸模式功能，向前或向後進行。觸發信號需要逃逸模式能力，並且在接口的兩側至少需要一個匹配的觸發逃逸條目命令。
Figure 18 shows an example of an Escape mode Reset-Trigger action. The Lane enters Escape mode via the Escape mode Entry procedure. If the Entry Command Pattern matches the Reset-Trigger Command a Trigger is flagged to the protocol at the receive side via the logical PPI. Any bit received after a Trigger Command but before the Lines go to Stop state shall be ignored. Therefore, dummy bytes can be concatenated in order to provide Clock information to the receive side. 圖 18 顯示了逃逸模式重置觸發動作的示例。通道通過逃逸模式進入程序進入逃逸模式。如果進入命令模式與重置觸發命令匹配，則觸發器將通過邏輯 PPI 標記到接收端的協議。任何在觸發命令之後但在通道進入停止狀態之前接收到的位都應被忽略。因此，可以串接虛擬位元組以向接收端提供時鐘信息。
Note that Trigger signaling including Reset-Trigger is a generic messaging system. The Trigger commands do not impact the behavior of the PHY itself. Therefore, Triggers can be used for any purpose by the Protocol layer. 請注意，觸發信號（包括重置觸發）是一種通用消息系統。觸發命令不會影響物理層本身的行為。因此，協議層可以將觸發用於任何目的。
6.6.2 Low-Power Data Transmission 6.6.2 低功耗數據傳輸
If the Escape mode Entry procedure is followed-up by the Entry Command for Low-Power Data Transmission (LPDT), Data can be communicated by the protocol at low speed, while the Lane remains in Low-Power mode. 如果遵循逃逸模式進入程序，然後執行低功耗數據傳輸（LPDT）的進入命令，則可以通過協議以低速傳輸數據，同時通道保持在低功耗模式。
Data shall be encoded on the lines with the same Spaced-One-Hot code as used for the Entry Commands. The data is self-clocked by the applied bit encoding and does not rely on the Clock Lane. The Lane can pause while using LPDT by maintaining a Space state on the Lines. A Stop state on the Lines stops LPDT, exits Escape mode, and switches the Lane to Control mode. The last phase before Stop state shall be a Mark-1 state, which does not represent a data-bit. Figure 19 shows a two-byte transmission with a pause period between the two bytes. 數據應該使用與進入命令相同的間隔一熱碼編碼在行上。數據由施加的位編碼自我時鐘，並不依賴於時鐘通道。在使用 LPDT 時，通道可以通過在行上保持空間狀態來暫停。在行上的停止狀態會停止 LPDT，退出逃逸模式，並將通道切換到控制模式。在停止狀態之前的最後階段應該是標記 1 狀態，這不代表數據位。圖 19 顯示了兩字節傳輸，兩字節之間有一個暫停期。
Figure 19 Two Data Byte Low-Power Data Transmission Example 圖 19 兩個數據字節低功耗數據傳輸示例
Using LPDT, a Low-Power (Bit) Clock signal ( f_("MOMENTARY ") < 20MHz\mathrm{f}_{\text {MOMENTARY }}<20 \mathrm{MHz} ) provided to the transmit side is used to transmit data. Data reception is self-timed by the bit encoding. Therefore, a variable clock rate can be allowed. At the end of LPDT the Lane shall return to the Stop state. 使用 LPDT，提供給發送端的低功耗（位元）時鐘信號（ f_("MOMENTARY ") < 20MHz\mathrm{f}_{\text {MOMENTARY }}<20 \mathrm{MHz} ）用於傳輸數據。數據接收由位元編碼自我定時。因此，可以允許變化的時鐘速率。在 LPDT 結束時，通道應返回到停止狀態。
6.6.3 Ultra-Low Power State 6.6.3 超低功耗狀態
If the Ultra-Low Power State Entry Command is sent after an Escape mode Entry command, the Lane shall enter the Ultra-Low Power State (ULPS). This command shall be flagged to the receive side Protocol. During this state, the Lines are in the Space state (LP-00). Ultra-Low Power State is exited by means of a Mark-1 state with a length Twakeup followed by a Stop state. Annex A describes an example of an exit procedure and a procedure to control the length of time spent in the Mark-1 state. 如果在逃逸模式進入命令之後發送超低功耗狀態進入命令，則通道應進入超低功耗狀態（ULPS）。此命令應標記給接收方協議。在此狀態下，線路處於空間狀態（LP-00）。超低功耗狀態的退出是通過一個長度為 Twakeup 的 Mark-1 狀態，然後是停止狀態。附錄 A 描述了一個退出程序的示例以及控制在 Mark-1 狀態中花費時間長度的程序。
6.6.4 Escape Mode State Machine 6.6.4 逃逸模式狀態機
The state machine for Escape mode operation is shown in Figure 20 and described in Table 9. 逃脫模式操作的狀態機如圖 20 所示，並在表 9 中描述。
Note: Horizontally aligned states occur simultaneously. 注意：水平對齊的狀態同時發生。
Figure 20 Escape Mode State Machine 圖 20 逃脫模式狀態機
Table 9 Escape Mode State Machine Description 表 9 逃脫模式狀態機描述
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
Any RX state 任何 RX 狀態
Any Received 任何收到的
RX-Stop
Observe LP-11 at Lines 觀察 LP-11 在行上
TX-Stop
Transmit LP-11 傳輸 LP-11
TX-LP-Rqst
On request of Protocol for Esc mode (PPI) 根據對 Esc 模式（PPI）協議的要求
TX-LP-Rqst
Transmit LP-10 傳輸 LP-10
TX-LP-Yield TX-LP-產量
After time T_("LPX ")\mathrm{T}_{\text {LPX }} 在時間 T_("LPX ")\mathrm{T}_{\text {LPX }} 之後
TX-LP-Yield TX-LP-產量
Transmit LP-00 傳輸 LP-00
TX-Esc-Rqst
After time T TPX
TX-Esc-Rqst
Transmit LP-01 傳輸 LP-01
TX-Esc-Go
After time T LPX^("a ")\mathrm{LPX}^{\text {a }} 在時間 T LPX^("a ")\mathrm{LPX}^{\text {a }} 之後
After Low-Power Data
Transmission Command| After Low-Power Data |
| :--- |
| Transmission Command |
TX-Triggers
Space state or optional dummy bytes for the purpose of generating clocks 空白狀態或可選的虛擬位元組，用於生成時鐘
TX-Mark
Exit of the Trigger State on request of Protocol (PPI) 根據協議（PPI）要求觸發狀態的退出
TX-ULPS
Transmit LP-00 傳輸 LP-00
TX-Mark
End of ULP State on request of Protocol (PPI) 根據協議（PPI）要求的 ULP 狀態結束
State Line Condition/State Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Esc mode (PPI)
TX-LP-Rqst Transmit LP-10 TX-LP-Yield After time T_("LPX ")
TX-LP-Yield Transmit LP-00 TX-Esc-Rqst After time T TPX
TX-Esc-Rqst Transmit LP-01 TX-Esc-Go After time T LPX^("a ")
TX-Esc-Go Transmit LP-00 TX-Esc-Cond After time T TPX
TX-Esc-Cmd Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command TX-Triggers After a Trigger Command
TX-ULPS After Ultra-Low Power Command
TX-LPDT "After Low-Power Data
Transmission Command"
TX-Triggers Space state or optional dummy bytes for the purpose of generating clocks TX-Mark Exit of the Trigger State on request of Protocol (PPI)
TX-ULPS Transmit LP-00 TX-Mark End of ULP State on request of Protocol (PPI)| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Esc mode (PPI) |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | After time $\mathrm{T}_{\text {LPX }}$ |
| TX-LP-Yield | Transmit LP-00 | TX-Esc-Rqst | After time T TPX |
| TX-Esc-Rqst | Transmit LP-01 | TX-Esc-Go | After time T $\mathrm{LPX}^{\text {a }}$ |
| TX-Esc-Go | Transmit LP-00 | TX-Esc-Cond | After time T TPX |
| TX-Esc-Cmd | Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | TX-Triggers | After a Trigger Command |
| | | TX-ULPS | After Ultra-Low Power Command |
| | | TX-LPDT | After Low-Power Data <br> Transmission Command |
| TX-Triggers | Space state or optional dummy bytes for the purpose of generating clocks | TX-Mark | Exit of the Trigger State on request of Protocol (PPI) |
| TX-ULPS | Transmit LP-00 | TX-Mark | End of ULP State on request of Protocol (PPI) |
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
TX-LPDT
Transmit serialized, Spaced-One-Hot encoded payload data 傳輸序列化的、空間一熱編碼的有效載荷數據
After last transmitted data bit 最後傳輸的數據位之後
TX-Mark
Mark-1
TX-Stop
Next driven state after time T_("LPX ")\mathrm{T}_{\text {LPX }}, or T_("WAKEUP ")\mathrm{T}_{\text {WAKEUP }} if leaving ULP State 下一個驅動狀態在時間 T_("LPX ")\mathrm{T}_{\text {LPX }} 之後，或在離開 ULP 狀態時為 T_("WAKEUP ")\mathrm{T}_{\text {WAKEUP }}
After Trigger and Unrecognized Commands 觸發後和未識別的命令
RX-ULPS
After Ultra-Low Power Command 超低功耗命令後
RX-LPDT
After Low-Power Data Transmission Command 低功耗數據傳輸命令之後
RX-ULPS
Receive LP-00 接收 LP-00
RX-Wait
Line transition to LP-10 線路過渡到 LP-10
RX-LPDT
Receive serial, Spaced-One-Hot encoded payload data 接收序列，空間一熱編碼的有效載荷數據
RX-Stop
Line transition to LP-11 (Last state should be a Mark-1) 行轉換至 LP-11（最後狀態應為 Mark-1）
RX-Wait
Any, except LP-11 任何，除了 LP-11
RX-Stop
Line transition to LP-11 線路過渡到 LP-11
State Line Condition/State Exit State Exit Conditions
TX-LPDT Transmit serialized, Spaced-One-Hot encoded payload data After last transmitted data bit
TX-Mark Mark-1 TX-Stop Next driven state after time T_("LPX "), or T_("WAKEUP ") if leaving ULP State
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-Esc-Rqst Line transition to LP-01
RX-Esc-Rqst Receive LP-01 RX-Esc-Go Line transition to LP-00
RX-Esc-Go Receive LP-00 RX-Esc-Cmd Line transition out of LP-00
RX-Esc-Cmd Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command RX-Wait After Trigger and Unrecognized Commands
RX-ULPS After Ultra-Low Power Command
RX-LPDT After Low-Power Data Transmission Command
RX-ULPS Receive LP-00 RX-Wait Line transition to LP-10
RX-LPDT Receive serial, Spaced-One-Hot encoded payload data RX-Stop Line transition to LP-11 (Last state should be a Mark-1)
RX-Wait Any, except LP-11 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| TX-LPDT | Transmit serialized, Spaced-One-Hot encoded payload data | | After last transmitted data bit |
| TX-Mark | Mark-1 | TX-Stop | Next driven state after time $\mathrm{T}_{\text {LPX }}$, or $\mathrm{T}_{\text {WAKEUP }}$ if leaving ULP State |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-Esc-Rqst | Line transition to LP-01 |
| RX-Esc-Rqst | Receive LP-01 | RX-Esc-Go | Line transition to LP-00 |
| RX-Esc-Go | Receive LP-00 | RX-Esc-Cmd | Line transition out of LP-00 |
| RX-Esc-Cmd | Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | RX-Wait | After Trigger and Unrecognized Commands |
| | | RX-ULPS | After Ultra-Low Power Command |
| | | RX-LPDT | After Low-Power Data Transmission Command |
| RX-ULPS | Receive LP-00 | RX-Wait | Line transition to LP-10 |
| RX-LPDT | Receive serial, Spaced-One-Hot encoded payload data | RX-Stop | Line transition to LP-11 (Last state should be a Mark-1) |
| RX-Wait | Any, except LP-11 | RX-Stop | Line transition to LP-11 |
6.7 High-Speed Clock Transmission 6.7 高速時鐘傳輸
In High-Speed mode the Clock Lane provides a low-swing, differential DDR (half-rate) clock signal from Master to Slave for High-Speed Data Transmission. The Clock signal shall have quadrature-phase with respect to a toggling bit sequence on a Data Lane in the Forward direction and a rising edge in the center of the first transmitted bit of a burst. Details of the Data-Clock relationship and timing specifications can be found in Section 10. 在高速模式下，時鐘通道從主設備到從設備提供低擺幅、差分 DDR（半速）時鐘信號，以進行高速數據傳輸。時鐘信號應與前向方向數據通道上的切換位序列具有正交相位，並在第一個傳輸位的突發中心處有上升沿。數據與時鐘之間的關係及時間規範的詳細信息可以在第 10 節中找到。
A Clock Lane is similar to a Unidirectional Data Lane. However, there are some timing differences and a Clock Lane transmits a High-Speed DDR clock signal instead of data bits. Furthermore, the Low-Power mode functionality is defined differently for a Clock Lane than a Data Lane. A Clock Lane shall be unidirectional and shall not include regular Escape mode functionality. Only ULPS shall be supported via a special entry sequence using the LP-Rqst state. High-Speed Clock Transmission shall start from, and exit to, a Stop state. 時鐘通道類似於單向數據通道。然而，存在一些時序差異，時鐘通道傳輸的是高速 DDR 時鐘信號，而不是數據位。此外，低功耗模式的功能在時鐘通道和數據通道之間的定義也不同。時鐘通道應為單向，並且不應包括常規的逃逸模式功能。僅支持通過使用 LP-Rqst 狀態的特殊進入序列來實現 ULPS。高速時鐘傳輸應從停止狀態開始，並返回到停止狀態。
The Clock Lane module is controlled by the Protocol via the Clock Lane PPI. The Protocol shall only stop the Clock Lane when there are no High-Speed transmissions active in any Data Lane. 時鐘通道模組由協議通過時鐘通道 PPI 控制。當任何數據通道中沒有高速度傳輸活動時，協議才會停止時鐘通道。
The High-Speed Data Transmission start-up time of a Data Lane is extended if the Clock Lane is in LowPower mode. In that case the Clock Lane shall first return to High-Speed operation before the Transmit Request can be handled. 如果時鐘通道處於低功耗模式，數據通道的高速數據傳輸啟動時間將延長。在這種情況下，時鐘通道必須首先恢復到高速操作，然後才能處理傳輸請求。
The High-Speed Clock signal shall continue running for a period T_("CLK-POsт ")\mathrm{T}_{\text {CLK-POsт }} after the last Data Lane switches to Low-Power mode and ends with a HS-0 state. The procedure for switching the Clock Lane to LowPower mode is given in Table 10. Note the Clock Burst always contains an even number of transitions as it 高速時鐘信號在最後一個數據通道切換到低功耗模式並以 HS-0 狀態結束後，應持續運行一段時間 T_("CLK-POsт ")\mathrm{T}_{\text {CLK-POsт }} 。切換時鐘通道到低功耗模式的程序見表 10。請注意，時鐘突發始終包含偶數次轉換，因為它
559 starts and ends with a HS-0 state. This implies that the clock provides transitions to sample an even number of bits on any associated Data Lanes. Clock periods shall be reliable and according to the HS timing specifications. The procedure to return the Clock Lane to High-Speed Clock Transmission is given in Table 11. Both Clock Start and Stop procedures are shown in Figure 21. 559 以 HS-0 狀態開始和結束。這意味著時鐘提供轉換以在任何相關數據通道上取樣偶數位元。時鐘週期應可靠並符合 HS 時序規範。將時鐘通道返回到高速時鐘傳輸的程序見表 11。時鐘啟動和停止程序顯示在圖 21 中。
Figure 21 Switching the Clock Lane between Clock Transmission and Low-Power Mode 圖 21 在時鐘傳輸和低功耗模式之間切換時鐘通道
Table 10 Procedure to Switch Clock Lane to Low-Power Mode 表 10 切換時鐘通道至低功耗模式的程序
Master Side 主側
Slave Side 奴隸端
驅動高速時鐘信號（切換 HS-0/HS-1）
Drives High-Speed Clock signal (Toggling
HS-0/HS-1)
Drives High-Speed Clock signal (Toggling
HS-0/HS-1)| Drives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
接收高速時鐘信號（切換 HS-0/HS-1）
Receives High-Speed Clock signal (Toggling
HS-0/HS-1)
Receives High-Speed Clock signal (Toggling
HS-0/HS-1)| Receives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
Last Data Lane goes into Low-Power mode 最後數據通道進入低功耗模式
持續驅動高速度時鐘信號一段時間 TcLK-Post，並以 HS-0 狀態結束
Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state
Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state| Continues to drives High-Speed Clock signal for a |
| :--- |
| period TcLK-Post and ends with HS-0 state |
檢測在時間 TcLK-MISs 內缺少時鐘轉換，禁用 HS-RX，然後等待轉換到停止狀態
Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state
Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state| Detects absence of Clock transitions within a time |
| :--- |
| TcLK-MISs, disables HS-RX then waits for a transition |
| to the Stop state |
Drives HS-0 for a time TcLK-TRAIL 驅動 HS-0 的時間 TcLK-TRAIL
禁用 HS-TX，啟用 LP-TX，並驅動停止狀態 (LP-11) 持續時間 THS-EXIT
Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT
Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
檢測到線路轉換到 LP-11，禁用 HS 終端，並進入停止狀態
Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state
Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state| Detects the Lines transitions to LP-11, disables HS |
| :--- |
| termination, and enters Stop state |
Master Side Slave Side
"Drives High-Speed Clock signal (Toggling
HS-0/HS-1)" "Receives High-Speed Clock signal (Toggling
HS-0/HS-1)"
Last Data Lane goes into Low-Power mode
"Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state" "Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state"
Drives HS-0 for a time TcLK-TRAIL
"Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state"
| Master Side | Slave Side |
| :--- | :--- |
| Drives High-Speed Clock signal (Toggling <br> HS-0/HS-1) | Receives High-Speed Clock signal (Toggling <br> HS-0/HS-1) |
| Last Data Lane goes into Low-Power mode | |
| Continues to drives High-Speed Clock signal for a <br> period TcLK-Post and ends with HS-0 state | Detects absence of Clock transitions within a time <br> TcLK-MISs, disables HS-RX then waits for a transition <br> to the Stop state |
| Drives HS-0 for a time TcLK-TRAIL | |
| Disables the HS-TX, enables LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines transitions to LP-11, disables HS <br> termination, and enters Stop state |
| | |
Drives HS-Req state (LP-01) for time TLPX 驅動 HS-Req 狀態 (LP-01) 於時間 TLPX
觀察從 LP-11 到 LP-01 的過渡情況
Observes transition from LP-11 to LP-01 on the
Lines
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
Drives Bridge state (LP-00) for time TcLK-PREPARE 驅動橋接狀態 (LP-00) 持續時間 TcLK-PREPARE
觀察從 LP-01 到 LP-00 的轉換。啟用在時間 TcLK-TERM-EN 之後的線路終止。
Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN
Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN| Observes transition from LP-01 to LP-00 on the |
| :--- |
| Lines. Enables Line Termination after time |
| TcLK-TERM-EN |
同時啟用高速驅動器並禁用低功耗驅動器。驅動 HS-0 持續時間為 TCLK-ZERO。
Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO.
Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO.| Enables High-Speed driver and disables Low-Power |
| :--- |
| drivers simultaneously. Drives HS-0 for a time |
| TCLK-ZERO. |
啟用 HS-RX 並等待計時器 TcLK-SETTLE 到期，以忽略過渡效應
Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects
Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer TcLK-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
Receives HS-signal 接收 HS 信號
在任何數據通道啟動之前，驅動高頻時鐘信號的時間周期為 TcLK-PRE
Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up
Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up| Drives the High-Speed Clock signal for time period |
| :--- |
| TcLK-PRE before any Data Lane starts up |
Receives High-Speed Clock signal 接收高速時鐘信號
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Req state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time TcLK-PREPARE "Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO." "Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects"
Receives HS-signal
"Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up" Receives High-Speed Clock signal| TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Req state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time TcLK-PREPARE | Observes transition from LP-01 to LP-00 on the <br> Lines. Enables Line Termination after time <br> TcLK-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. Drives HS-0 for a time <br> TCLK-ZERO. | Enables HS-RX and waits for timer TcLK-SETTLE to <br> expire in order to neglect transition effects |
| | Receives HS-signal |
| Drives the High-Speed Clock signal for time period <br> TcLK-PRE before any Data Lane starts up | Receives High-Speed Clock signal |
The Clock Lane state machine is shown in Figure 22 and is described in Table 12. 時鐘通道狀態機如圖 22 所示，並在表 12 中描述。
Note: Horizontally aligned states occur simultaneously. 注意：水平對齊的狀態同時發生。
Figure 22 High-Speed Clock Transmission State Machine 圖 22 高速時鐘傳輸狀態機
Table 12 Description of High-Speed Clock Transmission State Machine 表 12 高速時鐘傳輸狀態機的描述
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
TX-Stop
Transmit LP-11 傳輸 LP-11
TX-HS-Rqst
高速度傳輸協議的要求
On request of Protocol
for High-Speed
Transmission
On request of Protocol
for High-Speed
Transmission| On request of Protocol |
| :--- |
| for High-Speed |
| Transmission |
TX-HS-Rqst
Transmit LP-01 傳輸 LP-01
TX-HS-Prpr
定時區間 TLPx 結束
End of timed interval
TLPx
End of timed interval
TLPx| End of timed interval |
| :--- |
| TLPx |
TX-HS-Prpr
Transmit LP-00 傳輸 LP-00
TX-HS-Go
定時區間結束 TcLK-PREPARE
End of timed interval
TcLK-PREPARE
End of timed interval
TcLK-PREPARE| End of timed interval |
| :--- |
| TcLK-PREPARE |
TX-HS-Go
Transmit HS-0 傳輸 HS-0
TX-HS-1
定時間隔結束 TcLK-ZERO
End of timed interval
TcLK-ZERO
End of timed interval
TcLK-ZERO| End of timed interval |
| :--- |
| TcLK-ZERO |
TX-HS-0
Transmit HS-0 傳輸 HS-0
TX-HS-1
在 HS-0 階段之後發送 HS-1 階段：DDR 時鐘
Send a HS-1 phase after
a HS-0 phase: DDR
Clock
Send a HS-1 phase after
a HS-0 phase: DDR
Clock| Send a HS-1 phase after |
| :--- |
| a HS-0 phase: DDR |
| Clock |
TX-HS-1
Transmit HS-1 傳輸 HS-1
TX-HS-0
在 HS-1 階段之後發送 HS-0 階段：DDR 時鐘
Send a HS-0 phase after
a HS-1 phase: DDR
Clock
Send a HS-0 phase after
a HS-1 phase: DDR
Clock| Send a HS-0 phase after |
| :--- |
| a HS-1 phase: DDR |
| Clock |
Trail-HS-0
應要求將時鐘巷設置為低功耗模式
On request to put Clock
Lane in Low-Power
On request to put Clock
Lane in Low-Power| On request to put Clock |
| :--- |
| Lane in Low-Power |
Trail-HS-0
Transmit HS-0 傳輸 HS-0
TX-Stop
定時間隔結束 TcLK-TRAlL
End of timed interval
TcLK-TRAlL
End of timed interval
TcLK-TRAlL| End of timed interval |
| :--- |
| TcLK-TRAlL |
RX-Stop
Receive LP-11 接收 LP-11
RX-HS-Rqst
Line transition to LP-01 線路過渡到 LP-01
Line transition to LP-01| Line transition to LP-01 |
| :--- |
RX-HS-Rqst
Receive LP-01 接收 LP-01
RX-HS-Prpr
Line transition to LP-00 線路過渡到 LP-00
RX-HS-Prpr
Receive LP-00 接收 LP-00
RX-HS-Term
定時區間結束 TcLK-TERM-EN
End of timed interval
TcLK-TERM-EN
End of timed interval
TcLK-TERM-EN| End of timed interval |
| :--- |
| TcLK-TERM-EN |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol
for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr "End of timed interval
TLPx"
TX-HS-Prpr Transmit LP-00 TX-HS-Go "End of timed interval
TcLK-PREPARE"
TX-HS-Go Transmit HS-0 TX-HS-1 "End of timed interval
TcLK-ZERO"
TX-HS-0 Transmit HS-0 TX-HS-1 "Send a HS-1 phase after
a HS-0 phase: DDR
Clock"
TX-HS-1 Transmit HS-1 TX-HS-0 "Send a HS-0 phase after
a HS-1 phase: DDR
Clock"
Trail-HS-0 "On request to put Clock
Lane in Low-Power"
Trail-HS-0 Transmit HS-0 TX-Stop "End of timed interval
TcLK-TRAlL"
RX-Stop Receive LP-11 RX-HS-Rqst "Line transition to LP-01"
RX-HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00
RX-HS-Prpr Receive LP-00 RX-HS-Term "End of timed interval
TcLK-TERM-EN"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol <br> for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval <br> TLPx |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval <br> TcLK-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-1 | End of timed interval <br> TcLK-ZERO |
| TX-HS-0 | Transmit HS-0 | TX-HS-1 | Send a HS-1 phase after <br> a HS-0 phase: DDR <br> Clock |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-0 phase after <br> a HS-1 phase: DDR <br> Clock |
| | | Trail-HS-0 | On request to put Clock <br> Lane in Low-Power |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval <br> TcLK-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX-HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
| RX-HS-Prpr | Receive LP-00 | RX-HS-Term | End of timed interval <br> TcLK-TERM-EN |
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
RX-HS-Term
Receive LP-00 接收 LP-00
RX-HS-Clk
定時間隔結束 TCLK-SETTLE
End of timed interval
TCLK-SETTLE
End of timed interval
TCLK-SETTLE| End of timed interval |
| :--- |
| TCLK-SETTLE |
Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions| Time-out TCLK-MISs on the |
| :--- |
| period on the Clock |
| Lane without Clock |
| signal transitions |
RX-HS-End
Receive HS-0 接收 HS-0
RX-HS-Stop
Line transition to LP-11 線路過渡到 LP-11
State Line Condition/State Exit State Exit Conditions
RX-HS-Term Receive LP-00 RX-HS-Clk "End of timed interval
TCLK-SETTLE"
RX-HS-Clk "Receive DDR-Q Clock
signal" RX-Clk-End "Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions"
RX-HS-End Receive HS-0 RX-HS-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS-Term | Receive LP-00 | RX-HS-Clk | End of timed interval <br> TCLK-SETTLE |
| RX-HS-Clk | Receive DDR-Q Clock <br> signal | RX-Clk-End | Time-out TCLK-MISs on the <br> period on the Clock <br> Lane without Clock <br> signal transitions |
| RX-HS-End | Receive HS-0 | RX-HS-Stop | Line transition to LP-11 |
Note: 注意：
During High-Speed data transmission, Stop states (TX-Stop, RX-Stop) have multiple valid exit states. 在高速數據傳輸期間，停止狀態（TX-Stop，RX-Stop）具有多個有效的退出狀態。
6.8 Clock Lane Ultra-Low Power State 6.8 時鐘巷超低功耗狀態
Although a Clock Lane does not include regular Escape mode, the Clock Lane shall support the Ultra-Low Power State. 雖然時鐘通道不包括常規的逃逸模式，但時鐘通道應支持超低功耗狀態。
A Clock Lane shall enter Ultra-Low Power State via a Clock Lane Ultra-Low Power State Entry procedure. In this procedure, starting from Stop state, the transmit side shall drive TX-ULPS-Rqst State (LP-10) and then drive TX-ULPS State (LP-00). After this, the Clock Lane shall enter Ultra-Low Power State. If an error occurs, and an LP-01 or LP-11 is detected immediately after the TX-ULPS-Rqst state, the Ultra-Low Power State Entry procedure shall be aborted, and the receive side shall wait for, or return to, the Stop state, respectively. 時鐘通道應通過時鐘通道超低功耗狀態進入超低功耗狀態。在此程序中，從停止狀態開始，發送端應驅動 TX-ULPS-Rqst 狀態（LP-10），然後驅動 TX-ULPS 狀態（LP-00）。之後，時鐘通道應進入超低功耗狀態。如果發生錯誤，並且在 TX-ULPS-Rqst 狀態後立即檢測到 LP-01 或 LP-11，則應中止超低功耗狀態進入程序，接收端應分別等待或返回停止狀態。
The receiving PHY shall flag the appearance of ULP State to the receive side Protocol. During this state the Lines are in the ULP State (LP-00). Ultra-Low Power State is exited by means of a Mark-1 TX-ULPS-Exit State with a length Twakeup followed by a Stop State. Annex A describes an example of an exit procedure that allows control of the length of time spent in the Mark-1 TX-ULPS-Exit State. 接收 PHY 應向接收端協議標記 ULP 狀態的出現。在此狀態下，線路處於 ULP 狀態（LP-00）。超低功耗狀態通過一個長度為 Twakeup 的 Mark-1 TX-ULPS-Exit 狀態退出，隨後進入停止狀態。附錄 A 描述了一個退出程序的示例，該程序允許控制在 Mark-1 TX-ULPS-Exit 狀態中花費的時間長度。
Figure 23 Clock Lane Ultra-Low Power State State Machine 圖 23 時鐘通道超低功耗狀態機
Table 13 Clock Lane Ultra-Low Power State State Machine Description 表 13 時鐘巷超低功耗狀態狀態機描述
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
TX-Stop
Transmit LP-11 傳輸 LP-11
TX-ULPS-Rqst
根據超低功耗狀態的協議要求
On request of Protocol
for Ultra-Low Power
State
On request of Protocol
for Ultra-Low Power
State| On request of Protocol |
| :--- |
| for Ultra-Low Power |
| State |
TX-ULPS-Rqst
Transmit LP-10 傳輸 LP-10
TX-ULPS
結束計時區間 TLPX
End of timed interval
TLPX
End of timed interval
TLPX| End of timed interval |
| :--- |
| TLPX |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-ULPS-Rqst "On request of Protocol
for Ultra-Low Power
State"
TX-ULPS-Rqst Transmit LP-10 TX-ULPS "End of timed interval
TLPX"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-ULPS-Rqst | On request of Protocol <br> for Ultra-Low Power <br> State |
| TX-ULPS-Rqst | Transmit LP-10 | TX-ULPS | End of timed interval <br> TLPX |
State 州
Line Condition/State 線條狀態
Exit State 退出狀態
Exit Conditions 退出條件
TX-ULPS
Transmit LP-00 傳輸 LP-00
TX-ULPS-Exit
應協議要求離開超低功耗狀態
On request of Protocol
to leave Ultra-Low
Power State
On request of Protocol
to leave Ultra-Low
Power State| On request of Protocol |
| :--- |
| to leave Ultra-Low |
| Power State |
TX-ULPS-Exit
Transmit LP-10 傳輸 LP-10
TX-Stop
結束計時間隔 TwakEuP
End of timed interval
TwakEuP
End of timed interval
TwakEuP| End of timed interval |
| :--- |
| TwakEuP |
RX-Stop
Receive LP-11 接收 LP-11
RX-ULPS-Rqst
Line transition to LP-10 線路過渡到 LP-10
RX-ULPS-Rqst
Receive LP-10 接收 LP-10
RX-ULPS
Line transition to LP-00 線路過渡到 LP-00
RX-ULPS
Receive LP-00 接收 LP-00
RX-ULPS-Exit
Line transition to LP-10 線路過渡到 LP-10
RX-ULPS-Exit
Receive LP-10 接收 LP-10
RX-Stop
Line transition to LP-11 線路過渡到 LP-11
State Line Condition/State Exit State Exit Conditions
TX-ULPS Transmit LP-00 TX-ULPS-Exit "On request of Protocol
to leave Ultra-Low
Power State"
TX-ULPS-Exit Transmit LP-10 TX-Stop "End of timed interval
TwakEuP"
RX-Stop Receive LP-11 RX-ULPS-Rqst Line transition to LP-10
RX-ULPS-Rqst Receive LP-10 RX-ULPS Line transition to LP-00
RX-ULPS Receive LP-00 RX-ULPS-Exit Line transition to LP-10
RX-ULPS-Exit Receive LP-10 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-ULPS | Transmit LP-00 | TX-ULPS-Exit | On request of Protocol <br> to leave Ultra-Low <br> Power State |
| TX-ULPS-Exit | Transmit LP-10 | TX-Stop | End of timed interval <br> TwakEuP |
| RX-Stop | Receive LP-11 | RX-ULPS-Rqst | Line transition to LP-10 |
| RX-ULPS-Rqst | Receive LP-10 | RX-ULPS | Line transition to LP-00 |
| RX-ULPS | Receive LP-00 | RX-ULPS-Exit | Line transition to LP-10 |
| RX-ULPS-Exit | Receive LP-10 | RX-Stop | Line transition to LP-11 |
Note: 注意：
During High-Speed data transmission, Stop states (TX-Stop, RX-Stop) have multiple valid exit states. 在高速數據傳輸期間，停止狀態（TX-Stop，RX-Stop）具有多個有效的退出狀態。
6.9 Global Operation Timing Parameters 6.9 全球操作時間參數
Table 14 lists the ranges for all timing parameters used in this section. The values in the table assume a UI variation in the range defined by DeltaUI\Delta \mathrm{UI} (see Table 30 ). 表 14 列出了本節中使用的所有定時參數的範圍。表中的值假設 UI 變化在 DeltaUI\Delta \mathrm{UI} 定義的範圍內（見表 30）。
Transmitters shall support all transmitter-specific timing parameters defined in Table 14. 發射器應支持表 14 中定義的所有發射器特定時間參數。
Receivers shall support all Receiver-specific timing parameters in defined in Table 14. 接收器應支持表 14 中定義的所有接收器特定的時間參數。
Also note that while corresponding receiver tolerances are not defined for every transmitter-specific parameter, receivers shall also support reception of all allowed conformant values for all transmitterspecific timing parameters in Table 14 for all HS UI values up to, and including, the maximum supported HS clock rate specified in the receiver’s datasheet. 另請注意，雖然並非為每個發射器特定參數定義對應的接收器容差，但接收器也應支持接收表 14 中所有發射器特定時序參數的所有允許符合值，對於所有 HS UI 值，直到並包括接收器數據表中指定的最大支持 HS 時鐘速率。
Table 14 Global Operation Timing Parameters 表 14 全球操作時間參數
Parameter 參數
Description 描述
Min
Typ
Max
Unit 單位
Notes 筆記
Tclk-miss
Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. 接收器檢測到時鐘轉換缺失並禁用時鐘通道 HS-RX 的超時。
60
ns
1,6,8
Tclk-Post
Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of T_("HS-trall ")T_{\text {HS-trall }} to the beginning of Tclk-trall. 發射器在最後一個相關數據通道轉換到低功耗模式後繼續發送 HS 時鐘的時間。間隔定義為從 T_("HS-trall ")T_{\text {HS-trall }} 結束到 Tclk-trall 開始的時間段。
60 ns + 52*UI
ns
5
Tclu-pre
Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 在任何相關數據通道開始從 LP 模式過渡到 HS 模式之前，HS 時鐘應由發射器驅動的時間。
8
UI
5
Tclk-prepare
Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 發射器驅動時鐘通道 LP-00 線狀態在開始 HS 傳輸之前的 HS-0 線狀態。
38
95
ns
5
Tclk-settle
Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. 在 Tclk-prepare 開始時，HS 接收器應忽略任何時鐘通道 HS 轉換的時間間隔。
95
300
ns
6, 7
Tclk-term-en
Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. 時鐘通道接收器啟用 HS 線終端的時間，從 Dn 跨越 VIL,max 的時間點開始。
Time for Dn to reach
Vterm-en
Time for Dn to reach
Vterm-en| Time for Dn to reach |
| :--- |
| Vterm-en |
38
ns
6
Tclk-trall
Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 在高速度傳輸突發的最後有效載荷時鐘位元之後，發射器驅動 HS-0 狀態的時間。
60
ns
5
Tclk-Prepare + Tclk-Zero
Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. Tclk-PREPARE + 發射器在啟動時鐘之前驅動 HS-0 狀態的時間。
300
ns
5
Td-TERM-EN
Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses V_(IL,MAX)V_{I L, M A X}. 數據通道接收器啟用 HS 線終端的時間，從 Dn 越過 V_(IL,MAX)V_{I L, M A X} 的時刻開始。
Time for Dn to reach V_("term-en ")V_{\text {term-en }} Dn 到達 V_("term-en ")V_{\text {term-en }} 的時間
35 ns +4 * U
6
Teot
Transmitted time interval from the start of T_("HS-TRAIL ")\mathrm{T}_{\text {HS-TRAIL }} or T_("CLK-TRALL ")\mathrm{T}_{\text {CLK-TRALL }}, to the start of the LP-11 state following a HS burst. 從 T_("HS-TRAIL ")\mathrm{T}_{\text {HS-TRAIL }} 或 T_("CLK-TRALL ")\mathrm{T}_{\text {CLK-TRALL }} 開始到 HS 突發後 LP-11 狀態開始的傳輸時間間隔。
105 ns + n12UI
3,5
THS-EXIT
Time that the transmitter drives LP-11 following a HS burst. 發射器在高頻脈衝後驅動 LP-11 的時間。
100
ns
5
Parameter Description Min Typ Max Unit Notes
Tclk-miss Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. 60 ns 1,6,8
Tclk-Post Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of T_("HS-trall ") to the beginning of Tclk-trall. 60 ns + 52*UI ns 5
Tclu-pre Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 8 UI 5
Tclk-prepare Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 38 95 ns 5
Tclk-settle Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. 95 300 ns 6, 7
Tclk-term-en Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. "Time for Dn to reach
Vterm-en" 38 ns 6
Tclk-trall Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 60 ns 5
Tclk-Prepare + Tclk-Zero Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. 300 ns 5
Td-TERM-EN Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses V_(IL,MAX). Time for Dn to reach V_("term-en ") 35 ns +4 * U 6
Teot Transmitted time interval from the start of T_("HS-TRAIL ") or T_("CLK-TRALL "), to the start of the LP-11 state following a HS burst. 105 ns + n12UI 3,5
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Tclk-miss | Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. | | | 60 | ns | 1,6,8 |
| Tclk-Post | Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of $T_{\text {HS-trall }}$ to the beginning of Tclk-trall. | 60 ns + 52*UI | | | ns | 5 |
| Tclu-pre | Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. | 8 | | | UI | 5 |
| Tclk-prepare | Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. | 38 | | 95 | ns | 5 |
| Tclk-settle | Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. | 95 | | 300 | ns | 6, 7 |
| Tclk-term-en | Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. | Time for Dn to reach <br> Vterm-en | | 38 | ns | 6 |
| Tclk-trall | Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. | 60 | | | ns | 5 |
| Tclk-Prepare + Tclk-Zero | Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. | 300 | | | ns | 5 |
| Td-TERM-EN | Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses $V_{I L, M A X}$. | Time for Dn to reach $V_{\text {term-en }}$ | | 35 ns +4 * U | | 6 |
| Teot | Transmitted time interval from the start of $\mathrm{T}_{\text {HS-TRAIL }}$ or $\mathrm{T}_{\text {CLK-TRALL }}$, to the start of the LP-11 state following a HS burst. | | | 105 ns + n*12*UI | | 3,5 |
| THS-EXIT | Time that the transmitter drives LP-11 following a HS burst. | 100 | | | ns | 5 |
Parameter 參數
Description 描述
Min
Typ
Max
Unit 單位
Notes 筆記
Ths-Prepare
Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission 發射器驅動數據通道 LP-00 的時間狀態，立即在 HS 傳輸開始前的 HS-0 線狀態
40ns+440 \mathrm{~ns}+4 * Ul
85 ns + 6* UI
ns
5
Ths-PRepare + Ths-zero
ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. ThS-PREPARE + 發射器在傳輸同步序列之前驅動 HS-0 狀態的時間。
Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value.
Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value.| Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. |
| :--- |
| The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. |
85ns+685 \mathrm{~ns}+6 * Ul
145 ns + 10*UI
ns
6
THS-SKIP
Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 在 HS 突發之後，HS-RX 應忽略數據通道上的任何過渡的時間間隔。該間隔的終點定義為 HS 突發後 LP-11 狀態的開始。
40
55 ns +4 * Ul
ns
6
Ths-trall
Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst 在高速度傳輸突發的最後有效載荷數據位之後，發射器驅動翻轉差分狀態的時間
Transmitted length of any Low-Power state period 任何低功耗狀態期間的傳輸長度
50
ns
4,5
Ratio TLPX
Ratio of LPX(MASTER) ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ")^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }} LPX(MASTER) 比例 ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ")^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}
2/3
3/2
Tta-get
Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. 在鏈路轉換期間，新的發射器在接受控制後驅動橋接狀態（LP-00）的時間。
5*TLPX
ns
5
Tta-go
Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. 發射器在鏈路回轉期間驅動橋接狀態（LP-00）後釋放控制的時間。
4*TLPX
ns
5
Tta-sure
Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. 在連接轉換期間，新發射器在 LP-10 狀態後等待的時間，然後再發送橋接狀態（LP-00）。
TLPX
2*TLPX
ns
5
Twakeup
Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. 發射器在進入停止狀態之前驅動 Mark-1 狀態的時間，以便啟動從 ULPS 的退出。
1
ms
5
Parameter Description Min Typ Max Unit Notes
Ths-Prepare Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission 40ns+4 * Ul 85 ns + 6* UI ns 5
Ths-PRepare + Ths-zero ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns 5
Ths-settle "Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value." 85ns+6 * Ul 145 ns + 10*UI ns 6
THS-SKIP Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 40 55 ns +4 * Ul ns 6
Ths-trall Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst "max(n**8^(**)UI,:}
{: 60(ns)+n^(**)4**UI)" ns 2,3,5
Tinit See Section 6.11. 100 us 5
TLPX Transmitted length of any Low-Power state period 50 ns 4,5
Ratio TLPX Ratio of LPX(MASTER) ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ") 2/3 3/2
Tta-get Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. 5*TLPX ns 5
Tta-go Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. 4*TLPX ns 5
Tta-sure Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. TLPX 2*TLPX ns 5
Twakeup Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. 1 ms 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Ths-Prepare | Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission | $40 \mathrm{~ns}+4$ * Ul | | 85 ns + 6* UI | ns | 5 |
| Ths-PRepare + Ths-zero | ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. | 145 ns + 10*UI | | | ns | 5 |
| Ths-settle | Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. <br> The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. | $85 \mathrm{~ns}+6$ * Ul | | 145 ns + 10*UI | ns | 6 |
| THS-SKIP | Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. | 40 | | 55 ns +4 * Ul | ns | 6 |
| Ths-trall | Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst | $\begin{gathered} \max \left(\mathrm{n*} 8^{*} \mathrm{UI},\right. \\ \left.60 \mathrm{~ns}+\mathrm{n}^{*} 4 * \mathrm{UI}\right) \end{gathered}$ | | | ns | 2,3,5 |
| Tinit | See Section 6.11. | 100 | | | us | 5 |
| TLPX | Transmitted length of any Low-Power state period | 50 | | | ns | 4,5 |
| Ratio TLPX | Ratio of LPX(MASTER) $^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}$ | 2/3 | | 3/2 | | |
| Tta-get | Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. | 5*TLPX | | | ns | 5 |
| Tta-go | Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. | 4*TLPX | | | ns | 5 |
| Tta-sure | Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. | TLPX | | 2*TLPX | ns | 5 |
| Twakeup | Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. | 1 | | | ms | 5 |
Note: 注意：
The minimum value depends on the bit rate. Implementations should ensure proper operation for all the supported bit rates. 最小值取決於比特率。實現應確保在所有支持的比特率下正常運行。
If a > ba>b then max(a,b)=a\max (a, b)=a otherwise max(a,b)=b\max (a, b)=b. 如果 a > ba>b 則 max(a,b)=a\max (a, b)=a 否則 max(a,b)=b\max (a, b)=b 。
Where n=1n=1 for Forward-direction HS mode and n=4n=4 for Reverse-direction HS mode.
T_(LPX)T_{L P X} is an internal state machine timing reference. Externally measured values may differ slightly from the specified values due to asymmetrical rise and fall times. T_(LPX)T_{L P X} 是一個內部狀態機定時參考。由於上升和下降時間不對稱，外部測量的值可能與規定值略有不同。
Transmitter-specific parameter. 發射器特定參數。
Receiver-specific parameter. 接收器特定參數。
The stated values are considered informative guidelines rather than normative requirements since this parameter is untestable in typical applications. 所述的數值被視為資訊性指導方針，而非規範性要求，因為在典型應用中此參數是無法測試的。
During HS Test Mode the TCIk-Miss parameter should be used for re-initialization of pattern checkers. The device should only exit the HS Test mode in the cases described in chapter 12. 在 HS 測試模式下，應使用 TCIk-Miss 參數重新初始化模式檢查器。該設備僅應在第 12 章中描述的情況下退出 HS 測試模式。
6.10 System Power States 6.10 系統電源狀態
State 州
Entry Conditions 進入條件
Exit State 退出狀態
Exit Conditions 退出條件
Line Levels 行級別
Master Off 主控關閉
Power-down 關機
Master Initialization 主控初始化
Power-up 升級
任何 LP 級別，除了停止狀態，持續時間超過 100 微秒
Any LP level
except Stop States
for periods >100us
Any LP level
except Stop States
for periods >100us| Any LP level |
| :--- |
| except Stop States |
| for periods >100us |
Master Init 主控初始化
啟動或協議請求
Power-up or
Protocol request
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
TX-Stop
根據協議，第一停止狀態的持續時間長於 TinIT，MASTER
A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol
A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol| A First Stop state |
| :--- |
| for a period longer |
| than TinIT,MASTER as |
| specified by the |
| Protocol |
任何以長初始化停止狀態結束的 LP 信號序列
Any LP signaling
sequence that
ends with a long
Initialization Stop
state
Any LP signaling
sequence that
ends with a long
Initialization Stop
state| Any LP signaling |
| :--- |
| sequence that |
| ends with a long |
| Initialization Stop |
| state |
Slave Off 關閉從屬
Power-down 關機
Any LP state 任何 LP 狀態
Power-up 升級
Any 任何
Slave Init
啟動或協議請求
Power-up or
Protocol request
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
RX-Stop
根據協議，在輸入端觀察停止狀態的時間為 TinIT,SLAVE
Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol
Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol| Observe Stop state |
| :--- |
| at the inputs for a |
| period TinIT,SLAVE as |
| specified by the |
| Protocol |
任何以第一個長初始化停止期間結束的 LP 信號序列
Any LP signaling
sequence which
ends with the first
long Initialization
Stop period
Any LP signaling
sequence which
ends with the first
long Initialization
Stop period| Any LP signaling |
| :--- |
| sequence which |
| ends with the first |
| long Initialization |
| Stop period |
State Entry Conditions Exit State Exit Conditions Line Levels
Master Off Power-down Master Initialization Power-up "Any LP level
except Stop States
for periods >100us"
Master Init "Power-up or
Protocol request" TX-Stop "A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol" "Any LP signaling
sequence that
ends with a long
Initialization Stop
state"
Slave Off Power-down Any LP state Power-up Any
Slave Init "Power-up or
Protocol request" RX-Stop "Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol" "Any LP signaling
sequence which
ends with the first
long Initialization
Stop period"| State | Entry Conditions | Exit State | Exit Conditions | Line Levels |
| :--- | :--- | :--- | :--- | :--- |
| Master Off | Power-down | Master Initialization | Power-up | Any LP level <br> except Stop States <br> for periods >100us |
| Master Init | Power-up or <br> Protocol request | TX-Stop | A First Stop state <br> for a period longer <br> than TinIT,MASTER as <br> specified by the <br> Protocol | Any LP signaling <br> sequence that <br> ends with a long <br> Initialization Stop <br> state |
| Slave Off | Power-down | Any LP state | Power-up | Any |
| Slave Init | Power-up or <br> Protocol request | RX-Stop | Observe Stop state <br> at the inputs for a <br> period TinIT,SLAVE as <br> specified by the <br> Protocol | Any LP signaling <br> sequence which <br> ends with the first <br> long Initialization <br> Stop period |
6.12 Calibration 6.12 校準
Each Lane within a PHY configuration, that is powered and enabled, has potentially three different power consumption levels: High-Speed Transmission mode, Low-Power mode and Ultra-Low Power State. For details on Ultra-Low Power State see Section 6.6.3 and Section 6.8. The transition between these modes shall be handled by the PHY. 每個啟用並供電的 PHY 配置中的通道，可能有三種不同的功耗水平：高速傳輸模式、低功耗模式和超低功耗狀態。關於超低功耗狀態的詳細信息，請參見第 6.6.3 節和第 6.8 節。這些模式之間的轉換應由 PHY 處理。
6.11 Initialization 6.11 初始化
After power-up, the Slave side PHY shall be initialized when the Master PHY drives a Stop State (LP-11) for a period longer than T_("INIT ")\mathrm{T}_{\text {INIT }}. The first Stop state longer than the specified T_("INIT ")\mathrm{T}_{\text {INIT }} is called the Initialization period. The Master PHY itself shall be initialized by a system or Protocol input signal (PPI). The Master side shall ensure that a Stop State longer than T_("INIT ")\mathrm{T}_{\text {INIT }} does not occur on the Lines before the Master is initialized. The Slave side shall ignore all Line states during an interval of unspecified length prior to the Initialization period. In multi-Lane configurations, all Lanes shall be initialized simultaneously. 在上電後，從屬端的 PHY 應在主控 PHY 驅動停止狀態（LP-11）持續時間超過 T_("INIT ")\mathrm{T}_{\text {INIT }} 時進行初始化。第一次超過指定 T_("INIT ")\mathrm{T}_{\text {INIT }} 的停止狀態稱為初始化期間。主控 PHY 本身應由系統或協議輸入信號（PPI）進行初始化。主控端應確保在主控端初始化之前，線路上不會出現持續時間超過 T_("INIT ")\mathrm{T}_{\text {INIT }} 的停止狀態。在初始化期間之前，從屬端應忽略所有線路狀態，該間隔的長度未指定。在多通道配置中，所有通道應同時初始化。
Note that T_("INIT ")\mathrm{T}_{\text {INIT }} is considered a protocol-dependent parameter, and thus the exact requirements for T_("INIT,MASTER ")\mathrm{T}_{\text {INIT,MASTER }} and T_("INIT,SlaVe ")\mathrm{T}_{\text {INIT,SlaVe }} (transmitter and receiver initialization Stop state lengths, respectively,) are defined by the protocol layer specification and are outside the scope of this document. However, the DPHY specification does place a minimum bound on the lengths of T_("INIT,MASTER ")T_{\text {INIT,MASTER }} and T_("INIT,SLAVE ")\mathrm{T}_{\text {INIT,SLAVE }}, which each shall be no less than 100 mus100 \mu \mathrm{~s}. A protocol layer specification using the D -PHY specification may specify any values greater than this limit, for example, T_("INIT,MASTER ") >= 1ms\mathrm{T}_{\text {INIT,MASTER }} \geq 1 \mathrm{~ms} and T_("INIT,SLAVE ")=500\mathrm{T}_{\text {INIT,SLAVE }}=500 to 800 mus800 \mu \mathrm{~s}. 請注意， T_("INIT ")\mathrm{T}_{\text {INIT }} 被視為協議依賴的參數，因此 T_("INIT,MASTER ")\mathrm{T}_{\text {INIT,MASTER }} 和 T_("INIT,SlaVe ")\mathrm{T}_{\text {INIT,SlaVe }} （發射器和接收器初始化停止狀態長度）的具體要求由協議層規範定義，並不在本文件的範疇內。然而，DPHY 規範確實對 T_("INIT,MASTER ")T_{\text {INIT,MASTER }} 和 T_("INIT,SLAVE ")\mathrm{T}_{\text {INIT,SLAVE }} 的長度設置了最小限制，這兩者的長度不得少於 100 mus100 \mu \mathrm{~s} 。使用 D-PHY 規範的協議層規範可以指定任何大於此限制的值，例如 T_("INIT,MASTER ") >= 1ms\mathrm{T}_{\text {INIT,MASTER }} \geq 1 \mathrm{~ms} 和 T_("INIT,SLAVE ")=500\mathrm{T}_{\text {INIT,SLAVE }}=500 到 800 mus800 \mu \mathrm{~s} 。
Table 15 Initialization States 表 15 初始化狀態
Receiver deskew shall be initiated by the transmitter for the DUT’s supporting > 1.5 Gbps. The transmitter shall send a special deskew burst, as shown in Figure 24. When operating above 1.5 Gbps or changing to any rate above 1.5 Gbps , an initial deskew sequence shall be transmitted before High-Speed Data Transmission in normal operation. When operating at or below 1.5 Gbps, the transmission of initial deskew sequence is optional. Periodic deskew is optional irrespective of data rate. 接收器去偏移應由發射器啟動，以支持超過 1.5 Gbps 的被測設備。發射器應發送特殊的去偏移突發，如圖 24 所示。在超過 1.5 Gbps 或更改為任何超過 1.5 Gbps 的速率時，應在正常操作中的高速數據傳輸之前傳輸初始去偏移序列。在 1.5 Gbps 或以下的操作中，初始去偏移序列的傳輸是可選的。無論數據速率如何，定期去偏移都是可選的。
When changing states, for example from ULPS to HS, transmission of any deskew sequence is optional, provided HS operation resumes at a rate for which an initial deskew sequence has previously been transmitted. 在更改狀態時，例如從 ULPS 到 HS，任何去偏移序列的傳輸都是可選的，前提是 HS 操作以先前已傳輸初始去偏移序列的速率恢復。
A. HS Sync-Sequence for HS Skew-Calibration (‘11111111_11111111’) A. HS 同步序列用於 HS 偏差校準 (‘11111111_11111111’)
B. Same as clock lane (‘01010101’) B. 與時鐘通道相同（‘01010101’） rarr\rightarrow Performs HS Skew-Calibration in RX side rarr\rightarrow 在接收端執行 HS 偏斜校準
C. HS Sync-Sequence for normal HS mode (‘00011101’) C. HS 同步序列正常 HS 模式（‘00011101’）
D. HS payload data D. HS 貨載數據
Figure 24 High-Speed Data Transmission in Skew-Calibration 圖 24 高速數據傳輸中的偏斜校準
Figure 24 High-Speed Data Transmission in Skew-Calibration 圖 24 高速數據傳輸中的偏斜校準
The transmitter deskew burst shall use a sync pattern consisting of all one’s, lasting a duration of 16 UI. After the sync pattern is sent, the payload shall be a clock pattern ( 01010101 dots01010101 \ldots ) of minimum duration 2^(15)2^{15} UI for initial deskew calibration, and of minimum duration 2^(10)2^{10} UI for periodic calibration. See Figure 25 and Figure 26. 發射器去偏移突發應使用由全為 1 的同步模式組成，持續時間為 16 UI。在發送同步模式後，載荷應為時鐘模式 ( 01010101 dots01010101 \ldots )，初始去偏移校準的最小持續時間為 2^(15)2^{15} UI，定期校準的最小持續時間為 2^(10)2^{10} UI。請參見圖 25 和圖 26。
High-Speed Data Transmission in Normal Mode 正常模式下的高速數據傳輸
High-Speed Skew Calibration 高速斜率校準
Figure 25 Normal Mode vs Skew Calibration 圖 25 正常模式與偏斜校準
High-Speed Data Transmission in Normal Mode 正常模式下的高速數據傳輸
High-Speed Skew Calibration 高速斜率校準
Figure 26 Normal Mode vs Skew Calibration (Zoom-In) 圖 26 正常模式與偏斜校準（放大）
The receiver shall detect the deskew sync pattern and initiate deskew calibration upon detection. The transmitter deskew sequence transmission shall be initiated under the transmitter configuration control on all active lanes simultaneously. The start-of-transmission sequence is described in Table 16, and the end-oftransmission sequence is described in Table 17. 接收器應檢測去斜同步模式並在檢測到後啟動去斜校準。發射器去斜序列傳輸應在所有活動通道上同時在發射器配置控制下啟動。傳輸開始序列在表 16 中描述，傳輸結束序列在表 17 中描述。
Drives HS-Rqst state (LP-01) for time TLPX 驅動 HS-Rqst 狀態 (LP-01) 於時間 TLPX
Observes transition from LP-11 to LP-01 on the lines 觀察從 LP-11 到 LP-01 的過渡情況
TX Side RX Side
Drives stop state (LP-11) Observes stop state
Drives HS-Rqst state (LP-01) for time TLPX Observes transition from LP-11 to LP-01 on the lines| TX Side | RX Side |
| :--- | :--- |
| Drives stop state (LP-11) | Observes stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the lines |
TX Side TX 端
RX Side RX 端
Drives bridge state (LP-00) for time THS-PREPARE 驅動橋接狀態 (LP-00) 以時間 THS-PREPARE
Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)| Observes transition from LP-01 to LP-00 on the |
| :--- |
| lines, and enables line termination after time |
| TD-TERMEN $^{\mid}$ |
Drives HS-0 for a time THS-ZERO 驅動器 HS-0 持續時間 THS-ZERO
啟用 HS-RX 並等待計時器 THs-SETTLE 到期，以忽略過渡效應
Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects
Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THs-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
Starts looking for leader sequence 開始尋找領導序列
插入高速度同步序列以進行高速偏移校準：'11111111_11111111'，從上升時鐘邊緣開始
Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge
Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge| Inserts the high-speed sync sequence for high- |
| :--- |
| speed skew-calibration: '11111111_11111111' |
| beginning on a rising clock edge |
在識別到領導序列時進行同步：'1111_1111'
Synchronizes upon recognition of leader sequence:
'1111_1111'
Synchronizes upon recognition of leader sequence:
'1111_1111'| Synchronizes upon recognition of leader sequence: |
| :--- |
| '1111_1111' |
Receives '01010101' data 接收 '01010101' 數據
Receives '01010101' data| Receives '01010101' data |
| :--- |
繼續傳輸與時鐘通道相同的高速數據：'01010101'
Continues to transmit high speed data that is the
same as the clock lane: '01010101'
Continues to transmit high speed data that is the
same as the clock lane: '01010101'| Continues to transmit high speed data that is the |
| :--- |
| same as the clock lane: '01010101' |
在時鐘和數據通道之間進行高速傾斜校準
Performs high-speed skew-calibration between clock
and data lanes
Performs high-speed skew-calibration between clock
and data lanes| Performs high-speed skew-calibration between clock |
| :--- |
| and data lanes |
完成時鐘和數據通道之間的高速斜率校準
Finishes high-speed skew-calibration between clock
and data lanes
Finishes high-speed skew-calibration between clock
and data lanes| Finishes high-speed skew-calibration between clock |
| :--- |
| and data lanes |
TX Side RX Side
Drives bridge state (LP-00) for time THS-PREPARE "Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)"
"Simultaneously enables high-speed driver and
disables low-power drivers"
Drives HS-0 for a time THS-ZERO "Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects"
Starts looking for leader sequence
"Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge" "Synchronizes upon recognition of leader sequence:
'1111_1111'"
"Receives '01010101' data"
"Continues to transmit high speed data that is the
same as the clock lane: '01010101'" "Performs high-speed skew-calibration between clock
and data lanes"
"Finishes high-speed skew-calibration between clock
and data lanes"
| TX Side | RX Side |
| :--- | :--- |
| Drives bridge state (LP-00) for time THS-PREPARE | Observes transition from LP-01 to LP-00 on the <br> lines, and enables line termination after time <br> TD-TERMEN $^{\mid}$ |
| Simultaneously enables high-speed driver and <br> disables low-power drivers | |
| Drives HS-0 for a time THS-ZERO | Enables HS-RX and waits for timer THs-SETTLE to <br> expire in order to neglect transition effects |
| | Starts looking for leader sequence |
| Inserts the high-speed sync sequence for high- <br> speed skew-calibration: '11111111_11111111' <br> beginning on a rising clock edge | Synchronizes upon recognition of leader sequence: <br> '1111_1111' |
| | Receives '01010101' data |
| Continues to transmit high speed data that is the <br> same as the clock lane: '01010101' | Performs high-speed skew-calibration between clock <br> and data lanes |
| | Finishes high-speed skew-calibration between clock <br> and data lanes |
| | |
Completes transmission of '01010101' data 完成傳輸 '01010101' 數據
Receives '01010101' data 接收 '01010101' 數據
Toggles differential state immediately after last
payload data bit and holds that state for a time
THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}
the stop state (LP-11) for a time THS-EXIT
the stop state (LP-11) for a time THS-EXIT| the stop state (LP-11) for a time THS-EXIT |
| :--- |
Toggles differential state immediately after last
payload data bit and holds that state for a time
THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXIT| Toggles differential state immediately after last |
| :--- |
| payload data bit and holds that state for a time |
| THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXIT |
Detects the lines leaving LP-00 state and entering
the stop state (LP-11), and disables termination
Detects the lines leaving LP-00 state and entering
the stop state (LP-11), and disables termination| Detects the lines leaving LP-00 state and entering |
| :--- |
| the stop state (LP-11), and disables termination |
Neglects bits of last period THS-SKIP to hide transition
effects
Neglects bits of last period THS-SKIP to hide transition
effects| Neglects bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
檢測有效數據的最後過渡，確定最後有效數據字節並跳過尾部序列
Detects last transition of valid data, determines last
valid data byte and skip trailer sequence
Detects last transition of valid data, determines last
valid data byte and skip trailer sequence| Detects last transition of valid data, determines last |
| :--- |
| valid data byte and skip trailer sequence |
Starts looking for leader sequence 開始尋找領導序列
TX Side RX Side
Completes transmission of '01010101' data Receives '01010101' data
"Toggles differential state immediately after last
payload data bit and holds that state for a time
THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXIT""Detects the lines leaving LP-00 state and entering
the stop state (LP-11), and disables termination"
"Neglects bits of last period THS-SKIP to hide transition
effects"
"Detects last transition of valid data, determines last
valid data byte and skip trailer sequence"
Starts looking for leader sequence| TX Side | RX Side |
| :--- | :--- |
| Completes transmission of '01010101' data | Receives '01010101' data |
| Toggles differential state immediately after last <br> payload data bit and holds that state for a time <br> THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXITDetects the lines leaving LP-00 state and entering <br> the stop state (LP-11), and disables termination | |
| | Neglects bits of last period THS-SKIP to hide transition <br> effects |
| | Detects last transition of valid data, determines last <br> valid data byte and skip trailer sequence |
| | Starts looking for leader sequence |
Note: 注意：
During skew calibration time, high-speed skew calibration on the RX side has to finish. The TX side is not aware of the RX side completing calibration. 在偏斜校準期間，RX 端的高速偏斜校準必須完成。TX 端並不知道 RX 端已完成校準。
631 The TsKewcal maximum is 100 musec100 \mu \mathrm{sec} at initial calibration and 10 musec10 \mu \mathrm{sec} maximum for periodic calibration. 631 TsKewcal 最大值在初始校準時為 100 musec100 \mu \mathrm{sec} ，在定期校準時為 10 musec10 \mu \mathrm{sec} 。
632 The timing parameters are shown in Table 18. 632 時間參數顯示在表 18 中。
Time that the transmitter drives the skew-
calibration sync pattern, FFFFH| Time that the transmitter drives the skew- |
| :--- |
| calibration sync pattern, FFFFH |
16
UI
TSKEWCAL
發射器在初始偏斜校準模式下驅動偏斜校準模式的時間
Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode
Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the initial skew- |
| calibration mode |
100
mus\mu \mathrm{~s}
2^(15)2^{15}
UI
TSKEWCAL
TSKEWCAL| TSKEWCAL |
| :--- |
發射器在周期性偏斜校準模式下驅動偏斜校準模式的時間
Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode
Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the periodic skew- |
| calibration mode |
10
mus\mu \mathrm{~s}
UI
Parameter Description Min Typ Max Unit Notes
TSKEWCAL_SYNC "Time that the transmitter drives the skew-
calibration sync pattern, FFFFH" 16 UI
TSKEWCAL "Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode" 100 mus
2^(15) UI
"TSKEWCAL" "Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode" 10 mus
UI | Parameter | Description | Min | Typ | Max | Unit | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| TSKEWCAL_SYNC | Time that the transmitter drives the skew- <br> calibration sync pattern, FFFFH | | 16 | | UI | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the initial skew- <br> calibration mode | | | 100 | $\mu \mathrm{~s}$ | |
| | $2^{15}$ | | | UI | | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the periodic skew- <br> calibration mode | | | 10 | $\mu \mathrm{~s}$ | |
| | | | | UI | | |
For periodic deskew calibration, the transmitter shall finish the current burst before sending a deskew sequence. 對於定期的去斜校準，發射器應在發送去斜序列之前完成當前的突發。
During the Receiver deskew calibration, jittered signals are present at the input of the Receiver. The Receiver deskew block should function properly with Spread Spectrum clocking in active mode. The intent of periodic deskew is to fine tune the deskew established by the initial deskew sequence. 在接收器去斜校準期間，接收器的輸入端存在抖動信號。接收器去斜區塊應在活動模式下正常運作，並使用擴頻時鐘。定期去斜的目的是對初始去斜序列所建立的去斜進行微調。
Being a forwarded clock link, jitter spectral content shall remain in the following range: 作為一個轉發時鐘鏈路，抖動頻譜內容應保持在以下範圍內：
The minimum jitter frequency shall be calculated as (data_rate[b/s])/20. 最小抖動頻率應計算為 (data_rate[b/s])/20。
Example values: 範例值：
225 MHz at 4.5Gb//s4.5 \mathrm{~Gb} / \mathrm{s},
125 MHz at 2.5Gb//s2.5 \mathrm{~Gb} / \mathrm{s}
75 MHz at 1.5Gb//s1.5 \mathrm{~Gb} / \mathrm{s}
The maximum jitter frequency shall be calculated as (data_rate[b/s])/2. 最大抖動頻率應計算為 (data_rate[b/s])/2。
6.13 Global Operation Flow Diagram 6.13 全球操作流程圖
All previously described aspects of operation, either including or excluding optional parts, are contained in Lane Modules. Figure 27 shows the operational flow diagram for a Data Lane Module. Within both TX and RX four main processes can be distinguished: High-Speed Transmission, Escape mode, Turnaround, and Initialization. 所有先前描述的操作方面，無論是包括還是排除可選部件，都包含在通道模塊中。圖 27 顯示了數據通道模塊的操作流程圖。在 TX 和 RX 中可以區分出四個主要過程：高速傳輸、逃逸模式、回轉和初始化。
Figure 27 Data Lane Module State Diagram 圖 27 數據通道模塊狀態圖
Figure 28 shows the state diagram for a Clock Lane Module. The Clock Lane Module has four major operational states: Init (of unspecified duration), Low-Power Stop state, Ultra-Low Power state, and HighSpeed clock transmission. The figure also shows the transition states as described previously. 圖 28 顯示了時鐘通道模組的狀態圖。時鐘通道模組有四個主要操作狀態：初始化（持續時間未指定）、低功耗停止狀態、超低功耗狀態和高速時鐘傳輸。該圖還顯示了之前描述的過渡狀態。
Figure 28 Clock Lane Module State Diagram 圖 28 時鐘通道模組狀態圖
6.14 Data Rate Dependent Parameters (informative) 6.14 數據速率依賴參數（資訊性）
The high speed data transfer rate of the D-PHY may be programmable to values determined by a particular implementation. Any individual data transfer between SoT and EoT sequences must take place at a given, fixed rate. However, reprogramming the data rate of the D-PHY high speed transfer is allowed at initialization, before starting the exit from ULP state or in Stop state whenever the HS clock is not running. The method of data rate reprogramming is out of the scope of this document. D-PHY 的高速數據傳輸速率可以根據特定實現的要求進行編程。SoT 和 EoT 序列之間的任何單獨數據傳輸必須以給定的固定速率進行。然而，在初始化時允許重新編程 D-PHY 高速傳輸的數據速率，或者在 HS 時鐘未運行的情況下，在退出 ULP 狀態之前或在停止狀態下進行。數據速率重新編程的方法不在本文件的範疇內。
Many time parameter values in this document are specified as the sum of a fixed time and a particular number of High-Speed UIs. The parameters may need to be recomputed if the data rate, and therefore the UI value, is changed. These parameters, with their allowed values, are listed in Table 14. For clarity, the parameter names and purposes are repeated here. 本文件中的許多時間參數值被指定為固定時間和特定數量的高速 UI 之和。如果數據速率，因此 UI 值發生變化，則可能需要重新計算這些參數。這些參數及其允許的值列在表 14 中。為了清晰起見，這裡重複了參數名稱和用途。
6.14.1 Parameters Containing Only UI Values 6.14.1 僅包含 UI 值的參數
T _("ClK-PRe ")_{\text {ClK-PRe }} is the minimum number of High-Speed clock cycles the Master must send over the Clock Lane after it is restarted in HS mode and before any data transmission may begin. If a particular protocol at the Slave side requires more clock cycles then T_("CLK-PRE ")\mathrm{T}_{\text {CLK-PRE }}, the Master side protocol should ensure that these are transmitted. T _("ClK-PRe ")_{\text {ClK-PRe }} 是主設備在高速度模式下重新啟動後必須在時鐘通道上發送的最小高速度時鐘週期數，並且在任何數據傳輸開始之前。如果從設備端的特定協議需要的時鐘週期數超過 T_("CLK-PRE ")\mathrm{T}_{\text {CLK-PRE }} ，則主設備端的協議應確保這些時鐘週期被傳輸。
6.14.2 Parameters Containing Time and UI values 6.14.2 包含時間和 UI 值的參數
Several parameters are specified as the sum of an explicit time and a number of UI. The explicit time values, in general, are derived from the time needed to charge and discharge the interconnect to its specified values given the specified drive voltages and line termination values. As such, the explicit time values are not data rate dependent. It is conceivable to use the sum of an analog timer and a HS clock counter to ensure the implementation satisfies these parameters. If these explicit time values are implemented by counting HS clock cycles only, the count value is a function of the data rate and, therefore, must be changed when the data rate is changed. 幾個參數被指定為明確時間和多個 UI 的總和。一般來說，明確時間值是根據在指定驅動電壓和線終止值下，充電和放電互連到其指定值所需的時間得出的。因此，明確時間值不依賴於數據速率。可以想像使用模擬計時器和 HS 時鐘計數器的總和來確保實現滿足這些參數。如果這些明確時間值僅通過計數 HS 時鐘週期來實現，則計數值是數據速率的函數，因此在數據速率變更時必須進行更改。 T_(D"-term-en ")\mathrm{T}_{\mathrm{D} \text {-term-en }} is the time to enable Data Lane receiver line termination measured from when Dn crosses V_("IL,MAX. ")V_{\text {IL,MAX. }} T_(D"-term-en ")\mathrm{T}_{\mathrm{D} \text {-term-en }} 是從 Dn 穿越 V_("IL,MAX. ")V_{\text {IL,MAX. }} 時開始啟用數據通道接收器線終止的時間 T_(HS"-PREPARE ")\mathrm{T}_{\mathrm{HS} \text {-PREPARE }}, is the time to drive LP-00 before starting the HS transmission on a Data Lane. T_(HS"-PREPARE ")\mathrm{T}_{\mathrm{HS} \text {-PREPARE }} ，是在數據通道上開始 HS 傳輸之前驅動 LP-00 的時間。 T_("HS-PRepare ")+T_("HS-zero,Min ")\mathrm{T}_{\text {HS-PRepare }}+\mathrm{T}_{\text {HS-zero,Min }} is the sum of the time to drive LP-00 in preparation for the start of HS transmission plus the time to send HS-0, i.e. turn on the line termination and drive the interconnect with the HS driver, prior to sending the SoT Sync sequence. T_("HS-PRepare ")+T_("HS-zero,Min ")\mathrm{T}_{\text {HS-PRepare }}+\mathrm{T}_{\text {HS-zero,Min }} 是為了開始 HS 傳輸而駕駛 LP-00 的時間總和，加上發送 HS-0 的時間，即在發送 SoT 同步序列之前，打開線路終端並用 HS 驅動器驅動互連的時間。 T_(HS"-TRAIL ")\mathrm{T}_{\mathrm{HS} \text {-TRAIL }} is the time the transmitter must drive the flipped last data bit after sending the last payload data bit of a HS transmission burst. This time is required by the receiver to determine EoT. T_(HS"-TRAIL ")\mathrm{T}_{\mathrm{HS} \text {-TRAIL }} 是發射器在發送 HS 傳輸突發的最後有效載荷數據位後，必須驅動翻轉的最後數據位的時間。接收器需要這段時間來確定 EoT。 T_(HS"-SKIP ")\mathrm{T}_{\mathrm{HS} \text {-SKIP }} is the time the receiver must “back up” and skip data to ignore the transition period of the EoT sequence. T_(HS"-SKIP ")\mathrm{T}_{\mathrm{HS} \text {-SKIP }} 是接收器必須“回退”並跳過數據以忽略 EoT 序列的過渡期的時間。 T_("CLK-Post,Min ")\mathrm{T}_{\text {CLK-Post,Min }} is the minimum time that the transmitter continues sending HS clocks after the last Data Lane has transitioned to LP mode following a HS transmission burst. If a particular receiver implementation requires more clock cycles than T_("CLK-POST,MIN ")\mathrm{T}_{\text {CLK-POST,MIN }} to finish reception, the transmitter must supply sufficient clocks to accomplish the reception. T_("CLK-Post,Min ")\mathrm{T}_{\text {CLK-Post,Min }} 是發射器在最後一個數據通道轉換到 LP 模式後，繼續發送 HS 時鐘的最小時間。如果特定的接收器實現需要比 T_("CLK-POST,MIN ")\mathrm{T}_{\text {CLK-POST,MIN }} 更多的時鐘週期來完成接收，發射器必須提供足夠的時鐘來完成接收。
6.14.3 Parameters Containing Only Time Values 6.14.3 僅包含時間值的參數
Several parameters are specified only as explicit time values. As in Section 6.14.2, these explicit time values are typically derived from the time needed to charge and discharge the interconnect and are, therefore, not data rate dependent. It is conceivable to use an analog timer or a HS clock counter to ensure the implementation satisfies these parameters. However, if these time values are implemented by counting HS clock cycles only, the count value is a function of the data rate and, therefore, must be changed when the data rate is changed. 幾個參數僅以明確的時間值指定。如第 6.14.2 節所述，這些明確的時間值通常源自於充電和放電互連所需的時間，因此不依賴於數據速率。可以想像使用模擬計時器或 HS 時鐘計數器來確保實現滿足這些參數。然而，如果這些時間值僅通過計數 HS 時鐘週期來實現，則計數值是數據速率的函數，因此在數據速率變更時必須進行更改。
The following parameters are based on time values alone: 以下參數僅基於時間值：
THS-SKIP,MIN
TCLK-MISS,MAX
TClk-term-en
TClK-Prepare
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent 6.14.4 僅包含不依賴於數據速率的時間值的參數
The remaining parameters in Table 14 shall be complied with even when the High-Speed clock is off. These parameters include Low-Power and initialization state durations and LP signaling intervals. Though these parameters are not HS data rate dependent, some implementations of D-PHY may need to adjust these values when the data rate is changed. 表 14 中的其餘參數即使在高速時鐘關閉時也必須遵守。這些參數包括低功耗和初始化狀態持續時間以及 LP 信號間隔。雖然這些參數不依賴於 HS 數據速率，但某些 D-PHY 的實現可能需要在數據速率變更時調整這些值。
6.15 Interoperability 6.15 互操作性
Table 19 summarizes integration and downward compatibility for all possible combinations of the Tx’s DPHY Specification version and the Rx’s D-PHY Specification version. The table shows the maximum operating speed for each possible combination, and indicates the four combinations that require deskew initialization. For example, a D-PHY v2.0 Tx and a D-PHY v1.2 Rx are compatible for speeds up to 1.5 Gbps without deskew initialization, and at speeds up to 2.5 Gbps if deskew initialization is used. 表 19 總結了 Tx 的 DPHY 規範版本和 Rx 的 D-PHY 規範版本所有可能組合的整合性和向下相容性。該表顯示了每個可能組合的最大操作速度，並指出了需要進行去偏移初始化的四個組合。例如，D-PHY v2.0 Tx 和 D-PHY v1.2 Rx 在不進行去偏移初始化的情況下，兼容的速度可達 1.5 Gbps，並在使用去偏移初始化的情況下，兼容的速度可達 2.5 Gbps。
Table 19 D-PHY Version Integration and Downward Compatibility 表 19 D-PHY 版本整合與向下相容性
Note: 注意：
Cells containing dashes ( ^(-)-{ }^{-}-) indicate that Deskew Initialization is not required 包含破折號的單元格 ( ^(-)-{ }^{-}- ) 表示不需要進行去斜初始化
7 Fault Detection 7 故障檢測
There are three different mechanisms to detect malfunctioning of the Link. Bus contention and error detection functions are contained within the D-PHY. These functions should detect many typical faults. However, some faults cannot be detected within the D-PHY and require a protocol-level solution. Therefore, the third detection mechanism is a set of application specific watchdog timers. 有三種不同的機制來檢測連接的故障。總線競爭和錯誤檢測功能包含在 D-PHY 中。這些功能應該能檢測許多典型的故障。然而，某些故障無法在 D-PHY 內部檢測到，並需要協議層面的解決方案。因此，第三種檢測機制是一組特定於應用的看門狗計時器。
7.1 Contention Detection 7.1 競爭檢測
If a bi-directional Lane Module and a Unidirectional Module are combined in one Lane, only unidirectional functionality is available. Because in this case the additional functionality of one bi-directional PHY Module cannot be reliably controlled from the limited functionality PHY side, the bi-directional features of the bi-directional Module shall be safely disabled. Otherwise in some cases deadlock may occur which can only be resolved with a system power-down and re-initialization procedure. 如果在一條通道中結合了雙向通道模組和單向模組，則僅可使用單向功能。因為在這種情況下，無法從有限功能的物理層一側可靠地控制一個雙向物理模組的附加功能，因此雙向模組的雙向功能應安全禁用。否則在某些情況下可能會發生死鎖，這只能通過系統關機和重新初始化程序來解決。
During normal operation one and only one side of a Link shall drive a Lane at any given time except for certain transition periods. Due to errors or system malfunction a Lane may end up in an undesirable state, where the Lane is driven from two sides or not driven at all. This condition eventually results in a state conflict and is called Contention. 在正常運作期間，任何時候只有一側的連結應驅動一條通道，除非在某些過渡期間。由於錯誤或系統故障，通道可能會處於不理想的狀態，即通道同時被兩側驅動或根本不被驅動。這種情況最終會導致狀態衝突，稱為競爭。
All Lane Modules with LP bi-directionality shall include contention detection functions to detect the following contention conditions: 所有具有 LP 雙向性的通道模組應包括爭用檢測功能，以檢測以下爭用條件：
Modules on both sides of the same line drive opposite LP levels against each other. In this case, the line voltage will settle to some value between V_("OL,MIN ")\mathrm{V}_{\text {OL,MIN }} and V_(OH,MAx)\mathrm{V}_{\mathrm{OH}, \mathrm{MAx}}. Because V_(IL)\mathrm{V}_{\mathrm{IL}} is greater than V_(IHCD)\mathrm{V}_{\mathrm{IHCD}}, the settled value will always be either higher than V_(IHCD)\mathrm{V}_{\mathrm{IHCD}}, lower than V_(IL)\mathrm{V}_{\mathrm{IL}}, or both. Refer to Section 8. This ensures that at least one side of the link, possibly both, will detect the fault condition. 同一行兩側的模組相互驅動對立的 LP 水平。在這種情況下，線電壓將穩定在 V_("OL,MIN ")\mathrm{V}_{\text {OL,MIN }} 和 V_(OH,MAx)\mathrm{V}_{\mathrm{OH}, \mathrm{MAx}} 之間的某個值。因為 V_(IL)\mathrm{V}_{\mathrm{IL}} 大於 V_(IHCD)\mathrm{V}_{\mathrm{IHCD}} ，穩定值將始終高於 V_(IHCD)\mathrm{V}_{\mathrm{IHCD}} 、低於 V_(IL)\mathrm{V}_{\mathrm{IL}} ，或兩者皆是。請參閱第 8 節。這確保了鏈路的一側，可能是兩側，將檢測到故障狀態。
The Module at one side drives LP-high while the other side drives HS-low on the same Line. In this case, the line voltage will settle to a value lower than V_(IL)\mathrm{V}_{\mathrm{IL}}. The contention shall be detected at the side that is transmitting the LP-high. 模組一側驅動 LP 高，而另一側在同一條線上驅動 HS 低。在這種情況下，線電壓將穩定在低於 V_(IL)\mathrm{V}_{\mathrm{IL}} 的值。爭用將在傳輸 LP 高的一側被檢測到。
The first condition can be detected by the combination of LP-CD and LP-RX functions. The LP-RX function should be able to detect the second contention condition. Details on the LP-CD and LP-RX electrical specifications can be found in Section 9. Except when the previous state was TX-ULPS, contention shall be checked before the transition to a new state. Contention detection in ULPS is not required because the bit period is not defined and a clock might not be available. 第一個條件可以通過 LP-CD 和 LP-RX 功能的組合來檢測。LP-RX 功能應能夠檢測第二個競爭條件。關於 LP-CD 和 LP-RX 電氣規格的詳細信息可以在第 9 節中找到。除非前一狀態為 TX-ULPS，否則在過渡到新狀態之前應檢查競爭。在 ULPS 中不需要競爭檢測，因為位元週期未定義，且可能沒有時鐘可用。
After contention has been detected, the Protocol shall take proper measures to resolve the situation. 在檢測到爭議後，協議應採取適當措施來解決情況。
7.2 Sequence Error Detection 7.2 序列錯誤檢測
If for any reason the Lane signal is corrupted the receiving PHY may detect signal sequence errors. Errors detected inside the PHY may be communicated to the Protocol via the PPI. This kind of error detection is optional, but strongly recommended as it enhances reliability. The following sequence errors can be distinguished: 如果因任何原因通道信號受到損壞，接收 PHY 可能會檢測到信號序列錯誤。在 PHY 內部檢測到的錯誤可以通過 PPI 傳達給協議。這種錯誤檢測是可選的，但強烈建議使用，因為它增強了可靠性。可以區分以下序列錯誤：
SoT Error SoT 錯誤
SoT Sync Error SoT 同步錯誤
EoT Sync Error EoT 同步錯誤
Escape Entry Command Error 逃脫進入命令錯誤
LP Transmission Sync Error LP 傳輸同步錯誤
False Control Error 錯誤控制失敗
7.2.1 SoT Error 7.2.1 SoT 錯誤
The Leader sequence for Start of High-Speed Transmission is fault tolerant for any single-bit error and some multi-bit errors. Therefore, the synchronization may be usable, but confidence in the payload data is lower. If this situation occurs an SoT Error is indicated. 高速傳輸開始的領導序列對任何單位錯誤和某些多位錯誤具有容錯能力。因此，同步可能可用，但對有效載荷數據的信心較低。如果發生這種情況，則會指示 SoT 錯誤。
7.2.2 SoT Sync Error 7.2.2 SoT 同步錯誤
If the SoT Leader sequence is corrupted in a way that proper synchronization cannot be expected, a SoT Sync Error is indicated. 如果 SoT 領導者序列以無法預期正確同步的方式損壞，則會顯示 SoT 同步錯誤。
7.2.3 EoT Sync Error 7.2.3 EoT 同步錯誤
The EoT Sync Error is indicated when the last bit of a transmission does not match a byte boundary. This error can only be indicated in case of EoT processing on detection of LP-11. 當傳輸的最後一位元與位元組邊界不匹配時，會顯示 EoT 同步錯誤。此錯誤僅在檢測到 LP-11 時的 EoT 處理中顯示。
If the receiving Lane Module does not recognize the received Entry Command for Escape mode an Escape mode Entry Command Error is indicated. 如果接收的通道模組無法識別接收到的逃脫模式進入命令，則會顯示逃脫模式進入命令錯誤。
7.2.5 LP Transmission Sync Error 7.2.5 LP 傳輸同步錯誤
At the end of a Low-Power Data transmission procedure, if data is not synchronized to a Byte boundary an Escape Sync Error signal is indicated. 在低功耗數據傳輸程序結束時，如果數據未與字節邊界同步，則會顯示逃逸同步錯誤信號。
7.2.6 False Control Error 7.2.6 錯誤控制錯誤
If a LP-Rqst (LP-10) is not followed by the remainder of a valid Escape or Turnaround sequence, a False Control Error is indicated. This error is also indicated if a HS-Rqst (LP-01) is not correctly followed by a Bridge State (LP-00). 如果 LP-Rqst (LP-10) 沒有後接有效的逃逸或轉向序列的其餘部分，則表示出現虛假控制錯誤。如果 HS-Rqst (LP-01) 沒有正確後接橋接狀態 (LP-00)，也會顯示此錯誤。
It is not possible for the PHY to detect all fault cases. Therefore, additional protocol-level time-out mechanisms are necessary in order to limit the maximum duration of certain modes and states. PHY 無法檢測所有故障情況。因此，需要額外的協議層超時機制，以限制某些模式和狀態的最大持續時間。
7.3.1 HS RX Timeout 7.3.1 HS RX 超時
In HS RX mode if no EoT is received within a certain period the protocol should time-out. The timeout period can be protocol specific. 在 HS RX 模式下，如果在一定時間內未收到 EoT，則協議應該超時。超時期間可以是協議特定的。
7.3.2 HS TX Timeout 7.3.2 HS TX 超時
The maximum transmission length in HS TX is bounded. The timeout period is protocol specific. HS TX 中的最大傳輸長度是有限制的。超時期間是協議特定的。
7.3.3 Escape Mode Timeout 7.3.3 逃脫模式超時
A device may timeout during Escape mode. The timeout should be greater than the Escape mode Silence Limit of the other device. The timeout period is protocol specific. 設備在逃脫模式下可能會超時。超時應大於另一設備的逃脫模式靜音限制。超時期間是協議特定的。
7.3.4 Escape Mode Silence Timeout 7.3.4 逃脫模式靜音超時
A device may have a bounded length for LP TX-00 during Escape mode, after which the other device may timeout. The timeout period is protocol specific. For example, a display module should have an Escape mode Silence Limit, after which the host processor can timeout. 在逃逸模式下，設備可能對 LP TX-00 有一個有限的長度，之後另一個設備可能會超時。超時期間是協議特定的。例如，顯示模組應該有一個逃逸模式靜音限制，之後主處理器可以超時。
7.3.5 Turnaround Errors 7.3.5 轉換錯誤
A Turnaround procedure always starts from a Stop State. The procedure begins with a sequence of LowPower States ending with a Bridge State (LP-00) during which drive sides are swapped. The procedure is finalized by the response including a Turn State followed by a Stop State driven from the other side. If the actual sequence of events violates the normal Turnaround procedure a “False Control Error” may be flagged to the Protocol. See Section 7.2.6. The Turn State response serves as an acknowledgement for the correctly completed Turnaround procedure. If no acknowledgement is observed within a certain time period the Protocol should time-out and take appropriate action. This period should be larger than the maximum possible Turnaround time for a particular system. There is no time-out for this condition in the PHY. 轉向程序總是從停止狀態開始。該程序以一系列低功耗狀態開始，並以橋接狀態（LP-00）結束，在此期間交換驅動側。該程序以包括轉向狀態的響應結束，然後是從另一側驅動的停止狀態。如果實際事件序列違反正常的轉向程序，則可能會向協議標記“虛假控制錯誤”。請參見第 7.2.6 節。轉向狀態響應作為對正確完成的轉向程序的確認。如果在一定時間內未觀察到確認，則協議應超時並採取適當行動。此期間應大於特定系統的最大可能轉向時間。在 PHY 中對此條件沒有超時。
8 Interconnect and Lane Configuration 8 互連和通道配置
The interconnect between transmitter and receiver carries all signals used in D-PHY communication. This includes both high speed, low voltage signaling I/O technology and low speed, low power signaling for control functions. For this reason, the physical connection shall be implemented by means of balanced, differential, point-to-point transmission lines referenced to ground. The total interconnect may consist of several cascaded transmission line segments, such as, printed circuit boards, flex-foils, and cable connections. 發射器和接收器之間的互連承載了 D-PHY 通信中使用的所有信號。這包括高速、低電壓信號 I/O 技術和低速、低功耗的控制功能信號。因此，物理連接應通過平衡的差分點對點傳輸線實現，並以地面為參考。總互連可能由幾個級聯的傳輸線段組成，例如印刷電路板、柔性電路板和電纜連接。
Figure 29 Point-to-point Interconnect 圖 29 點對點互連
8.1 Lane Configuration 8.1 車道配置
The complete physical connection of a Lane consists of a transmitter (TX), and/or receiver (RX) at each side, with some Transmission-Line-Interconnect-Structure (TLIS) in between. The overall Lane performance is therefore determined by the combination of these three elements. The split between these elements is defined to be on the module (IC) pins. This section defines both the required performance of the Transmission-Line-Interconnect-Structure for the signal routing as well as the I/O-cell Reflection properties of TX and RX. This way the correct overall operation of the Lane can be ensured. 一條通道的完整物理連接由每側的發射器（TX）和/或接收器（RX）組成，中間有一些傳輸線互連結構（TLIS）。因此，整體通道性能由這三個元素的組合決定。這些元素之間的分界定義為模塊（IC）引腳。這一部分定義了信號路由所需的傳輸線互連結構的性能以及 TX 和 RX 的 I/O 單元反射特性。這樣可以確保通道的正確整體操作。
With respect to physical dimensions, the Transmission-Line-Interconnect-Structure will typically be the largest part. Besides printed circuit board and flex-foil traces, this may also include elements such as vias and connectors. 在物理尺寸方面，傳輸線互連結構通常是最大的部分。除了印刷電路板和柔性電路板的導線外，這還可能包括如通孔和連接器等元件。
8.2 Boundary Conditions 8.2 邊界條件
The reference characteristic impedance level is 100 Ohm differential, 50 Ohm single-ended per Line, and 25 Ohm common-mode for both Lines together. The 50 Ohm impedance level for single-ended operation is also convenient for test and characterization purposes. 參考特性阻抗水平為 100 歐姆差分、每條線 50 歐姆單端，以及兩條線共同的 25 歐姆共模。50 歐姆的單端操作阻抗水平對於測試和特性化目的也很方便。
This typical impedance level is required for all three parts of the Lane: TX, TLIS, and RX. The tolerances for characteristic impedances of the interconnect and the tolerance on line termination impedances for TX and RX are specified by means of S-parameter templates over the whole operating frequency range. 這個典型的阻抗水平是所有三個部分的要求：TX、TLIS 和 RX。互連的特徵阻抗的公差以及 TX 和 RX 的線終端阻抗的公差是通過整個操作頻率範圍的 S 參數模板來指定的。
The differential channel is also used for LP single-ended signaling. Therefore, it is strongly recommended to apply only very loosely coupled differential transmission lines. 差分通道也用於 LP 單端信號傳輸。因此，強烈建議僅使用非常鬆散耦合的差分傳輸線。
The flight time for signals across the interconnect shall not exceed two nanoseconds. 信號在互連中的飛行時間不得超過兩納秒。
8.3 Definitions 8.3 定義
The frequency ‘fh’ is the fundamental frequency of the operating data rate, e.g. for an operating data rate of 1Gb//s1 \mathrm{~Gb} / \mathrm{s} ‘fh’ is 500 MHz . 頻率‘fh’是操作數據速率的基頻，例如，對於操作數據速率為 1Gb//s1 \mathrm{~Gb} / \mathrm{s} 時，‘fh’為 500 MHz。
The frequency ’ fh_(MAX)\mathrm{fh}_{\mathrm{MAX}} ’ is a device specification and indicates the maximum supported fh for a particular device. 頻率 ' fh_(MAX)\mathrm{fh}_{\mathrm{MAX}} ' 是設備規範，表示特定設備支持的最大 fh。
The frequency ’ f_(LP,MAX)\mathrm{f}_{\mathrm{LP}, \mathrm{MAX}} ’ is the maximum toggle frequency for Low-Power mode. 頻率 ' f_(LP,MAX)\mathrm{f}_{\mathrm{LP}, \mathrm{MAX}} ' 是低功耗模式的最大切換頻率。
RF interference frequencies are denoted by ’ f_(INT)\mathrm{f}_{\mathrm{INT}} ', where f_(INT,MIN)\mathrm{f}_{\mathrm{INT}, \mathrm{MIN}} defines the lower bound for the band of relevant RF interferers. RF 干擾頻率用 ' f_(INT)\mathrm{f}_{\mathrm{INT}} ' 表示，其中 f_(INT,MIN)\mathrm{f}_{\mathrm{INT}, \mathrm{MIN}} 定義了相關 RF 干擾源的頻帶下限。
The frequency f_(MAX)\mathrm{f}_{\mathrm{MAX}} for devices supporting data rates up to 1.5 Gbps is defined by the maximum of (1//5t_(F,MIN),1//5t_(R,MIN))\left(1 / 5 t_{F, M I N}, 1 / 5 t_{R, M I N}\right), where t_(R)t_{R} and t_(F)t_{F} are the rise and fall times of the High-Speed signaling. 支持高達 1.5 Gbps 數據速率的設備的頻率 f_(MAX)\mathrm{f}_{\mathrm{MAX}} 由 (1//5t_(F,MIN),1//5t_(R,MIN))\left(1 / 5 t_{F, M I N}, 1 / 5 t_{R, M I N}\right) 的最大值定義，其中 t_(R)t_{R} 和 t_(F)t_{F} 是高速信號的上升和下降時間。
For devices supporting data rates of more than 1.5Gbps,f_(MAX)1.5 \mathrm{Gbps}, \mathrm{f}_{\mathrm{MAX}} is 3//43 / 4 * data rate. 對於支持超過 1.5Gbps,f_(MAX)1.5 \mathrm{Gbps}, \mathrm{f}_{\mathrm{MAX}} 的數據速率的設備，數據速率為 3//43 / 4 * 數據速率。
The frequency ’ fh_(MIN)\mathrm{fh}_{\mathrm{MIN}} ’ is defined as fh_(MIN)=fh//10\mathrm{fh}_{\mathrm{MIN}}=\mathrm{fh} / 10. 頻率 ' fh_(MIN)\mathrm{fh}_{\mathrm{MIN}} ' 定義為 fh_(MIN)=fh//10\mathrm{fh}_{\mathrm{MIN}}=\mathrm{fh} / 10 。
8.4 S-parameter Specifications 8.4 S-參數規格
The required performance of the physical connection is specified by means of S-parameter requirements for TX, TLIS, and RX, for TLIS by mixed-mode, 4-port parameters, and for RX and TX by mixed-mode, reflection (return loss) parameters. The S-parameter limits are defined over the whole operating frequency range by means of templates. 物理連接所需的性能是通過對 TX、TLIS 和 RX 的 S 參數要求來指定的，對 TLIS 則是通過混合模式、4 端口參數，而對 RX 和 TX 則是通過混合模式、反射（回損）參數來指定。S 參數限制是通過模板在整個工作頻率範圍內定義的。
The differential transmission properties are most relevant and therefore this specification uses mixed-mode parameters. As the performance needs depend on the targeted bit rates, most S-parameter requirements are specified on a normalized frequency axis with respect to bit rate. Only the parameters that are important for the suppression of external (RF) interference are specified on an absolute frequency scale. This scale extends up to f_("MAX. ")\mathrm{f}_{\text {MAX. }}. Beyond this frequency the circuitry itself shall suppress the high-frequency interference signals sufficiently. 差分傳輸特性最為相關，因此本規範使用混合模式參數。由於性能需求取決於目標比特率，大多數 S 參數要求是在相對於比特率的標準化頻率軸上指定的。只有對於抑制外部（射頻）干擾重要的參數是在絕對頻率尺度上指定的。此尺度延伸至 f_("MAX. ")\mathrm{f}_{\text {MAX. }} 。超過此頻率，電路本身應能夠充分抑制高頻干擾信號。
Only the overall performance of the TLIS and the maximum reflection of RX and TX are specified. This fully specifies the signal behavior at the RX/TX-module pins. The subdivision of losses, reflections and mode-conversion budget to individual physical fractions of the TLIS is left to the system designer. Annex B includes some rules of thumb for system design and signal routing guidelines. 僅指定 TLIS 的整體性能以及 RX 和 TX 的最大反射。這完全指定了 RX/TX 模塊引腳的信號行為。損耗、反射和模式轉換預算的細分留給系統設計師。附錄 B 包括一些系統設計的經驗法則和信號路由指導方針。
8.5 Characterization Conditions 8.5 特徵化條件
All S-parameter definitions are based on a 50 Omega50 \Omega impedance reference level. The characterization can be done with a measurement system, as shown in Figure 30. 所有 S 參數定義都是基於 50 Omega50 \Omega 阻抗參考水平。特性可以通過測量系統進行，如圖 30 所示。
Figure 30 Set-up for S-parameter Characterization of RX, TX and TLIS 圖 30 RX、TX 和 TLIS 的 S 參數特性測試設置
The syntax of S-parameters is S[measured-mode][driven-mode][measured-port][driven-port]. Examples: Sdd21of TLIS is the differential signal at port 2 due to a differential signal driven at port 1; Sdc22 is the measured differential reflected signal at port 2 due to a common signal driven at port 2 . S-參數的語法是 S[測量模式][驅動模式][測量端口][驅動端口]。例子：Sdd21of TLIS 是由端口 1 驅動的差分信號在端口 2 的差分信號；Sdc22 是由端口 2 驅動的共模信號在端口 2 測量的差分反射信號。
8.6 Interconnect Specifications 8.6 互連規範
The Transmission-Line Signal-Routing (TLSR) is specified by means of mixed-mode 4-port S-parameter behavior templates over the frequency range. This includes the differential and common-mode, insertion and return losses, and mode-conversion limitations. 傳輸線信號路由（TLSR）是通過混合模式 4 端口 S 參數行為模板在頻率範圍內進行規範的。這包括差分和共模、插入損耗和回波損耗，以及模式轉換限制。
8.6.1 Differential Characteristics 8.6.1 差異特徵
8.6.1.1 Differential Insertion Loss for Data Rate >= 80\geq \mathbf{8 0} Mbps and <= 1.5\leq \mathbf{1 . 5} Gbps 8.6.1.1 數據速率 >= 80\geq \mathbf{8 0} Mbps 和 <= 1.5\leq \mathbf{1 . 5} Gbps 的差分插入損耗
The differential transfer behavior (insertion loss) of the TLIS when supporting data rates >= 80Mbps\geq 80 \mathrm{Mbps} and <= 1.5\leq 1.5 Gbps shall meet the Sdd21 template shown in Figure 31, where i!=j\mathrm{i} \neq \mathrm{j}. 當支持數據速率 >= 80Mbps\geq 80 \mathrm{Mbps} 和 <= 1.5\leq 1.5 Gbps 時，TLIS 的差分傳輸行為（插入損耗）應符合圖 31 中顯示的 Sdd21 模板，其中 i!=j\mathrm{i} \neq \mathrm{j} 。
8.6.1.2 Differential Insertion Loss for Data Rate > 1.5 Gbps and <=\leq 4.5 Gbps 8.6.1.2 數據速率 > 1.5 Gbps 和 <=\leq 4.5 Gbps 的差分插入損耗
The differential transfer behavior (insertion loss) of the TLIS when supporting data rates > 1.5 Gbps and <= 4.5\leq 4.5 Gbps shall meet the Sdd21 template shown in Figure 32, where i!=j\mathrm{i} \neq \mathrm{j}. 當支持數據速率 > 1.5 Gbps 和 <= 4.5\leq 4.5 Gbps 時，TLIS 的差分傳輸行為（插入損耗）應符合圖 32 中顯示的 Sdd21 模板，其中 i!=j\mathrm{i} \neq \mathrm{j} 。
Figure 32 Template for Differential Insertion Losses, Data Rates > 1.5 Gbps and <= 4.5\leq 4.5 Gbps 圖 32 差分插入損耗模板，數據速率 > 1.5 Gbps 和 <= 4.5\leq 4.5 Gbps
Three Reference channels (Short, Standard & Long) are defined to support a wide range of display and camera applications. 定義了三個參考通道（短、標準和長）以支持廣泛的顯示和攝像頭應用。
Standard Reference channel is a default requirement and the transmitters/receivers shall support it. 標準參考通道是默認要求，發射器/接收器應支持它。
Short Reference channel support is optional. In applications targeting lower interconnect loss, and when the Transmitter or the Receiver support the optional power saving modes, this channel can be referenced for better system power optimization. 短參考通道支援是可選的。在針對較低互連損耗的應用中，當發射器或接收器支援可選的省電模式時，可以參考此通道以實現更好的系統功率優化。
Long Reference Channel support is optional. This is aimed at supporting higher loss interconnect like Chip-On-Glass (COG). In order to support such an interconnect, the data rate may need to be limited. COG interconnect is used for display panels and has reduced cost compared to other solutions. However, it increases the total loss of interconnect due to additional routing on the glass, bonding between the glass and PCB, and bonding between the glass and silicon. The maximum data rate recommended with the long channel is 2.5 Gbps . 長參考通道支持是可選的。這旨在支持更高損耗的互連，如玻璃芯片（COG）。為了支持這種互連，數據速率可能需要受到限制。COG 互連用於顯示面板，與其他解決方案相比，成本降低。然而，由於在玻璃上的額外布線、玻璃與 PCB 之間的粘合以及玻璃與矽之間的粘合，它增加了互連的總損耗。長通道推薦的最大數據速率為 2.5 Gbps。
Specific guidance on using these reference channels is provided in Section 10.4. 在第 10.4 節中提供了有關使用這些參考通道的具體指導。
8.6.1.3 Differential Reflection Loss for Data Rate >= 80\geq 80 Mbps and <=\leq 1.5 Gbps 8.6.1.3 數據速率 >= 80\geq 80 Mbps 和 <=\leq 1.5 Gbps 的差分反射損失
When supported data rates are >= 80Mbps\geq 80 \mathrm{Mbps} and <= 1.5Gbps\leq 1.5 \mathrm{Gbps}, the differential reflection for both ports of the TLIS is specified by Sdd11 and Sdd22, and should match the template shown in Figure 33. Not meeting the differential reflection coefficient might impact interoperability and operation. 當支持的數據速率為 >= 80Mbps\geq 80 \mathrm{Mbps} 和 <= 1.5Gbps\leq 1.5 \mathrm{Gbps} 時，TLIS 的兩個端口的差分反射由 Sdd11 和 Sdd22 指定，並應符合圖 33 中顯示的模板。不符合差分反射係數可能會影響互操作性和操作。
Figure 33 Template for Differential Reflection at Both Ports 圖 33 兩端口差分反射的模板
8.6.1.4 Differential Reflection Loss for Data Rate >1.5 Gbps and <=\leq 4.5 Gbps 8.6.1.4 數據速率 >1.5 Gbps 和 <=\leq 4.5 Gbps 的差分反射損失
When supported data rates are > 1.5Gbps>1.5 \mathrm{Gbps} and <= 4.5Gbps\leq 4.5 \mathrm{Gbps}, the differential reflection for both ports of the TLIS is specified by Sdd11 and Sdd22, and should be better than -12 dB in the range from 0 to fmax. Not meeting the differential reflection coefficient might impact interoperability and operation. 當支持的數據速率為 > 1.5Gbps>1.5 \mathrm{Gbps} 和 <= 4.5Gbps\leq 4.5 \mathrm{Gbps} 時，TLIS 的兩個端口的差分反射由 Sdd11 和 Sdd22 指定，並且在 0 到 fmax 的範圍內應該好於 -12 dB。不符合差分反射係數可能會影響互操作性和操作。
8.6.2 Common-mode Characteristics 8.6.2 共模特性
The common-mode insertion loss is implicitly specified by means of the differential insertion loss and the Intra-Lane cross coupling. The requirements for common-mode insertion loss are therefore equal to the differential requirements. 共模插入損耗是通過差分插入損耗和車道內交叉耦合隱式指定的。因此，對共模插入損耗的要求等同於差分要求。
8.6.3 Intra-Lane Cross-Coupling 8.6.3 車道內交叉耦合
The two lines applied as a differential pair during HS transmission are also used individually for singleended signaling during Low-Power mode. Therefore, the coupling between the two wires shall be restricted in order to limit single-ended cross coupling. The coupling between the two wires is defined as the difference of the S-parameters Scc21 and Sdd21 or Scc12 and Sdd12. In either case, the difference shall not exceed -20 dB for frequencies up to 10**f_("LP,MAX ")10 * \mathrm{f}_{\text {LP,MAX }}. 在高頻傳輸期間應用作差分對的兩條線在低功耗模式下也單獨用於單端信號傳輸。因此，兩根線之間的耦合應受到限制，以限制單端交叉耦合。兩根線之間的耦合定義為 S 參數 Scc21 和 Sdd21 或 Scc12 和 Sdd12 的差值。在任何情況下，該差值在頻率高達 10**f_("LP,MAX ")10 * \mathrm{f}_{\text {LP,MAX }} 時不得超過-20 dB。
8.6.4 Mode-Conversion Limits 8.6.4 模式轉換限制
All mixed-mode, 4-port S-parameters for differential to common-mode conversion, and vice-versa, shall not exceed -26 dB for frequencies below f_("MAx ")\mathrm{f}_{\text {MAx }}. This includes Sdc12, Scd21, Scd12, Sdc21, Scd11, Sdc11, Scd22, and Sdc22. 所有混合模式、4 端口的 S 參數在差分到共模轉換及反向轉換時，對於低於 f_("MAx ")\mathrm{f}_{\text {MAx }} 的頻率不得超過-26 dB。這包括 Sdc12、Scd21、Scd12、Sdc21、Scd11、Sdc11、Scd22 和 Sdc22。
8.6.5 Inter-Lane Cross-Coupling 8.6.5 車道間交叉耦合
The common-mode and differential inter-Lane cross coupling between Lanes (clock and data) shall meet the requirements as shown in Figure 34 and Figure 35, respectively. Lanes（時鐘和數據）之間的共模和差模交叉耦合應符合圖 34 和圖 35 所示的要求。
The difference in signal delay between any Data Lane and the Clock Lane shall be less than UI/50 for all frequencies up to, and including, fh when the supported data rate is less than or equal to 1.5 Gbps . For data rates higher than 1.5 Gbps , refer to Table 30. 任何數據通道與時鐘通道之間的信號延遲差異應小於 UI/50，適用於所有頻率，直到 fh 為止，並包括 fh，當支持的數據速率小於或等於 1.5 Gbps 時。對於高於 1.5 Gbps 的數據速率，請參考表 30。
(∣Sdd 12" data "(varphi)-Sdd 12 clock(varphi)∣)/(omega) < (" UI ")/(50)" Driver and Receiver Characteristics "\frac{\mid \operatorname{Sdd} 12 \text { data }(\varphi)-\operatorname{Sdd} 12 \operatorname{clock}(\varphi) \mid}{\omega}<\frac{\text { UI }}{50} \text { Driver and Receiver Characteristics }
8.7 Driver and Receiver Characteristics 8.7 驅動器和接收器特性
Besides the TLIS the Lane consists of two RX-TX modules, one at each side. This paragraph specifies the reflection behavior (return loss) of these RX-TX modules in HS-mode. The signaling characteristics of all possible functional blocks inside the RX-TX modules can be found in Section 9. 除了 TLIS，通道由兩個 RX-TX 模塊組成，每側一個。本段落指定了這些 RX-TX 模塊在 HS 模式下的反射行為（回損）。所有可能的功能區塊的信號特性可以在第 9 節中找到。
8.7.1 Differential Characteristics 8.7.1 差異特徵
The differential reflection of a Lane Module in High-Speed RX mode is specified by the template shown in Figure 36. 在高速接收模式下，Lane 模組的差分反射由圖 36 所示的模板指定。
Figure 36 Differential Reflection Template for Lane Module Receivers 圖 36 差異反射模板用於通道模組接收器
The differential reflection of a Lane Module in High-Speed TX mode is specified by the template shown in Figure 37. 在高速傳輸模式下，Lane 模組的差分反射由圖 37 所示的模板規定。
Figure 37 Differential Reflection Template for Lane Module Transmitters 圖 37 差異反射模板用於通道模組發射器
8.7.2 Common-Mode Characteristics 8.7.2 共模特性
The common-mode return loss specification is different for a High-Speed TX and RX mode, because the RX is not DC terminated to ground. The common-mode reflection of a Lane Module in High-Speed TX mode shall be less than -6 dB from f_(LP,MAX)\mathrm{f}_{\mathrm{LP}, \mathrm{MAX}} up to f_("MAX ")\mathrm{f}_{\text {MAX }} for devices supporting data rates up to 1.5 Gbps , 2.5 dB for devices supporting data rates up to 2.5 Gbps , and -1 dB for devices supporting data rates up to 4.5 Gbps. 高速度 TX 和 RX 模式的共模回損規範不同，因為 RX 並未以直流接地終端。在高速度 TX 模式下，通道模組的共模反射應小於-6 dB，範圍從 f_(LP,MAX)\mathrm{f}_{\mathrm{LP}, \mathrm{MAX}} 到 f_("MAX ")\mathrm{f}_{\text {MAX }} ，適用於支持高達 1.5 Gbps 數據速率的設備，對於支持高達 2.5 Gbps 數據速率的設備為 2.5 dB，對於支持高達 4.5 Gbps 數據速率的設備為-1 dB。
The common-mode reflection of a Lane Module in High-Speed RX mode shall conform to the limits specified by the template shown in Figure 38. Assuming a high DC common-mode impedance, this implies a sufficiently large capacitor at the termination center tap. The minimum value allows integration. While the common-mode termination is especially important for reduced influence of RF interferers, the RX requirement limits reflection for the most relevant frequency band. 在高速接收模式下，Lane 模組的共模反射應符合圖 38 所示模板中規定的限制。假設高直流共模阻抗，這意味著在終端中心抽頭處需要一個足夠大的電容器。最小值允許集成。雖然共模終端對於減少射頻干擾者的影響特別重要，但接收要求限制了最相關頻帶的反射。
Figure 38 Template for RX Common-Mode Return Loss 圖 38 RX 共模回損模板
8.7.3 Mode-Conversion Limits 8.7.3 模式轉換限制
The differential to common-mode conversion limits of RXR X shall be -26 dB-26 d B up to f_("MAX ")f_{\text {MAX }}. 差分到共模轉換的限制為 -26 dB-26 d B 最高可達 f_("MAX ")f_{\text {MAX }} 。
9 Electrical Characteristics 9 電氣特性
A PHY may contain the following electrical functions: a High-Speed Transmitter (HS-TX), a High-Speed Receiver (HS-RX), a Low-Power Transmitter (LP-TX), a Low-Power Receiver (LP-RX), and a Low-Power Contention Detector (LP-CD). A PHY does not need to contain all electrical functions, only the functions that are required for a particular PHY configuration. The required functions for each configuration are specified in Section 5. All electrical functions included in any PHY shall meet the specifications in this section. Figure 39 shows the complete set of electrical functions required for a fully featured PHY transceiver. 一個 PHY 可能包含以下電氣功能：高速發射器（HS-TX）、高速接收器（HS-RX）、低功耗發射器（LP-TX）、低功耗接收器（LP-RX）和低功耗競爭檢測器（LP-CD）。一個 PHY 不需要包含所有電氣功能，只需包含特定 PHY 配置所需的功能。每個配置所需的功能在第 5 節中指定。任何 PHY 中包含的所有電氣功能必須符合本節中的規範。圖 39 顯示了完全功能 PHY 收發器所需的完整電氣功能集。
Figure 39 Electrical Functions of a Fully Featured D-PHY Transceiver 圖 39 完整功能 D-PHY 收發器的電氣功能
The HS transmitter and HS receiver are used for the transmission of the HS data and clock signals. The HS transmitter and receiver use low-voltage differential signaling for signal transmission. The HS receiver contains a switchable parallel termination. HS 發射器和 HS 接收器用於傳輸 HS 數據和時鐘信號。HS 發射器和接收器使用低電壓差分信號進行信號傳輸。HS 接收器包含可切換的並行終端。
The LP transmitter and LP receiver serve as a low power signaling mechanism. The LP transmitter is a push-pull driver and the LP receiver is an un-terminated, single-ended receiver. LP 發射器和 LP 接收器作為低功率信號機制。LP 發射器是一個推拉驅動器，而 LP 接收器是一個未終止的單端接收器。
The signal levels are different for differential HS mode and single-ended LP mode. Figure 40 shows both the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below the LP low-level input threshold such that LP receiver always detects low on HS signals. 差分 HS 模式和單端 LP 模式的信號水平不同。圖 40 分別顯示了 HS 和 LP 信號水平在左側和右側。HS 信號水平低於 LP 低電平輸入閾值，因此 LP 接收器在 HS 信號上始終檢測到低電平。
All absolute voltage levels are relative to the ground voltage at the transmit side. 所有絕對電壓水平均相對於發射端的接地電壓。
Figure 40 D-PHY Signaling Levels 圖 40 D-PHY 信號電平
A Lane switches between Low-Power and High-Speed mode during normal operation. Bidirectional Lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events shall not cause glitches on the Lines that would result in a detection of an incorrect signal level. Therefore, all mode and direction changes shall be smooth to always ensure a proper detection of the Line signals. 在正常操作中，通道在低功耗模式和高速模式之間切換。雙向通道也可以切換通信方向。操作模式或方向的變更需要啟用和禁用某些電氣功能。這些啟用和禁用事件不得在通道上引起故障，導致檢測到不正確的信號水平。因此，所有模式和方向的變更應該是平滑的，以始終確保正確檢測通道信號。
9.1 Driver Characteristics 9.1 駕駛員特徵
9.1.1 High-Speed Transmitter 9.1.1 高速發射器
9.1.1.1 Differential & Common Mode Swing 9.1.1.1 差模與共模擺幅
A HS differential signal driven on the Dp and Dn pins is generated by a differential output driver. For reference, Dp is considered as the positive side and Dn as the negative side. The Lane state is called Differential-1 (HS-1) when the potential on Dp is higher than the potential of Dn. The Lane state is called Differential-0 (HS-0), when the potential on Dp is lower than the potential of Dn. Figure 41 shows an example implementation of a HS transmitter. 在 Dp 和 Dn 引腳上驅動的 HS 差分信號是由差分輸出驅動器生成的。作為參考，Dp 被視為正側，Dn 則為負側。當 Dp 上的電位高於 Dn 的電位時，通道狀態稱為差分-1（HS-1）。當 Dp 上的電位低於 Dn 的電位時，通道狀態稱為差分-0（HS-0）。圖 41 顯示了一個 HS 發射器的實現示例。
Note, this section uses Dp and Dn to reference the pins of a Lane Module regardless of whether the pins belong to a Clock Lane Module or a Data Lane Module. 注意，本節使用 Dp 和 Dn 來引用通道模組的引腳，無論這些引腳是否屬於時鐘通道模組或數據通道模組。
Figure 41 Example HS Transmitter 圖 41 示例 HS 發射器
The differential output voltage V_(OD)\mathrm{V}_{\mathrm{OD}} is defined as the difference of the voltages V_(DP)\mathrm{V}_{\mathrm{DP}} and V_(DN)\mathrm{V}_{\mathrm{DN}} at the Dp and Dn pins, respectively. 差分輸出電壓 V_(OD)\mathrm{V}_{\mathrm{OD}} 定義為 Dp 和 Dn 引腳上電壓 V_(DP)\mathrm{V}_{\mathrm{DP}} 和 V_(DN)\mathrm{V}_{\mathrm{DN}} 的差值。
V_(OD)=V_(DP)-V_(DN)V_{O D}=V_{D P}-V_{D N}
The output voltages V_(DP)\mathrm{V}_{\mathrm{DP}} and V_(DN)\mathrm{V}_{\mathrm{DN}} at the Dp and Dn pins shall not exceed the High-Speed output high voltage Vohнs. Volhs is the High-Speed output, low voltage on Dp and Dn and is determined by Vod and V_("смтx. ")\mathrm{V}_{\text {смтx. }} The High-Speed V_("out ")\mathrm{V}_{\text {out }} is bounded by the minimum value of V_("olhs ")\mathrm{V}_{\text {olhs }} and the maximum value of Voннs. Dp 和 Dn 引腳上的輸出電壓 V_(DP)\mathrm{V}_{\mathrm{DP}} 和 V_(DN)\mathrm{V}_{\mathrm{DN}} 不得超過高速輸出高電壓 Vohнs。Volhs 是 Dp 和 Dn 上的高速輸出低電壓，並由 Vod 和 V_("смтx. ")\mathrm{V}_{\text {смтx. }} 決定。高速 V_("out ")\mathrm{V}_{\text {out }} 受限於 V_("olhs ")\mathrm{V}_{\text {olhs }} 的最小值和 Voннs 的最大值。
The common-mode voltage V_("CMTX ")\mathrm{V}_{\text {CMTX }} is defined as the arithmetic mean value of the voltages at the Dp and Dn pins: 共模電壓 V_("CMTX ")\mathrm{V}_{\text {CMTX }} 定義為 Dp 和 Dn 引腳電壓的算術平均值：
V_(CMTX)=(V_(DP)+V_(DN))/(2)V_{C M T X}=\frac{V_{D P}+V_{D N}}{2}
V_("OD ")V_{\text {OD }} and V_("CMTx ")\mathrm{V}_{\text {CMTx }} are graphically shown in Figure 42 for ideal HS signals. Figure 43 shows single-ended HS signals with the possible kinds of distortion of the differential output and common-mode voltages. V V_(OD)\mathrm{V}_{\mathrm{OD}} and V_("Смтх ")\mathrm{V}_{\text {Смтх }} may be slightly different for driving a Differential-1 or a Differential-0 on the pins. V_("OD ")V_{\text {OD }} 和 V_("CMTx ")\mathrm{V}_{\text {CMTx }} 在圖 42 中以理想的 HS 信號圖形顯示。圖 43 顯示了單端 HS 信號及其差分輸出和共模電壓的可能失真類型。V V_(OD)\mathrm{V}_{\mathrm{OD}} 和 V_("Смтх ")\mathrm{V}_{\text {Смтх }} 在驅動引腳上的 Differential-1 或 Differential-0 時可能會略有不同。
9.1.1.2 Differential Voltage Mismatch 9.1.1.2 差分電壓不匹配
The output differential voltage mismatch DeltaV_(OD)\Delta \mathrm{V}_{\mathrm{OD}} is defined as the difference of the absolute values of the differential output voltage in the Differential-1 state V_(OD(1))\mathrm{V}_{\mathrm{OD}(1)} and the differential output voltage in the Differential-0 state V_(OD(0))\mathrm{V}_{\mathrm{OD}(0)}. This is expressed by: 差分輸出電壓不匹配 DeltaV_(OD)\Delta \mathrm{V}_{\mathrm{OD}} 定義為在差分-1 狀態 V_(OD(1))\mathrm{V}_{\mathrm{OD}(1)} 和差分-0 狀態 V_(OD(0))\mathrm{V}_{\mathrm{OD}(0)} 中差分輸出電壓的絕對值之差。這可以表示為：
9.1.1.3 Static Common Mode Mismatch & Transient Common Mode Voltage 9.1.1.3 靜態共模不匹配與瞬態共模電壓
If V_("Смтx (1) ")\mathrm{V}_{\text {Смтx (1) }} and V_("CмTх(0) ")\mathrm{V}_{\text {CмTх(0) }} are the common-mode voltages for static Differential-1 and Differential-0 states respectively, then the common-mode reference voltage is defined by: 如果 V_("Смтx (1) ")\mathrm{V}_{\text {Смтx (1) }} 和 V_("CмTх(0) ")\mathrm{V}_{\text {CмTх(0) }} 分別是靜態差分-1 和差分-0 狀態的共模電壓，那麼共模參考電壓定義為：
V_("CMTX,REF ")=(V_(CMTX(1))+V_(CMTX(0)))/(2)V_{\text {CMTX,REF }}=\frac{V_{C M T X(1)}+V_{C M T X(0)}}{2}
The transient common-mode voltage variation is defined by: 瞬態共模電壓變化定義為：
The static common-mode voltage mismatch between the Differential-1 and Differential-0 state is given by: 差分-1 和差分-0 狀態之間的靜態共模電壓不匹配為：
DeltaV_(CMTX(1,0))=(V_(CMTX(1))-V_(CMTX(0)))/(2)\Delta V_{C M T X(1,0)}=\frac{V_{C M T X(1)}-V_{C M T X(0)}}{2}
The transmitter shall send data such that the high frequency and low frequency common-mode voltage variations do not exceed DeltaV_(CMTX(HF))\Delta \mathrm{V}_{\mathrm{CMTX}(\mathrm{HF})} and DeltaV_(CMTX(LF))\Delta \mathrm{V}_{\mathrm{CMTX}(\mathrm{LF})}, respectively. An example test circuit for the measurement of V_(OD)\mathrm{V}_{\mathrm{OD}} and V_(CMTX)\mathrm{V}_{\mathrm{CMTX}} is shown in Figure 44. 發射器應發送數據，使得高頻和低頻共模電壓變化分別不超過 DeltaV_(CMTX(HF))\Delta \mathrm{V}_{\mathrm{CMTX}(\mathrm{HF})} 和 DeltaV_(CMTX(LF))\Delta \mathrm{V}_{\mathrm{CMTX}(\mathrm{LF})} 。圖 44 顯示了測量 V_(OD)\mathrm{V}_{\mathrm{OD}} 和 V_(CMTX)\mathrm{V}_{\mathrm{CMTX}} 的示例測試電路。
Figure 43 Possible DeltaV_("CMTX ")\Delta V_{\text {CMTX }} and DeltaV_("OD ")\Delta V_{\text {OD }} Distortions of the Single-ended HS Signals 圖 43 單端 HS 信號的可能 DeltaV_("CMTX ")\Delta V_{\text {CMTX }} 和 DeltaV_("OD ")\Delta V_{\text {OD }} 失真
Figure 44 Example Circuit for VCMTX and VOD Measurements 圖 44 VCMTX 和 VOD 測量的示例電路
9.1.1.4 Output Resistance 9.1.1.4 輸出電阻
The single-ended output impedance of the transmitter at both the Dp and Dn pins is denoted by Z_(O).DeltaZ_(Os)\mathrm{Z}_{\mathrm{O}} . \Delta \mathrm{Z}_{\mathrm{Os}} is the mismatch of the single ended output impedances at the Dp and Dn pins, denoted by Z_(OSDP)\mathrm{Z}_{\mathrm{OSDP}} and Z_(OSDN)\mathrm{Z}_{\mathrm{OSDN}}, respectively. This mismatch is defined as the ratio of the absolute value of the difference of Z_("OSDP ")\mathrm{Z}_{\text {OSDP }} and Z_("OSDN ")\mathrm{Z}_{\text {OSDN }} and the average of those impedances: 發射器在 Dp 和 Dn 引腳的單端輸出阻抗用 Z_(O).DeltaZ_(Os)\mathrm{Z}_{\mathrm{O}} . \Delta \mathrm{Z}_{\mathrm{Os}} 表示，Dp 和 Dn 引腳的單端輸出阻抗不匹配，用 Z_(OSDP)\mathrm{Z}_{\mathrm{OSDP}} 和 Z_(OSDN)\mathrm{Z}_{\mathrm{OSDN}} 分別表示。這種不匹配定義為 Z_("OSDP ")\mathrm{Z}_{\text {OSDP }} 和 Z_("OSDN ")\mathrm{Z}_{\text {OSDN }} 之差的絕對值與這些阻抗的平均值之比：
The output impedance Z_(OS)\mathrm{Z}_{\mathrm{OS}} and the output impedance mismatch DeltaZ_(OS)\Delta \mathrm{Z}_{\mathrm{OS}} shall be compliant with Table 20 for both the Differential-0 and Differential-1 states for all allowed loading conditions. It is recommended that implementations keep the output impedance during state transitions as close as possible to the steady state value. The output impedance Z_(OS)\mathrm{Z}_{\mathrm{OS}} can be determined by injecting an AC current into the Dp and Dn pins and measuring the peak-to-peak voltage amplitude. 输出阻抗 Z_(OS)\mathrm{Z}_{\mathrm{OS}} 和输出阻抗不匹配 DeltaZ_(OS)\Delta \mathrm{Z}_{\mathrm{OS}} 应符合表 20 的要求，适用于所有允许的负载条件下的差分状态 0 和差分状态 1。建议在状态转换期间，实施方案尽可能保持输出阻抗接近稳态值。输出阻抗 Z_(OS)\mathrm{Z}_{\mathrm{OS}} 可以通过向 Dp 和 Dn 引脚注入交流电流并测量峰峰电压幅度来确定。
9.1.1.5 Rise/Fall Times 9.1.1.5 上升/下降時間
The rise and fall times, t_(R)\mathrm{t}_{\mathrm{R}} and t_(F)\mathrm{t}_{\mathrm{F}}, are defined as the transition time between 20%20 \% and 80%80 \% of the full HS signal swing. Full HS Swing can be calculated by driving a steady state pattern. The driver shall meet the t_(R)t_{R} and t_(F)\mathrm{t}_{\mathrm{F}} specifications for all allowable Z_(ID)\mathrm{Z}_{\mathrm{ID}}. The specifications for TX common-mode return loss and the TX differential mode return loss can be found in Section 8. 上升和下降時間， t_(R)\mathrm{t}_{\mathrm{R}} 和 t_(F)\mathrm{t}_{\mathrm{F}} ，定義為完整 HS 信號擺動的 20%20 \% 和 80%80 \% 之間的過渡時間。完整 HS 擺動可以通過驅動穩態模式來計算。驅動器應滿足所有允許的 Z_(ID)\mathrm{Z}_{\mathrm{ID}} 的 t_(R)t_{R} 和 t_(F)\mathrm{t}_{\mathrm{F}} 規範。TX 共模回損和 TX 差分模式回損的規範可以在第 8 節中找到。
Rise/Fall Times are defined for a maximum data rate of 1.5 Gbps . For Data rates above 1.5 Gbps , the Eye diagram specification defined in section 10.2.3 governs the slew rate requirements of the transmitter. 上升/下降時間定義為最大數據速率為 1.5 Gbps。對於超過 1.5 Gbps 的數據速率，10.2.3 節中定義的眼圖規範規範了發射器的變化速率要求。
It is recommended that a High-Speed transmitter that is directly terminated at its pins should not generate any overshoot in order to minimize EMI. 建議直接在其引腳終止的高速發射器不應產生任何超調，以最小化電磁干擾。
9.1.1.6 Half Swing Mode 9.1.1.6 半擺模式
In the Half Swing mode, differential swing of the transmitter is reduced to half that of the default swing specification. This is an optional mode that a transmitter can choose to support for power savings. Transmitter Half Swing mode can be used with the Receiver either in terminated or unterminated mode. Half Swing mode is defined for a termination ZID. There is no transmitter parameter defined for the operation with an unterminated receiver, due to the difficulty of measuring excess reflections on the line. Refer to the Receiver termination condition in section 9.2.1. A Transmitter with full swing operation shall not operate with a Receiver in unterminated mode due to the violation of V_("оннs ")\mathrm{V}_{\text {оннs }}. 在半擺動模式下，發射器的差分擺動減少到默認擺動規範的一半。這是一種可選模式，發射器可以選擇支持以節省功耗。發射器半擺動模式可以與接收器一起使用，無論是終端模式還是非終端模式。半擺動模式是為終端 ZID 定義的。由於測量線路上過多反射的困難，未定義與非終端接收器操作的發射器參數。請參閱第 9.2.1 節中的接收器終端條件。由於違反 V_("оннs ")\mathrm{V}_{\text {оннs }} ，全擺動操作的發射器不得與非終端模式的接收器一起操作。
Figure 45 Common Mode and Differential Swing in Half Swing Mode versus Default 圖 45 半擺模式下的共模和差模擺幅與默認模式的比較
9.1.1.7 De-emphasis 9.1.1.7 降低重視
To mitigate additional channel-induced ISI above 2.5 Gbps , an HS-TX needs to use channel equalization in the form of de-emphasis. The transmitter de-emphasis has two taps, where the first tap is the cursor and the second tap is the first post-cursor. The taps are separated by UI and the transmitter de-emphasis ratio EQ_(TX)\mathrm{EQ}_{\mathrm{TX}} determines the de-emphasis level. Two de-emphasis ratios are defined. 為了減輕超過 2.5 Gbps 的額外通道引起的 ISI，HS-TX 需要使用去強調形式的通道均衡。發射器去強調有兩個抽頭，其中第一個抽頭是游標，第二個抽頭是第一個後游標。抽頭之間的間隔為 UI，發射器去強調比率 EQ_(TX)\mathrm{EQ}_{\mathrm{TX}} 決定了去強調的水平。定義了兩個去強調比率。
Figure 46 shows an example transmit waveform with de-emphasis. After a logical bit transition, the amplitude of the differential output voltage signal V_("DIF_TX ")(t)\mathrm{V}_{\text {DIF_TX }}(\mathrm{t}) conforms to the differential AC output voltage amplitude V_(OD)\mathrm{V}_{\mathrm{OD}}. The next bit that retains the same logical state is reduced in amplitude. The differential AC output voltage amplitude with de-emphasis V_("OD_EQ ")\mathrm{V}_{\text {OD_EQ }} is defined as the reduced amplitude. EQTX is defined as the minus 20 log of the ratio of V_("OD_EQ ")V_{\text {OD_EQ }} and V_("OD ")V_{\text {OD }} as shown in the following equation: 圖 46 顯示了一個具有去強調的傳輸波形示例。在邏輯位元轉換後，差分輸出電壓信號 V_("DIF_TX ")(t)\mathrm{V}_{\text {DIF_TX }}(\mathrm{t}) 的幅度符合差分交流輸出電壓幅度 V_(OD)\mathrm{V}_{\mathrm{OD}} 。保持相同邏輯狀態的下一位的幅度減小。具有去強調的差分交流輸出電壓幅度 V_("OD_EQ ")\mathrm{V}_{\text {OD_EQ }} 被定義為減小的幅度。EQTX 被定義為 V_("OD_EQ ")V_{\text {OD_EQ }} 和 V_("OD ")V_{\text {OD }} 的比率的負 20 對數，如下方的方程所示：
EQ_(TX)=-20 log((V_(OD_(-)EQ))/(V_(OD)))E Q_{T X}=-20 \log \left(\frac{V_{O D_{-} E Q}}{V_{O D}}\right)
Figure 46 De-emphasis Example 圖 46 降低重視範例
Table 20 HS Transmitter DC Specifications 表 20 HS 發射器直流規格
Parameter 參數
Description 描述
Min
Nom
Max
Units 單位
Notes 筆記
EQTX1
De-emphasis Option 1 去強調選項 1
2.5
3.5
4.5
dB
1
EQTX2
De-emphasis Option 2 去強調選項 2
6
7
8
dB
1
Vсmix
HS transmit static commonmode voltage HS 傳輸靜態共模電壓
150
200
250
mV
2
VCMTX_HalfSwing
HS transmit static commonmode voltage in Half Swing Mode HS 在半擺動模式下傳輸靜態共模電壓
VoD mismatch when output is
Differential-1 or Differential-0| VoD mismatch when output is |
| :--- |
| Differential-1 or Differential-0 |
14
mV
3
VoHHS
HS output high voltage HS 輸出高電壓
360
mV
2
Zos
Single ended output impedance 單端輸出阻抗
40
50
62.5
Omega\Omega
DeltaZ_("OS ")\Delta Z_{\text {OS }}
單端輸出阻抗不匹配
Single ended output impedance
mismatch
Single ended output impedance
mismatch| Single ended output impedance |
| :--- |
| mismatch |
20
%\%
Parameter Description Min Nom Max Units Notes
|DeltaV_("OD ")| "VoD mismatch when output is
Differential-1 or Differential-0" 14 mV 3
VoHHS HS output high voltage 360 mV 2
Zos Single ended output impedance 40 50 62.5 Omega
DeltaZ_("OS ") "Single ended output impedance
mismatch" 20 % | Parameter | Description | Min | Nom | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| $\left\|\Delta V_{\text {OD }}\right\|$ | VoD mismatch when output is <br> Differential-1 or Differential-0 | | | 14 | mV | 3 |
| VoHHS | HS output high voltage | | | 360 | mV | 2 |
| Zos | Single ended output impedance | 40 | 50 | 62.5 | $\Omega$ | |
| $\Delta Z_{\text {OS }}$ | Single ended output impedance <br> mismatch | | | 20 | $\%$ | |
Note: 注意：
When the supported data rate is > 2.5>2.5 Gbps. Conformance requirements for the transmitter are defined through the eye diagram. The values for equalization in this table are informative. 當支持的數據速率為 > 2.5>2.5 Gbps 時，發射器的符合性要求通過眼圖定義。本表中的均衡值僅供參考。
Value when driving into load impedance anywhere in the ZID range. 在 ZID 範圍內進入負載阻抗時的值。
A transmitter should minimize /_\VOD\triangle V O D and /_\VCMTX(1,0)\triangle V C M T X(1,0) in order to minimize radiation and optimize signal integrity. 發射器應該最小化 /_\VOD\triangle V O D 和 /_\VCMTX(1,0)\triangle V C M T X(1,0) 以減少輻射並優化信號完整性。
Half Swing Mode is optional. It is an additional capability a transmitter can support for better system power optimization. 半擺模式是可選的。這是發射器可以支持的一項額外功能，以實現更好的系統功率優化。
Table 21 HS Transmitter AC Specifications 表 21 HS 發射器交流規格
Parameter Description Min Nom Max Units Notes
DeltaV_("CMTX ") (HF) Common-level variations above 450MHz 15 mVRMS
DeltaV_("cmix(LF) ") Common-level variation between 50-450MHz 25 mVV_("PEAK ")
t_(R) and t_(F) 20%-80% rise time and fall time 0.3 UI 1, 2
0.35 UI 1, 3
100 ps 4| Parameter | Description | Min | Nom | Max | Units | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| $\Delta \mathrm{V}_{\text {CMTX }}$ (HF) | Common-level variations above 450MHz | | | 15 | mVRMS | |
| $\Delta \mathrm{V}_{\text {cmix(LF) }}$ | Common-level variation between $50-450 \mathrm{MHz}$ | | | 25 | $\mathrm{mV} \mathrm{V}_{\text {PEAK }}$ | |
| $t_{R}$ and $t_{F}$ | 20%-80% rise time and fall time | | | 0.3 | UI | 1, 2 |
| | | | | 0.35 | UI | 1, 3 |
| | | 100 | | | ps | 4 |
Note: 注意：
Ul is equal to 1//(2^(***)fh)1 /\left(2^{\star} f h\right). See Section 8.3 for the definition of fhf h. Ul 等於 1//(2^(***)fh)1 /\left(2^{\star} f h\right) 。請參見第 8.3 節以獲取 fhf h 的定義。
Applicable when supporting maximum HS bit rates > 1Gbps>1 \mathrm{Gbps} ( UI <= 1ns\mathrm{UI} \leq 1 \mathrm{~ns} ) but <= 1.5Gbps\leq 1.5 \mathrm{Gbps} ( UI >= 0.667 nsU I \geq 0.667 n s ). 適用於支持最大 HS 比特率 > 1Gbps>1 \mathrm{Gbps} （ UI <= 1ns\mathrm{UI} \leq 1 \mathrm{~ns} ），但 <= 1.5Gbps\leq 1.5 \mathrm{Gbps} （ UI >= 0.667 nsU I \geq 0.667 n s ）。
Applicable when supporting maximum HS bit rates <= 1.5\leq 1.5 Gbps. However, to avoid excessive radiation, bit rates < 1<1 Gbps ( UI >= 1ns\mathrm{UI} \geq 1 \mathrm{~ns} ), should not use values below 150 ps. 適用於支持最大 HS 比特率 <= 1.5\leq 1.5 Gbps。然而，為了避免過度輻射，比特率 < 1<1 Gbps（ UI >= 1ns\mathrm{UI} \geq 1 \mathrm{~ns} ）不應使用低於 150 ps 的值。
9.1.2 Low-Power Transmitter 9.1.2 低功耗發射器
The Low-Power transmitter shall be a slew-rate controlled push-pull driver. It is used for driving the Lines in all Low-Power operating modes It is therefore important that the static power consumption of an LP transmitter be as low as possible. The slew-rate of signal transitions is bounded in order to keep EMI low. An example of an LP transmitter is shown in Figure 47. 低功耗發射器應為斜率控制的推挽驅動器。它用於驅動所有低功耗操作模式中的線路。因此，LP 發射器的靜態功耗應盡可能低。信號轉換的斜率受到限制，以保持電磁干擾（EMI）低。圖 47 顯示了一個 LP 發射器的例子。
Figure 47 Example LP Transmitter 圖 47 範例 LP 發射器 V_("OL ")\mathrm{V}_{\text {OL }} is the Thevenin output, low-level voltage in the LP transmit mode. This is the voltage at an unloaded pad pin in the low-level state. V_(OH)\mathrm{V}_{\mathrm{OH}} is the Thevenin output, high-level voltage in the high-level state, when the pad pin is not loaded. The LP transmitter shall not drive the pad pin potential statically beyond the maximum value of V_(OH)\mathrm{V}_{\mathrm{OH}}. The pull-up and pull-down output impedances of LP transmitters shall be as described in Figure 48 and Figure 49, respectively. The circuit for measuring V_(OL)\mathrm{V}_{\mathrm{OL}} and V_(OH)\mathrm{V}_{\mathrm{OH}} is shown in Figure 50. V_("OL ")\mathrm{V}_{\text {OL }} 是 LP 發射模式下的 Thevenin 輸出、低電壓。這是在低電平狀態下未加載的引腳的電壓。 V_(OH)\mathrm{V}_{\mathrm{OH}} 是高電平狀態下的 Thevenin 輸出、高電壓，當引腳未加載時。LP 發射器不應靜態驅動引腳電位超過 V_(OH)\mathrm{V}_{\mathrm{OH}} 的最大值。LP 發射器的上拉和下拉輸出阻抗應如圖 48 和圖 49 所示。測量 V_(OL)\mathrm{V}_{\mathrm{OL}} 和 V_(OH)\mathrm{V}_{\mathrm{OH}} 的電路如圖 50 所示。
Figure 48 V-I Characteristic for LP Transmitter Driving Logic High 圖 48 LP 發射器驅動邏輯高的 V-I 特性
The impedance Z_("OLP ")\mathrm{Z}_{\text {OLP }} is defined by: 阻抗 Z_("OLP ")\mathrm{Z}_{\text {OLP }} 定義為：
The times T_(RLP)\mathrm{T}_{\mathrm{RLP}} and T_(FLP)\mathrm{T}_{\mathrm{FLP}} are the 15%-85%15 \%-85 \% rise and fall times, respectively, of the output signal voltage, when the LP transmitter is driving a capacitive load C LOAd. ^(2)^{2} The 15%-85%15 \%-85 \% levels are relative to the fully settled V_(OH)\mathrm{V}_{\mathrm{OH}} and V_(OL)\mathrm{V}_{\mathrm{OL}} voltages. The slew rate deltaV//deltat_(SR)\delta \mathrm{V} / \delta \mathrm{t}_{\mathrm{SR}} is the derivative of the LP transmitter output signal voltage over time. The LP transmitter output signal transitions shall meet the maximum and minimum slew rate specifications as shown in Table 23. The intention of specifying a maximum slew rate value is to limit EMI. 當 LP 發射器驅動電容負載 C LOAd 時， T_(RLP)\mathrm{T}_{\mathrm{RLP}} 和 T_(FLP)\mathrm{T}_{\mathrm{FLP}} 是輸出信號電壓的 15%-85%15 \%-85 \% 上升和下降時間。 ^(2)^{2} 這些 15%-85%15 \%-85 \% 水平相對於完全穩定的 V_(OH)\mathrm{V}_{\mathrm{OH}} 和 V_(OL)\mathrm{V}_{\mathrm{OL}} 電壓。斜率 deltaV//deltat_(SR)\delta \mathrm{V} / \delta \mathrm{t}_{\mathrm{SR}} 是 LP 發射器輸出信號電壓隨時間的導數。LP 發射器輸出信號的過渡應符合表 23 中顯示的最大和最小斜率規範。指定最大斜率值的意圖是限制 EMI。
Table 22 LP Transmitter DC Specifications 表 22 LP 發射器直流規格
Parameter 參數
Description 描述
Min
Nom
Max
Units 單位
Notes 筆記
VOH_(OH)\mathrm{VOH}_{\mathrm{OH}}
Thevenin output high level 特文寧輸出高電平
1.1
1.2
1.3
V
1
0.95
1.3
V
2
VOL
Thevenin output low level 泰文輸出低電平
-50
50
mV
ZoLP
LP 發射器的輸出阻抗
Output impedance of LP
transmitter
Output impedance of LP
transmitter| Output impedance of LP |
| :--- |
| transmitter |
110
Omega\Omega
3,4
Parameter Description Min Nom Max Units Notes
VOH_(OH) Thevenin output high level 1.1 1.2 1.3 V 1
0.95 1.3 V 2
VOL Thevenin output low level -50 50 mV
ZoLP "Output impedance of LP
transmitter" 110 Omega 3,4| Parameter | Description | Min | Nom | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| $\mathrm{VOH}_{\mathrm{OH}}$ | Thevenin output high level | 1.1 | 1.2 | 1.3 | V | 1 |
| | | 0.95 | | 1.3 | V | 2 |
| VOL | Thevenin output low level | -50 | | 50 | mV | |
| ZoLP | Output impedance of LP <br> transmitter | 110 | | | $\Omega$ | 3,4 |
Note: 注意：
Applicable when the supported data rate <= 1.5\leq 1.5 Gbps. 適用於支援的數據速率 <= 1.5\leq 1.5 Gbps。
Applicable when the supported data rate > 1.5>1.5 Gbps. 適用於支援的數據速率 > 1.5>1.5 Gbps。
See Figure 48 and Figure 49. 請參見圖 48 和圖 49。
Though no maximum value for ZoLP is specified, the LP transmitter output impedance shall ensure the T_(RLP)//T_(FLP)T_{R L P} / T_{F L P} specification is met. 雖然未指定 ZoLP 的最大值，但 LP 發射器的輸出阻抗應確保滿足 T_(RLP)//T_(FLP)T_{R L P} / T_{F L P} 規範。
Table 23 LP Transmitter AC Specifications 表 23 LP 發射器交流規格
Parameter 參數
Description 描述
Min
Nom
Max
Units 單位
Notes 筆記
TrLP/TfLP
15%-85% rise time and fall time 15%-85% 上升時間和下降時間
25
ns
1
Treot
30%-85% rise time and fall time 30%-85% 上升時間和下降時間
35
ns
5,6
TLP-PuLSE-TX
LP 獨佔或時鐘的脈衝寬度
Pulse width of the LP
exclusive-OR clock
Pulse width of the LP
exclusive-OR clock| Pulse width of the LP |
| :--- |
| exclusive-OR clock |
停止狀態後的第一個 LP 獨佔或運算時鐘脈衝或停止狀態之前的最後一個脈衝
First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state
First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state| First LP |
| :--- |
| exclusive-OR |
| clock pulse after |
| Stop state or last pulse before Stop state |
40
ns
4
All other pulses 所有其他脈衝
20
ns
4
TLP-PER-TX
Period of the LP exclusive-OR clock LP 獨佔或時鐘的週期
90
ns
deltaV// bar(" tsR ")\delta \mathrm{V} / \overline{\text { tsR }}
Parameter Description Min Nom Max Units Notes
TrLP/TfLP 15%-85% rise time and fall time 25 ns 1
Treot 30%-85% rise time and fall time 35 ns 5,6
TLP-PuLSE-TX "Pulse width of the LP
exclusive-OR clock" "First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state" 40 ns 4
All other pulses 20 ns 4
TLP-PER-TX Period of the LP exclusive-OR clock 90 ns
deltaV// bar(" tsR ") Slew rate @ Cload = 0pF 500 mV/ns 1, 3, 7, 8
Slew rate @ Cload = 5pF 300 mV//ns 1, 3, 7, 8
Slew rate @ Cload = 20pF 250 mV//ns 1, 3, 7, 8
Slew rate @ ClOAd = 70pF 150 mV//ns 1, 3, 7, 8
Slew rate @ Cload =0 to 70pF (Falling Edge Only) 30 mV//ns 1, 2, 3, 12
25 mV/ns 1, 3, 13, 16| Parameter | Description | | Min | Nom | Max | Units | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| TrLP/TfLP | 15%-85% rise time and fall time | | | | 25 | ns | 1 |
| Treot | 30%-85% rise time and fall time | | | | 35 | ns | 5,6 |
| TLP-PuLSE-TX | Pulse width of the LP <br> exclusive-OR clock | First LP <br> exclusive-OR <br> clock pulse after <br> Stop state or last pulse before Stop state | 40 | | | ns | 4 |
| | | All other pulses | 20 | | | ns | 4 |
| TLP-PER-TX | Period of the LP exclusive-OR clock | | 90 | | | ns | |
| $\delta \mathrm{V} / \overline{\text { tsR }}$ | Slew rate @ Cload = 0pF | | | | 500 | mV/ns | 1, 3, 7, 8 |
| | Slew rate @ Cload = 5pF | | | | 300 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload = 20pF | | | | 250 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ ClOAd = 70pF | | | | 150 | $\mathrm{mV} / \mathrm{ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload $=0$ to 70pF (Falling Edge Only) | | 30 | | | $\mathrm{mV/ns}$ | 1, 2, 3, 12 |
| | | | 25 | | | mV/ns | 1, 3, 13, 16 |
Note: 注意：
ClOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TXT X and RX are assumed to always be <10pF. The distributed line capacitance can be up to 50pF for a transmission line with 2ns delay. ClOAD 包括低頻等效傳輸線電容。假設 TXT X 和 RX 的電容始終小於 10pF。對於延遲為 2ns 的傳輸線，分佈線電容可達 50pF。
When the output voltage is between 400 mV and 930 mV . 當輸出電壓在 400 毫伏到 930 毫伏之間。
Measured as average across any 50 mV segment of the output signal transition. 以輸出信號過渡的任何 50 mV 段的平均值進行測量。
This parameter value can be lower than T_(LPX)T_{L P X} due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Section 9.2.2. 此參數值可能低於 T_(LPX)T_{L P X} ，這是由於上升與下降信號斜率和跳脫水平的差異，以及 Dp 和 Dn LP 發射器之間的不匹配。在 HS EoT（從 HS 水平過渡到 LP-11）期間觀察到的任何 LP 獨佔或脈衝都是第 9.2.2 節中所描述的故障行為。
The rise-time of T_("REOT ")T_{\text {REOT }} starts from the HS common-level at the moment the differential amplitude drops below 70 mV , due to stopping the differential drive. T_("REOT ")T_{\text {REOT }} 的上升時間從差分幅度降至 70 mV 以下的瞬間開始，因為停止了差分驅動。
With an additional load capacitance Cсм _("betw ")_{\text {betw }} between 0 and 60 pF on the termination center tap at RXR X side of the Lane 在通道的 RXR X 側的終端中心抽頭上，增加一個介電容量 Cсм _("betw ")_{\text {betw }} ，介於 0 和 60 pF 之間
This value represents a corner point in a piece-wise linear curve. 這個值代表一個分段線性曲線中的拐點。
When the output voltage is in the range specified by VPIN(absmax). 當輸出電壓在 VPIN(absmax)指定的範圍內。
When the output voltage is between 400 mV and 700 mV . 當輸出電壓在 400 毫伏到 700 毫伏之間。
Where V_(O,INST)V_{O, I N S T} is the instantaneous output voltage, V_(DP)V_{D P} or V_(DN)V_{D N}, in millivolts. 其中 V_(O,INST)V_{O, I N S T} 是瞬時輸出電壓， V_(DP)V_{D P} 或 V_(DN)V_{D N} ，以毫伏為單位。
When the output voltage is between 700 mV and 930 mV . 當輸出電壓在 700 毫伏到 930 毫伏之間。
Applicable when the supported data rate <= 1.5Gbps\leq 1.5 \mathrm{Gbps}. 適用於支援的數據速率 <= 1.5Gbps\leq 1.5 \mathrm{Gbps} 時。
Applicable when the supported data rate > 1.5 Gbps. 適用於支援的數據速率 > 1.5 Gbps 時。
When the output voltage is between 550 mV and 790 mV 當輸出電壓在 550 毫伏到 790 毫伏之間
When the output voltage is between 400 mV and 550 mV 當輸出電壓在 400 毫伏到 550 毫伏之間
When the output voltage is between 400 mV and 790 mV 當輸出電壓在 400 毫伏到 790 毫伏之間
There are minimum requirements on the duration of each LP state. To determine the duration of the LP state, the Dp and Dn signal lines are each compared to a common trip-level. The result of these comparisons is then exclusive-ORed to produce a single pulse train. The output of this “exclusive-OR clock” can then be used to find the minimum pulse width output of an LP transmitter. 每個 LP 狀態的持續時間都有最低要求。為了確定 LP 狀態的持續時間，Dp 和 Dn 信號線各自與一個共同的觸發水平進行比較。這些比較的結果然後進行異或運算，以產生一個單一的脈衝序列。這個“異或時鐘”的輸出可以用來找出 LP 發射器的最小脈衝寬度輸出。
Using a common trip-level in the range [ V_(IL,Max)+V_("OL,Min, ")V_(IH,Min)+V_("Ol,Max ")\mathrm{V}_{\mathrm{IL}, \mathrm{Max}}+\mathrm{V}_{\text {OL,Min, }} \mathrm{V}_{\mathrm{IH}, \mathrm{Min}}+\mathrm{V}_{\text {Ol,Max }} ], the exclusive-OR clock shall not contain pulses shorter than T_("Lp-pulse-Tx. ")\mathrm{T}_{\text {Lp-pulse-Tx. }} 使用範圍為 [ V_(IL,Max)+V_("OL,Min, ")V_(IH,Min)+V_("Ol,Max ")\mathrm{V}_{\mathrm{IL}, \mathrm{Max}}+\mathrm{V}_{\text {OL,Min, }} \mathrm{V}_{\mathrm{IH}, \mathrm{Min}}+\mathrm{V}_{\text {Ol,Max }} ] 的常見行程級別，異或時鐘不得包含短於 T_("Lp-pulse-Tx. ")\mathrm{T}_{\text {Lp-pulse-Tx. }} 的脈衝
9.2 Receiver Characteristics 9.2 接收器特性
9.2.1 High-Speed Receiver 9.2.1 高速接收器
The HS receiver is a differential line receiver. It contains a switchable parallel input termination, Z_(ID)\mathrm{Z}_{\mathrm{ID}}, between the positive input pin Dp and the negative input pin Dn. A simplified diagram of an example implementation using a PMOS input stage is shown in Figure 51. HS 接收器是一種差分線接收器。它包含一個可切換的並行輸入終端， Z_(ID)\mathrm{Z}_{\mathrm{ID}} ，位於正輸入引腳 Dp 和負輸入引腳 Dn 之間。圖 51 顯示了使用 PMOS 輸入級的示例實現的簡化圖。
Figure 51 HS Receiver Implementation Example 圖 51 HS 接收器實現範例
The differential input high and low threshold voltages of the HS receiver are denoted by V_("IDTH ")\mathrm{V}_{\text {IDTH }} and V_("IDtL ")\mathrm{V}_{\text {IDtL }}, respectively. V_(ILhs)\mathrm{V}_{\mathrm{ILhs}} and V_(IHhs)\mathrm{V}_{\mathrm{IHhs}} are the single-ended, input low and input high voltages, respectively. V_(CMRX(DC))\mathrm{V}_{\mathrm{CMRX}(\mathrm{DC})} is the differential input common-mode voltage. The HS receiver shall be able to detect differential signals at its Dp and Dn input signal pins when both signal voltages, V_(DP)\mathrm{V}_{\mathrm{DP}} and V_(DN)\mathrm{V}_{\mathrm{DN}}, are within the common-mode voltage range and if the voltage difference of V_(DP)\mathrm{V}_{\mathrm{DP}} and V_(DN)\mathrm{V}_{\mathrm{DN}} exceeds either V_(IDTH)\mathrm{V}_{\mathrm{IDTH}} or V_("IDtl. ")V_{\text {IDtl. }} The High-Speed receiver shall receive High-Speed data correctly while rejecting common-mode interference DeltaV_(CMRX(HF))\Delta \mathrm{V}_{\mathrm{CMRX}(\mathrm{HF})} and DeltaV_(CMRX(LF))\Delta \mathrm{V}_{\mathrm{CMRX}(\mathrm{LF})}. HS 接收器的差分輸入高低閾值電壓分別用 V_("IDTH ")\mathrm{V}_{\text {IDTH }} 和 V_("IDtL ")\mathrm{V}_{\text {IDtL }} 表示。 V_(ILhs)\mathrm{V}_{\mathrm{ILhs}} 和 V_(IHhs)\mathrm{V}_{\mathrm{IHhs}} 分別是單端輸入低電壓和輸入高電壓。 V_(CMRX(DC))\mathrm{V}_{\mathrm{CMRX}(\mathrm{DC})} 是差分輸入共模電壓。當兩個信號電壓 V_(DP)\mathrm{V}_{\mathrm{DP}} 和 V_(DN)\mathrm{V}_{\mathrm{DN}} 在共模電壓範圍內，且 V_(DP)\mathrm{V}_{\mathrm{DP}} 和 V_(DN)\mathrm{V}_{\mathrm{DN}} 的電壓差超過 V_(IDTH)\mathrm{V}_{\mathrm{IDTH}} 或 V_("IDtl. ")V_{\text {IDtl. }} 時，HS 接收器應能夠在其 Dp 和 Dn 輸入信號引腳上檢測到差分信號。高速接收器應能正確接收高速數據，同時拒絕共模干擾 DeltaV_(CMRX(HF))\Delta \mathrm{V}_{\mathrm{CMRX}(\mathrm{HF})} 和 DeltaV_(CMRX(LF))\Delta \mathrm{V}_{\mathrm{CMRX}(\mathrm{LF})} 。
During operation of the HS receiver, termination impedance Z_(ID)\mathrm{Z}_{\mathrm{ID}} is required between the Dp and Dn pins of the HS receiver. Z_(ID)\mathrm{Z}_{\mathrm{ID}} shall be disabled when the module is not in the HS receive mode. When transitioning from Low-Power Mode to HS receive mode the termination impedance shall not be enabled until the single-ended input voltages on both Dp and Dn fall below V_("TERM-EN. ")\mathrm{V}_{\text {TERM-EN. }}. To meet this requirement, a receiver does not need to sense the Dp and Dn lines to determine when to enable the line termination, rather the LP to HS transition timing can allow the line voltages to fall to the appropriate level before the line termination is enabled. 在 HS 接收器運作期間，HS 接收器的 Dp 和 Dn 引腳之間需要終端阻抗 Z_(ID)\mathrm{Z}_{\mathrm{ID}} 。當模組不處於 HS 接收模式時， Z_(ID)\mathrm{Z}_{\mathrm{ID}} 應禁用。從低功耗模式轉換到 HS 接收模式時，終端阻抗在 Dp 和 Dn 的單端輸入電壓降到 V_("TERM-EN. ")\mathrm{V}_{\text {TERM-EN. }} 以下之前不得啟用。為了滿足這一要求，接收器不需要感測 Dp 和 Dn 線來確定何時啟用線終端，而是 LP 到 HS 的轉換時序可以允許線電壓降到適當的水平，然後再啟用線終端。
The RX common-mode return loss and the RX differential mode return loss are specified in Section 8 . C_(CM)\mathrm{C}_{\mathrm{CM}} is the common-mode AC termination, which ensures a proper termination of the receiver at higher frequencies. For higher data rates, C_(CM)\mathrm{C}_{\mathrm{CM}} is needed at the termination center tap in order to meet the commonmode reflection requirements. RX 共模回波損失和 RX 差模回波損失在第 8 節中規定。 C_(CM)\mathrm{C}_{\mathrm{CM}} 是共模交流終端，確保接收器在較高頻率下的正確終端。對於更高的數據速率， C_(CM)\mathrm{C}_{\mathrm{CM}} 在終端中心抽頭處是必需的，以滿足共模反射要求。
When a Transmitter is in Half Swing mode, the receiver may choose to turn off the termination in High Speed mode for lower data rate operation. This is an optional mode that can be supported in addition to the default mode. A receiver in unterminated mode shall not operate with TX full swing. 當發射器處於半擺動模式時，接收器可以選擇在高速模式下關閉終端以進行較低數據速率的操作。這是一種可選模式，可以在默認模式之外支持。處於未終端模式的接收器不得與 TX 全擺動一起操作。
Table 24 HS Receiver DC Specifications 表 24 HS 接收器直流規格
Parameter 參數
Description 描述
Min
Nom
Max
Units 單位
Notes 筆記
V_(CMRX(DC))V_{C M R X(D C)}
共模電壓 HS 接收模式
Common-mode voltage HS
receive mode
Common-mode voltage HS
receive mode| Common-mode voltage HS |
| :--- |
| receive mode |
Differential input impedance in
unterminated mode| Differential input impedance in |
| :--- |
| unterminated mode |
10 K
-
-
Omega\Omega
4
Parameter Description Min Nom Max Units Notes
V_(CMRX(DC)) "Common-mode voltage HS
receive mode" 70 330 mV 1,2
Z_(ID) Differential input impedance 80 100 125 Omega 3
Z_(ID" _Open ") "Differential input impedance in
unterminated mode" 10 K - - Omega 4| Parameter | Description | Min | Nom | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| $V_{C M R X(D C)}$ | Common-mode voltage HS <br> receive mode | 70 | | 330 | mV | 1,2 |
| $\mathrm{Z}_{\mathrm{ID}}$ | Differential input impedance | 80 | 100 | 125 | $\Omega$ | 3 |
| $\mathrm{Z}_{\mathrm{ID} \text { _Open }}$ | Differential input impedance in <br> unterminated mode | 10 K | - | - | $\Omega$ | 4 |
Note: 注意：
Excluding possible additional RF interference of 100 mV peak sine wave beyond 450 MHz . 排除 450 MHz 以上可能額外的 100 mV 峰值正弦波射頻干擾。
This table value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450 MHz 此表格值包括發射器和接收器之間的地面差異為 50 mV，靜態共模電平容差和 450 MHz 以下的變化
Z_(ID)Z_{I D} can be higher than 125 ohms in unterminated mode. Z_(ID)Z_{I D} 在未終止模式下可以高於 125 歐姆。
Unterminated Mode for HS-RX is optional. This mode can only be used when a transmitter is in Half Swing mode. ZID_OPEN is defined for a differential voltage with maximum amplitude of ∣\mid Vod_Halswing| and within the common voltage range of VCMTX_Halfswing. HS-RX 的未終止模式是可選的。此模式僅在發射器處於半擺動模式時使用。ZID_OPEN 定義為最大幅度為 ∣\mid Vod_Halswing| 的差分電壓，並在 VCMTX_Halfswing 的共模電壓範圍內。
DeltaV_(CMRX(HF))\Delta V_{C M R X(H F)} is the peak amplitude of a sine wave superimposed on the receiver inputs. DeltaV_(CMRX(HF))\Delta V_{C M R X(H F)} 是疊加在接收器輸入上的正弦波的峰值振幅。
For higher bit rates a 14pF capacitor will be needed to meet the common-mode return loss specification. 對於較高的比特率，需要一個 14pF 的電容器來滿足共模回損規範。
Voltage difference compared to the DC average common-mode potential. 與直流平均共模電位相比的電壓差。
For devices supporting data rates <= 1.5Gbps\leq 1.5 \mathrm{Gbps}. 對於支持數據速率 <= 1.5Gbps\leq 1.5 \mathrm{Gbps} 的設備。
For devices supporting data rates > 1.5 Gbps. 對於支持數據速率 > 1.5 Gbps 的設備。
Excluding possible additional RF interference of 100 mV peak sine wave beyond 450 MHz . 排除 450 MHz 以上可能額外的 100 mV 峰值正弦波射頻干擾。
9.2.2 Low-Power Receiver 9.2.2 低功耗接收器
The Low-Power receiver is an un-terminated, single-ended receiver circuit. The LP receiver is used to detect the Low-Power state on each pin. For high robustness, the LP receiver shall filter out noise pulses and RF interference. It is recommended the implementer optimize the LP receiver design for low power. 低功耗接收器是一種未終止的單端接收器電路。LP 接收器用於檢測每個引腳上的低功耗狀態。為了提高穩健性，LP 接收器應過濾噪聲脈衝和射頻干擾。建議實施者優化 LP 接收器設計以降低功耗。
The input low-level voltage, V_(IL)\mathrm{V}_{\mathrm{IL}}, is the voltage at which the receiver is required to detect a low state in the input signal. A lower input voltage, V V_(IL-ulps)\mathrm{V}_{\mathrm{IL}-\mathrm{ulps}}, may be used when the receiver is in the Ultra-Low Power State. V_(IL)\mathrm{V}_{\mathrm{IL}} is larger than the maximum single-ended Line voltage during HS transmission. Therefore, an LP receiver shall detect low during HS signaling. 輸入的低電壓 V_(IL)\mathrm{V}_{\mathrm{IL}} 是接收器需要檢測輸入信號低狀態的電壓。在超低功耗狀態下，可能使用較低的輸入電壓 V V_(IL-ulps)\mathrm{V}_{\mathrm{IL}-\mathrm{ulps}} 。 V_(IL)\mathrm{V}_{\mathrm{IL}} 大於 HS 傳輸期間的最大單端線電壓。因此，LP 接收器在 HS 信號傳輸期間應檢測低電平。
The input high-level voltage, V_(IH)\mathrm{V}_{\mathrm{IH}}, is the voltage at which the receiver is required to detect a high state in the input signal. In order to reduce noise sensitivity on the received signal, an LP receiver shall incorporate a hysteresis, The hysteresis voltage is defined as V_("HYSt ")\mathrm{V}_{\text {HYSt }}. 輸入的高電壓 V_(IH)\mathrm{V}_{\mathrm{IH}} 是接收器需要檢測輸入信號高狀態的電壓。為了降低接收到的信號的噪聲敏感度，LP 接收器應該包含滯後特性，滯後電壓定義為 V_("HYSt ")\mathrm{V}_{\text {HYSt }} 。
The LP receiver shall reject any input signal smaller than e_("SPIKE. ")\mathrm{e}_{\text {SPIKE. }} Signal pulses wider than T_(MIN-RX)\mathrm{T}_{\mathrm{MIN}-\mathrm{RX}} shall propagate through the LP receiver. LP 接收器應拒絕任何小於 e_("SPIKE. ")\mathrm{e}_{\text {SPIKE. }} 的輸入信號。寬於 T_(MIN-RX)\mathrm{T}_{\mathrm{MIN}-\mathrm{RX}} 的信號脈衝應通過 LP 接收器傳播。
Furthermore, the LP receivers shall be tolerant of super-positioned RF interference on top of the wanted Line signals. This implies an input signal filter. The LP receiver shall meet all specifications for interference with peak amplitude V_("INT ")\mathrm{V}_{\text {INT }} and frequency f_("INT ")\mathrm{f}_{\text {INT }}. The interference shall not cause glitches or incorrect operation during signal transitions. 此外，LP 接收器應能容忍在所需的線信號上方的重疊射頻干擾。這意味著需要一個輸入信號濾波器。LP 接收器應滿足所有對於峰值幅度 V_("INT ")\mathrm{V}_{\text {INT }} 和頻率 f_("INT ")\mathrm{f}_{\text {INT }} 的干擾規範。干擾不應在信號過渡期間引起故障或不正確的操作。
Time-voltage integration of a spike above V_(IL)V_{I L} when being in LP-0 state or below V_(IH)V_{I H} when being in LP-1L P-1 state. eSpike generation will ensure the spike is crossing both V_(IL,max)V_{I L, m a x} and V_(IH,min)V_{I H, m i n} levels. 在 LP-0 狀態下，當尖峰高於 V_(IL)V_{I L} 時的時間-電壓積分，或在 LP-1L P-1 狀態下低於 V_(IH)V_{I H} 時的時間-電壓積分。eSpike 生成將確保尖峰同時穿越 V_(IL,max)V_{I L, m a x} 和 V_(IH,min)V_{I H, m i n} 水平。
An impulse less than this will not change the receiver state. 小於這個的脈衝將不會改變接收器的狀態。
In addition to the required glitch rejection, implementers shall ensure rejection of known RFinterferers. 除了所需的故障拒絕外，實施者應確保拒絕已知的射頻干擾源。
An input pulse greater than this shall toggle the output. 超過此值的輸入脈衝將切換輸出。
9.3 Line Contention Detection 9.3 線路競爭檢測
The Low-Power receiver and a separate Contention Detector (LP-CD) shall be used in a bi-directional Data Lane to monitor the line voltage on each Low-Power signal. This is required to detect line contention as described in Section 7.1. The Low-Power receiver shall be used to detect an LP high fault when the LP transmitter is driving high and the pin voltage is less than V_(IL)\mathrm{V}_{\mathrm{IL}}. Refer to Table 26. The LP-CD shall be used to detect an LP low fault when the LP transmitter is driving low and the pin voltage is greater than V_(IHCD)\mathrm{V}_{\mathrm{IHCD}}. Refer to Table 28. An LP low fault shall not be detected when the pin voltage is less than V_("ILCD ")\mathrm{V}_{\text {ILCD }}. 低功耗接收器和單獨的競爭檢測器（LP-CD）應用於雙向數據通道，以監控每個低功耗信號的線電壓。這是為了檢測線路競爭，如第 7.1 節所述。當 LP 發射器驅動高電平且引腳電壓小於 V_(IL)\mathrm{V}_{\mathrm{IL}} 時，低功耗接收器應用於檢測 LP 高故障。請參閱表 26。當 LP 發射器驅動低電平且引腳電壓大於 V_(IHCD)\mathrm{V}_{\mathrm{IHCD}} 時，LP-CD 應用於檢測 LP 低故障。請參閱表 28。當引腳電壓小於 V_("ILCD ")\mathrm{V}_{\text {ILCD }} 時，將不會檢測到 LP 低故障。
The general operation of a contention detector shall be similar to that of an LP receiver with lower threshold voltages. Although the DC specifications differ, the AC specifications of the LP-CD are defined to match those of the LP receiver and the LP-CD shall meet the specifications listed in Table 27 except for T_("MIN-RX. ")\mathrm{T}_{\text {MIN-RX. }} The LP-CD shall sufficiently filter the input signal to avoid false triggering on short events. 競爭檢測器的一般操作應類似於具有較低閾值電壓的 LP 接收器。雖然直流規格不同，但 LP-CD 的交流規格被定義為與 LP 接收器相匹配，並且 LP-CD 應滿足表 27 中列出的規格，除了 T_("MIN-RX. ")\mathrm{T}_{\text {MIN-RX. }} 。LP-CD 應充分過濾輸入信號，以避免在短事件上產生誤觸發。
The LP-CD threshold voltages ( V_("ILCD "),V_("IHCD ")\mathrm{V}_{\text {ILCD }}, \mathrm{V}_{\text {IHCD }} ) are shown along with the normal signaling voltages in Figure 53. LP-CD 閾值電壓 ( V_("ILCD "),V_("IHCD ")\mathrm{V}_{\text {ILCD }}, \mathrm{V}_{\text {IHCD }} ) 與正常信號電壓一起顯示在圖 53 中。
Figure 53 Signaling and Contention Voltage Levels 圖 53 信號和競爭電壓水平
Table 28 Contention Detector (LP-CD) DC Specifications 表 28 競爭檢測器 (LP-CD) 直流規格
No structure within the PHY may be damaged when a DC signal that is within the signal voltage range V_("PIN ")\mathrm{V}_{\text {PIN }} is applied to a pad pin for an indefinite period of time. V_("PIN(absmax) ")\mathrm{V}_{\text {PIN(absmax) }} is the maximum transient output voltage at the transmitter pin. The voltage on the transmitter’s output pin shall not exceed V_("PIN,MAX ")\mathrm{V}_{\text {PIN,MAX }} for a period greater than T_(VPIN(" absmax) ")\mathrm{T}_{\mathrm{VPIN}(\text { absmax) }}. When the PHY is in the Low-Power receive mode the pad pin leakage current shall be I_("LEAK ")\mathrm{I}_{\text {LEAK }} when the pad signal voltage is within the signal voltage range of V_(PIN)\mathrm{V}_{\mathrm{PIN}}. The specification of I_("LEAK ")\mathrm{I}_{\text {LEAK }} assures interoperability of any PHY in the LP mode by restricting the maximum load current of an LP transmitter. An example test circuit for leakage current measurement is shown in Figure 54. 當施加一個在信號電壓範圍內的直流信號 V_("PIN ")\mathrm{V}_{\text {PIN }} 到一個引腳針上時，PHY 內部的結構不得損壞，且施加時間不得定義。 V_("PIN(absmax) ")\mathrm{V}_{\text {PIN(absmax) }} 是發射器引腳的最大瞬態輸出電壓。發射器的輸出引腳電壓不得超過 V_("PIN,MAX ")\mathrm{V}_{\text {PIN,MAX }} ，持續時間不得超過 T_(VPIN(" absmax) ")\mathrm{T}_{\mathrm{VPIN}(\text { absmax) }} 。當 PHY 處於低功耗接收模式時，當引腳信號電壓在 V_(PIN)\mathrm{V}_{\mathrm{PIN}} 的信號電壓範圍內時，引腳針的漏電流應為 I_("LEAK ")\mathrm{I}_{\text {LEAK }} 。 I_("LEAK ")\mathrm{I}_{\text {LEAK }} 的規範通過限制 LP 發射器的最大負載電流來保證任何 PHY 在 LP 模式下的互操作性。圖 54 顯示了一個漏電流測量的示例測試電路。
The ground supply voltages shifts between a Master and a Slave shall be less than V_(GNDSH)\mathrm{V}_{\mathrm{GNDSH}}. 主設備和從設備之間的地面供電電壓變化應小於 V_(GNDSH)\mathrm{V}_{\mathrm{GNDSH}} 。
Maximum transient time above V_(PIN(max))\mathrm{V}_{\mathrm{PIN}(\max )} or below V_(PIN(min))\mathrm{V}_{\mathrm{PIN}(\min )} 最大瞬時時間高於 V_(PIN(max))\mathrm{V}_{\mathrm{PIN}(\max )} 或低於 V_(PIN(min))\mathrm{V}_{\mathrm{PIN}(\min )}
20
ns
2
Parameter Description Min Nom Max Units Notes
VPin Pin signal voltage range -50 1350 mV
ILEAK Pin leakage current -100 100 muA 1
VGNDSH Ground shift -50 50 mV
-5 5 mV 4
VPIn(absmax) Transient pin voltage level -0.15 1.45 V 3
TVPIN(absmax) Maximum transient time above V_(PIN(max)) or below V_(PIN(min)) 20 ns 2| Parameter | Description | Min | Nom | Max | Units | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| VPin | Pin signal voltage range | -50 | | 1350 | mV | |
| ILEAK | Pin leakage current | -100 | | 100 | $\mu \mathrm{A}$ | 1 |
| VGNDSH | Ground shift | -50 | | 50 | mV | |
| | | -5 | | 5 | mV | 4 |
| VPIn(absmax) | Transient pin voltage level | $-0.15$ | | 1.45 | V | 3 |
| TVPIN(absmax) | Maximum transient time above $\mathrm{V}_{\mathrm{PIN}(\max )}$ or below $\mathrm{V}_{\mathrm{PIN}(\min )}$ | | | 20 | ns | 2 |
Note: 注意：
When the pad voltage is in the signal voltage range from V_(GNDSH,MIN)V_{G N D S H, M I N} to V_(OH)+V_(GNDSH,MAx)V_{O H}+V_{G N D S H, M A x} and the Lane Module is in LP receive mode. 當墊電壓在信號電壓範圍從 V_(GNDSH,MIN)V_{G N D S H, M I N} 到 V_(OH)+V_(GNDSH,MAx)V_{O H}+V_{G N D S H, M A x} 且通道模組處於 LP 接收模式時。
The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20ns window after any LP-0 to LP-1 transition or vice versa. For all other situations it must stay within the VPIN range. 在任何 LP-0 到 LP-1 的轉換或反之之後，超過 VPIN 的電壓過沖和欠沖僅在單個 20ns 的窗口內被允許。在所有其他情況下，它必須保持在 VPIN 範圍內。
This value includes ground shift. 此值包括地面位移。
Ground shift when operating in Half Swing mode. 在半擺動模式下操作時地面會移動。
10 High-Speed Data-Clock Timing 10 高速數據時鐘定時
This section specifies the required timings on the High-Speed signaling interface independent of the electrical characteristics of the signal. The PHY is a source synchronous interface in the Forward direction. In either the Forward or Reverse signaling modes there shall be only one clock source. In the Reverse direction, Clock is sent in the Forward direction and one of four possible edges is used to launch the data. 本節指定了高速信號接口所需的時序，與信號的電氣特性無關。PHY 是一個在前向方向上的源同步接口。在前向或反向信號模式中，僅應有一個時鐘源。在反向方向上，時鐘在前向方向上發送，並使用四個可能邊緣中的一個來啟動數據。
Data transmission may occur at any rate greater than the minimum specified data bit rate. 數據傳輸可以以任何高於指定的最小數據比特率的速率進行。
Figure 55 shows an example PHY configuration including the compliance measurement planes for the specified timings. Note that the effect of signal degradation inside each package due to parasitic effects is included in the timing budget for the transmitter and receiver and is not included in the interconnect degradation budget. See Section 8 for details. 圖 55 顯示了一個 PHY 配置的範例，包括指定時序的合規測量平面。請注意，由於寄生效應導致每個封裝內的信號衰減的影響已包含在發射器和接收器的時序預算中，而不包括在互連衰減預算中。詳情請參見第 8 節。
Figure 55 Conceptual D-PHY Data and Clock Timing Compliance Measurement Planes 圖 55 概念性 D-PHY 數據和時鐘時序合規性測量平面
10.1 High-Speed Clock Timing 10.1 高速時鐘定時
The Master side of the Link shall send a differential clock signal to the Slave side to be used for data sampling. This signal shall be a DDR (half-rate) clock and shall have one transition per data bit time. All timing relationships required for correct data sampling are defined relative to the clock transitions. Therefore, implementations may use frequency spreading modulation on the clock to reduce EMI. 鏈路的主端應向從端發送差分時鐘信號以用於數據取樣。該信號應為 DDR（半速）時鐘，並且每個數據位時間應有一次轉換。所有正確數據取樣所需的時序關係均相對於時鐘轉換定義。因此，實現可以在時鐘上使用頻率擴展調製以減少電磁干擾。
The DDR clock signal shall maintain a quadrature phase relationship to the data signal. Data shall be sampled on both the rising and falling edges of the Clock signal. The term “rising edge” means "rising edge of the differential signal, i.e. CLKp - CLKn, and similarly for “falling edge”. Therefore, the period of the Clock signal shall be the sum of two successive instantaneous data bit times. This relationship is shown in Figure 56. DDR 時鐘信號應與數據信號保持四分之一相位關係。數據應在時鐘信號的上升沿和下降沿進行取樣。“上升沿”一詞指的是差分信號的上升沿，即 CLKp - CLKn，對於“下降沿”也是如此。因此，時鐘信號的週期應為兩個連續瞬時數據位時間的總和。此關係如圖 56 所示。
Note that the UI indicated in Figure 56 is the instantaneous UI. Implementers shall specify a maximum data rate and corresponding maximum clock frequency, fh _(MAX)_{\mathrm{MAX}}, for a given implementation. For a description of fh_("MAX ")\mathrm{fh}_{\text {MAX }}, see Section 8.3. 請注意，圖 56 中所示的用戶介面是瞬時用戶介面。實施者應指定給定實施的最大數據速率和相應的最大時鐘頻率，fh _(MAX)_{\mathrm{MAX}} 。有關 fh_("MAX ")\mathrm{fh}_{\text {MAX }} 的描述，請參見第 8.3 節。
Figure 56 DDR Clock Definition 圖 56 DDR 時鐘定義
As can be seen in Figure 55, the same clock source is used to generate the DDR Clock and launch the serial data. Since the Clock and Data signals propagate together over a channel of specified skew, the Clock may be used directly to sample the Data lines in the receiver. Such a system can accommodate instantaneous variations in UI for an ongoing burst defined by Delta UI\Delta U I. 如圖 55 所示，使用相同的時鐘源來生成 DDR 時鐘並啟動串行數據。由於時鐘和數據信號在指定的偏移通道中一起傳播，因此可以直接使用時鐘來對接收器中的數據線進行取樣。這樣的系統可以容納由 Delta UI\Delta U I 定義的持續突發中的瞬時 UI 變化。
The allowed instantaneous UI variation can cause large, instantaneous data rate variations. Therefore, devices shall accommodate these instantaneous variations with appropriate logic. It is recommended that devices accommodate these instantaneous variations using some method, such as with appropriate FIFO logic outside of the PHY, or provide an accurate clock source to the Lane Module to eliminate these instantaneous variations, or the data sink outside the PHY can be designed to be tolerant of UI variations The UI_("INST ")\mathrm{UI}_{\text {INST }} specifications for the Clock signal are summarized in Table 30. 允許的瞬時 UI 變化可能會導致大型的瞬時數據速率變化。因此，設備應該用適當的邏輯來適應這些瞬時變化。建議設備使用某種方法來適應這些瞬時變化，例如在 PHY 外部使用適當的 FIFO 邏輯，或為通道模塊提供準確的時鐘源以消除這些瞬時變化，或者 PHY 外部的數據接收器可以設計為能夠容忍 UI 變化。時鐘信號的 UI_("INST ")\mathrm{UI}_{\text {INST }} 規範在表 30 中總結。
Table 30 Clock Signal Specification 表 30 時鐘信號規範
Clock Parameter 時鐘參數
Symbol 符號
Min
Typ
Max
Units 單位
Notes 筆記
UI instantaneous UI 瞬時
Ulinst
12.5
ns
1,2
UI variation UI 變體
UUI
-10%-10 \%
10%10 \%
UI
Period Jitter 週期抖動
-5%-5 \%
5%5 \%
3
Clock Parameter Symbol Min Typ Max Units Notes
UI instantaneous Ulinst 12.5 ns 1,2
UI variation UUI -10% 10% UI
Period Jitter -5% 5% 3| Clock Parameter | Symbol | Min | Typ | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| UI instantaneous | Ulinst | | | 12.5 | ns | 1,2 |
| UI variation | UUI | $-10 \%$ | | $10 \%$ | UI | |
| Period Jitter | | $-5 \%$ | | $5 \%$ | | 3 |
Note: 注意：
This value corresponds to a minimum operating data rate of 80 Mbps. This instantaneous value does not take into account UI variations due to jitter or SSC modulation. 此值對應於最低操作數據速率為 80 Mbps。此瞬時值未考慮由於抖動或 SSC 調製引起的 UI 變化。
The minimum UI shall not be violated for any single bit period, i.e., any DDR half cycle within a data burst. The allowed instantaneous UI variation can cause instantaneous data rate variations. Therefore, devices should either accommodate these instantaneous variations with appropriate FIFO logic outside of the PHY or provide an accurate clock source to the Lane Module to eliminate these instantaneous variations. 在任何單一位元期間內，不得違反最小 UI，即在數據突發中的任何 DDR 半週期內。允許的瞬時 UI 變化可能會導致瞬時數據速率變化。因此，設備應該要麼使用適當的 FIFO 邏輯來適應這些瞬時變化，這些邏輯位於 PHY 之外，或者提供準確的時鐘源給通道模組，以消除這些瞬時變化。
When 0.444 ns <=0.444 n s \leq UI < 0.8 ns<0.8 n s, within a single burst ( 32 K Periods). This is rising to rising edge. 當 0.444 ns <=0.444 n s \leq UI < 0.8 ns<0.8 n s 時，在單一脈衝內（32 K 週期）。這是上升到上升邊緣。
10.2 Forward High-Speed Data Transmission Timing 10.2 前向高速數據傳輸時序
The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in Figure 57. Data is launched in a quadrature relationship to the clock such that the Clock signal edge may be used directly by the receiver to sample the received data. DDR 時鐘差分信號與數據差分信號的時序關係如圖 57 所示。數據以與時鐘的正交關係發送，使得接收器可以直接使用時鐘信號邊緣來取樣接收到的數據。
The transmitter shall ensure that a rising edge of the DDR clock is sent during the first payload bit of a transmission burst such that the first payload bit can be sampled by the receiver on the rising clock edge, the second bit can be sampled on the falling edge, and all following bits can be sampled on alternating rising and falling edges. 發射器應確保在傳輸突發的第一個有效載荷位元期間發送 DDR 時鐘的上升邊緣，以便接收器可以在上升時鐘邊緣對第一個有效載荷位元進行取樣，第二個位元可以在下降邊緣進行取樣，所有後續位元可以在交替的上升和下降邊緣進行取樣。
All timing values are measured with respect to the actual observed crossing of the Clock differential signal. The effects due to variations in this level are included in the clock to data timing budget. 所有時間值都是相對於實際觀察到的時鐘差分信號的交叉進行測量的。由於此水平變化所造成的影響已包含在時鐘到數據的時間預算中。
Receiver input offset and threshold effects shall be accounted as part of the receiver setup and hold parameters. 接收器輸入偏移和閾值效應應作為接收器設置和保持參數的一部分進行考慮。
Figure 57 Data to Clock Timing Definitions 圖 57 數據到時鐘定義
The Data-Clock timing parameters shown in Figure 58 are specified in Table 31. The skew specification, T_("SKEW[TX] ")\mathrm{T}_{\text {SKEW[TX] }}, is the allowed deviation of the data launch time to the ideal 1//2UI_("INST ")1 / 2 \mathrm{UI}_{\text {INST }} displaced quadrature clock edge. The setup and hold times, T_(SETUP[RX])\mathrm{T}_{\mathrm{SETUP[RX}]} and T_(HOLD[RX])\mathrm{T}_{\mathrm{HOLD}[\mathrm{RX}]}, respectively, describe the timing relationships between the data and clock signals. T_(SETUP[RX])\mathrm{T}_{\mathrm{SETUP[RX]}} is the minimum time that data shall be present before a rising or falling clock edge and T_(HOLD[RX])\mathrm{T}_{\mathrm{HOLD}[\mathrm{RX}]} is the minimum time that data shall remain in its current state after a rising or falling clock edge. The timing budget specifications for a receiver shall represent the minimum variations observable at the receiver for which the receiver will operate at the maximum specified acceptable bit error rate. 圖 58 中顯示的數據時鐘定時參數在表 31 中指定。偏差規範 T_("SKEW[TX] ")\mathrm{T}_{\text {SKEW[TX] }} 是數據發送時間與理想 1//2UI_("INST ")1 / 2 \mathrm{UI}_{\text {INST }} 偏移的正交時鐘邊緣之間的允許偏差。設置時間和保持時間，分別為 T_(SETUP[RX])\mathrm{T}_{\mathrm{SETUP[RX}]} 和 T_(HOLD[RX])\mathrm{T}_{\mathrm{HOLD}[\mathrm{RX}]} ，描述了數據和時鐘信號之間的定時關係。 T_(SETUP[RX])\mathrm{T}_{\mathrm{SETUP[RX]}} 是數據在上升或下降時鐘邊緣之前必須存在的最小時間， T_(HOLD[RX])\mathrm{T}_{\mathrm{HOLD}[\mathrm{RX}]} 是數據在上升或下降時鐘邊緣之後必須保持其當前狀態的最小時間。接收器的定時預算規範應表示接收器可觀察到的最小變化，接收器將在最大指定可接受位錯誤率下運行。
RX Data to Clock Setup Time Tolerance RX 數據到時鐘設置時間容差
TSETUP[Rx]
0.15
Ulhs
1
RX Data to Clock Hold Time Tolerance RX 數據到時鐘保持時間容差
THold[RX]
0.15
Ulhs
1
Channel Timing 頻道時序
Channel Data to Clock Skew 通道數據到時鐘偏移
TSKEw[TLIS]
-0.2
0.2
UlHS
Parameter Symbol Min Max Unit Note
HS-TX Timing
TX Data to Clock Skew TsKEW[TX] -0.15 0.15 Ulhs 1
HS-RX Timing
RX Data to Clock Setup Time Tolerance TSETUP[Rx] 0.15 Ulhs 1
RX Data to Clock Hold Time Tolerance THold[RX] 0.15 Ulhs 1
Channel Timing
Channel Data to Clock Skew TSKEw[TLIS] -0.2 0.2 UlHS | Parameter | Symbol | Min | Max | Unit | Note |
| :---: | :---: | :---: | :---: | :---: | :---: |
| HS-TX Timing | | | | | |
| TX Data to Clock Skew | TsKEW[TX] | -0.15 | 0.15 | Ulhs | 1 |
| HS-RX Timing | | | | | |
| RX Data to Clock Setup Time Tolerance | TSETUP[Rx] | 0.15 | | Ulhs | 1 |
| RX Data to Clock Hold Time Tolerance | THold[RX] | 0.15 | | Ulhs | 1 |
| Channel Timing | | | | | |
| Channel Data to Clock Skew | TSKEw[TLIS] | -0.2 | 0.2 | UlHS | |
Note: 注意：
All jitter specifications are specified with a 100 ohm differential termination 所有抖動規範均以 100 歐姆差分終端指定
10.2.1.2 Data Rate > 1>1 Gbps and <=\leq 1.5 Gbps 10.2.1.2 數據速率 > 1>1 Gbps 和 <=\leq 1.5 Gbps
The timing budget has been adjusted between the Transmitter, Receiver, and Channel to a support a maximum data rate of 1.5 Gbps . 傳輸器、接收器和通道之間的時間預算已調整，以支持最高數據速率為 1.5 Gbps。
RX Data to Clock Setup Time Tolerance RX 數據到時鐘設置時間容差
TsetuP[Rx]
0.2
Ulhs
1
RX Data to Clock Hold Time Tolerance RX 數據到時鐘保持時間容差
THOLd[RX]
0.2
Ulhs
1
Channel Timing 頻道時序
Channel Data to Clock Skew 通道數據到時鐘偏移
TSKEW[TLIS]
-0.1
0.1
Ulhs
Parameter Symbol Min Max Unit Note
HS-TX Timing
TX Data to Clock Skew TSKEW[TX] -0.2 0.2 Ulhs 1
HS-RX Timing
RX Data to Clock Setup Time Tolerance TsetuP[Rx] 0.2 Ulhs 1
RX Data to Clock Hold Time Tolerance THOLd[RX] 0.2 Ulhs 1
Channel Timing
Channel Data to Clock Skew TSKEW[TLIS] -0.1 0.1 Ulhs | Parameter | Symbol | Min | Max | Unit | Note |
| :---: | :---: | :---: | :---: | :---: | :---: |
| HS-TX Timing | | | | | |
| TX Data to Clock Skew | TSKEW[TX] | $-0.2$ | 0.2 | Ulhs | 1 |
| HS-RX Timing | | | | | |
| RX Data to Clock Setup Time Tolerance | TsetuP[Rx] | 0.2 | | Ulhs | 1 |
| RX Data to Clock Hold Time Tolerance | THOLd[RX] | 0.2 | | Ulhs | 1 |
| Channel Timing | | | | | |
| Channel Data to Clock Skew | TSKEW[TLIS] | -0.1 | 0.1 | Ulhs | |
Note: 注意：
All jitter specifications are specified with a 100 ohm differential termination 所有抖動規範均以 100 歐姆差分終端指定
10.2.1.3 Data Rate > 1.5 Gbps and <=\leq 4.5 Gbps 10.2.1.3 數據速率 > 1.5 Gbps 和 <=\leq 4.5 Gbps
For higher data rate operation, jitter specifications have been decomposed into Deterministic jitter and Random jitter based on a target BER of 10^(-12)10^{-12}. Meeting the jitter specifications is a recommendation, whereas meeting the Eye diagram specification is a requirement. 為了實現更高的數據傳輸速率，抖動規範已根據目標比特錯誤率（BER） 10^(-12)10^{-12} 分解為確定性抖動和隨機抖動。滿足抖動規範是建議，而滿足眼圖規範則是要求。
Spread Spectrum Clocking (sometimes referred to as “Spectrum Spread Clocking”) is a common technique where a low frequency modulation is added to the Transmitter’s clock to reduce the peak emissions. 擴頻時鐘（有時稱為“頻譜擴展時鐘”）是一種常見技術，通過在發射器的時鐘上添加低頻調製來減少峰值排放。
All DPHY 2.0 compliant Transmitters shall support SSC as per Table 34 for data rates operating above 2.5 Gbps. 所有符合 DPHY 2.0 標準的發射器應根據表 34 支持 SSC，以便在超過 2.5 Gbps 的數據速率下運行。
All DPHY 2.0 compliant Receivers shall support SSC per Table 34 for data rates operating above 2.5 Gbps. 所有符合 DPHY 2.0 標準的接收器應支持根據表 34 的 SSC，以便在超過 2.5 Gbps 的數據速率下運行。
All DPHY 2.0 compliant Transmitters shall provide the system integrator a mechanism to enable/disable SSC transmissions. 所有符合 DPHY 2.0 標準的發射器應提供系統集成商一種機制來啟用/禁用 SSC 傳輸。
SSC can be used in HS Data Transmission Mode. If used during HS Data Transmission Mode, SSC transmission shall be consistent during the entire mode. SSC 可以在 HS 數據傳輸模式中使用。如果在 HS 數據傳輸模式中使用，SSC 傳輸在整個模式中應保持一致。
SSC should not be used in Escape mode. SSC 不應在逃脫模式下使用。
SSC shall be implemented within the Transmitter such that a single modulated profile, single modulation rate and a single SSC deviation is common between the clock and all High-speed data lanes. SSC 應在發射器內實施，使得時鐘和所有高速數據通道之間共用單一調製配置、單一調製速率和單一 SSC 偏差。
All SSC parameters are defined for the HS Clock. 所有 SSC 參數均為 HS 時鐘定義。
Modulation using a triangular profile for the frequency spread should be the baseline. Implementers can provide further emissions reduction using more-complex modulation profiles. 使用三角形輪廓的調變來擴展頻率應該是基準。實施者可以通過使用更複雜的調變輪廓來進一步減少排放。
The required SSC deviation is also called “Down-Spread”. 所需的 SSC 偏差也稱為“下擴散”。
Any implementation with an SSC deviation significantly smaller than 5000 PPM may fail in EMI testing below 1 GHz clock rate (Data Rate < 2 Gbps ). 任何 SSC 偏差顯著小於 5000 PPM 的實現可能在低於 1 GHz 時鐘速率（數據速率<2 Gbps）的 EMI 測試中失敗。
df/dt limit shall be for clock and all data lanes. df/dt 限制應適用於時鐘和所有數據通道。
Measured over a 0.5 mus0.5 \mu \mathrm{~s} interval using an alternating 010101010… input pattern at highest data rate. The measurements shall be low pass filtered using a filter with 3 dB cutoff frequency that is 60 times the modulation rate. The filter stopband rejection shall be a second order low-pass of 40 dB per decade. Evaluation of the maximum df/dt is achieved by inspection of the low-pass filtered waveform. 在最高數據速率下，使用交替的 010101010…輸入模式在 0.5 mus0.5 \mu \mathrm{~s} 間隔內進行測量。測量結果應使用截止頻率為調變速率 60 倍的濾波器進行低通濾波。濾波器的阻帶衰減應為每十倍頻率 40 dB 的二階低通濾波器。通過檢查低通濾波後的波形來評估最大 df/dt。
Maximum change rate of 1250 PPM/ mu\mu s is limiting the absolute value of the df/dt. 最大變化率為 1250 PPM/ mu\mu s 限制了 df/dt 的絕對值。
The Eye Diagram Specification shown below is applicable to Transmitters operating at data rates greater than 1.5 Gbps and less than or equal to 4.5 Gbps , and is specified for differential data signals with regard to the differential zero of the forwarded clock. This Transmitter Eye Diagram Specification applies after passing through the reference channel described in TLIS and differential termination of 100 Ohms. A Prorated Eye Diagram is specified for a higher BER to reduce validation time. 下方所示的眼圖規範適用於數據速率大於 1.5 Gbps 且小於或等於 4.5 Gbps 的發射器，並針對轉發時鐘的差分零點規範差分數據信號。此發射器眼圖規範適用於通過 TLIS 中描述的參考通道和 100 歐姆的差分終端後。為了降低驗證時間，規範了較高 BER 的按比例眼圖。
The Receiver Eye Diagram Specification shown below defines the worst-case Eye that the Receiver shall tolerate while injected at the Rx pads. This Eye Diagram Specification applies to Receivers operating at data rates between 1.5 Gbps and 4.5 Gbps. 下面顯示的接收器眼圖規範定義了接收器在 Rx 焊盤注入時應容忍的最壞情況眼圖。此眼圖規範適用於數據速率在 1.5 Gbps 到 4.5 Gbps 之間運行的接收器。
10.3 Reverse High-Speed Data Transmission Timing 10.3 反向高速數據傳輸時序
This section only applies to Half-Duplex Lane Modules that include Reverse High-Speed Data Transmission functionality. 本節僅適用於包含反向高速數據傳輸功能的半雙工通道模塊。
A Lane enters the Reverse High-Speed Data Transmission mode by means of a Link Turnaround procedure as specified in Section 6.5. Reverse Data Transmission is not source-synchronous; the Clock signal is driven by the Master side while the Data Lane is driven by the Slave side. The Slave Side transmitter shall send one data bit every two periods of the received Clock signal. Therefore, for a given Clock frequency, the Reverse direction data rate is one-fourth the Forward direction data rate. The bit period in this case is defined to be 4**UI_(INST).UI_(INST)4 * \mathrm{UI}_{\mathrm{INST}} . \mathrm{UI}_{\mathrm{INST}} is the value specified for the full-rate forward transmission. 一條通道通過第 6.5 節中規定的鏈路回轉程序進入反向高速數據傳輸模式。反向數據傳輸不是源同步的；時鐘信號由主端驅動，而數據通道由從端驅動。從端發射器應每兩個接收到的時鐘信號週期發送一個數據位。因此，對於給定的時鐘頻率，反向數據速率是正向數據速率的四分之一。在這種情況下，比特週期定義為 4**UI_(INST).UI_(INST)4 * \mathrm{UI}_{\mathrm{INST}} . \mathrm{UI}_{\mathrm{INST}} ，這是為全速正向傳輸指定的值。
Note that the clock source frequency may change between transmission bursts. However, all Data Lanes shall be in a Low-Power state before changing the clock source frequency. 請注意，時鐘源頻率可能在傳輸突發之間改變。然而，在更改時鐘源頻率之前，所有數據通道應處於低功耗狀態。
The conceptual overview of Reverse HS Data Transmission is shown in Figure 62. 反向 HS 數據傳輸的概念概述如圖 62 所示。
Figure 62 Conceptual View of HS Data Transmission in Reverse Direction 圖 62 HS 數據傳輸反向的概念視圖
There are four possible phase relationships between clock and data signals in the Reverse direction. The Clock phase used to send data is at the discretion of the Slave side, but once chosen it shall remain fixed throughout that data transmission burst. Signal delays in the interconnect, together with internal signal delays in the Master and Slave Modules, cause a fixed, but unknown, phase relationship in the Master Module between received (Reverse) Data and its own (Forward) Clock. Therefore, the Reverse traffic arriving at the Master side may not be phase aligned with the Forward direction clock. 在反向傳輸中，時鐘和數據信號之間有四種可能的相位關係。用於發送數據的時鐘相位由從屬端自行決定，但一旦選定，則在該數據傳輸突發期間保持不變。互連中的信號延遲，加上主模塊和從模塊內部的信號延遲，導致主模塊中接收到的（反向）數據與其自身的（正向）時鐘之間存在固定但未知的相位關係。因此，抵達主端的反向流量可能與正向方向的時鐘不對齊。
Synchronization between Clock and Data signals is achieved with the Sync sequence sent by the Slave during the Start of Transmission (SoT). The Master shall include sufficient functionality to correctly sample the received data given the instantaneous UI variations of the Clock sent to the Slave. 時鐘和數據信號之間的同步是通過從設備在傳輸開始（SoT）期間發送的同步序列來實現的。主設備應具備足夠的功能，以正確取樣接收到的數據，考慮到發送給從設備的時鐘的瞬時 UI 變化。
Reverse transmission by the Slave side is one-fourth of the Forward direction speed, based on the Forward direction Clock as transmitted via the Clock Lane. This ratio makes it easy to find a suitable phase at the Master Side for Data recovery of Reverse direction traffic. 反向傳輸由從屬端進行，其速度為正向方向速度的四分之一，基於通過時鐘通道傳輸的正向方向時鐘。這一比例使得在主端找到適合的相位以進行反向方向流量的數據恢復變得容易。
The known transitions of the received Sync sequence shall be used to select an appropriate phase of the clock signal for data sampling. Thus, there is no need to specify the round trip delay between the source of the clock and the receiver of the data. 接收到的同步序列的已知轉換將用於選擇數據取樣的時鐘信號的適當相位。因此，無需指定時鐘源和數據接收器之間的往返延遲。
The timing of the Reverse transmission as seen at the Slave side is shown in Figure 63. 在從屬端看到的反向傳輸的時機如圖 63 所示。
Figure 63 Reverse High-Speed Data Transmission Timing at Slave Side 圖 63 從屬端的反向高速數據傳輸時序
10.4 Operating Modes: Data rate and Channel Support Guidance 10.4 操作模式：數據速率和通道支持指導
Table 37 shows the possible configurations of a transmitter, channel, and receiver that can be supported based on the DPHY 2.0 electrical specification. 表 37 顯示了根據 DPHY 2.0 電氣規範可以支持的發射器、通道和接收器的可能配置。
Mode 1 is the default configuration targeted to meet the maximum data rate. 模式 1 是預設配置，旨在達到最大數據速率。
Mode 2 is an optional configuration targeted at supporting higher-loss interconnect. 模式 2 是一種可選配置，旨在支持高損耗互連。
Modes 3 through 10 are optional configurations and are targeted at lowering system-level power consumption. A system design can use these modes based on the transmitter and receiver capabilities. 模式 3 至 10 是可選配置，旨在降低系統級功耗。系統設計可以根據發射器和接收器的能力使用這些模式。
This section is only a guide for system-level optimization. 本節僅為系統級優化的指南。
Table 37 Operating Modes and Guidance 表 37 操作模式和指導
All MIPI D-PHY based devices should be designed to meet the applicable regulatory requirements. 所有基於 MIPI D-PHY 的設備應設計以符合適用的法規要求。
12 Built-In HS Test Mode (Informative) 12 內建 HS 測試模式（資訊性）
Figure 64 Testing with Pattern Checkers and Generators 圖 64 使用模式檢查器和生成器進行測試
Figure 65 Alternative Testing with Loopback Mode 圖 65 迴路模式的替代測試
12.1 Introduction 12.1 介紹
The standardized built-in test mode simplifies testing of the PHY layer of an Rx and a Tx. It may also be used for production testing, verification, interoperability testing, and self-testing. It requires a minimum set of registers to contain error and bit counters (see Figure 64), or alternatively support loopback testing (see Figure 65). The test mode is a PHY layer mode. As a result, use of the test mode should not require any protocol layers. It focuses on HS testing, because the LP operation and LP to HS transition was not modified by D-PHY Specification revisions above v1.0, and therefore can be tested as they were tested 標準化的內建測試模式簡化了接收器和發射器的 PHY 層測試。它也可以用於生產測試、驗證、互操作性測試和自我測試。它需要一組最小的寄存器來包含錯誤和位計數器（見圖 64），或者支持迴路測試（見圖 65）。測試模式是一種 PHY 層模式。因此，使用測試模式不應該需要任何協議層。它專注於 HS 測試，因為 LP 操作和 LP 到 HS 的過渡在 D-PHY 規範版本 1.0 以上並未修改，因此可以按照原來的方式進行測試。
before. This new mode will simplify the HS testing, and allows using the same or even less complicated / expensive equipment for testing new features such as SSC, Jitter, and equalization. 之前。這種新模式將簡化 HS 測試，並允許使用相同或甚至更簡單/更便宜的設備來測試新功能，如 SSC、抖動和均衡。
The HS test mode allows testing the tolerance of: HS 測試模式允許測試的容忍度：
Jitter 抖動
SSC parameters SSC 參數
Equalization parameters 均衡參數
HS amplitude and offset HS 振幅和偏移量
Clock to Data timing 時鐘到數據時序
Intra-lane timing, if the device allows multi-lane testing 車道內計時，如果設備允許多車道測試
Cross talk, if the device allows multi-lane testing 交叉對話，如果設備允許多車道測試
It does not allow testing of: 它不允許測試：
LP mode timing and level LP 模式定時和水平
LP-HS timings LP-HS 時間設定
ULPS mode timings and levels ULPS 模式時間和級別
Protocol specific parameters 協議特定參數
12.2 Entering the HS Test Mode 12.2 進入 HS 測試模式
Since the protocol should not be involved in entering the HS test mode, a simple pattern or sequence of LP states is defined to enter the test mode. 由於協議不應參與進入 HS 測試模式，因此定義了一個簡單的模式或 LP 狀態序列來進入測試模式。
The LP Trigger Escape Entry Code sequence from Table 8 (0b01011101) should be used to enter the test mode. If the device allows configuration via an external interface, then the test mode may also be activated by a configuration sequence via the external interface. In this case the vendor should publish the sequence required to activate the test mode. 表 8 中的 LP 觸發逃脫進入代碼序列（0b01011101）應用於進入測試模式。如果設備允許通過外部介面進行配置，那麼測試模式也可以通過外部介面的配置序列來啟動。在這種情況下，供應商應該發布啟動測試模式所需的序列。
In HS test mode the Rx of the device should expect HS data. If comparators and (bit- and error-) counters to determine BER are built in, then these registers should be reset and the device should do the Clock-Data alignment as soon as it detects the alignment pattern a HS clock/2 pattern on all tested lanes. For a multilane device this feature can be used to determine which lane(s) is/are tested. The Tx side should do the same as the test generator. It should send the initializing sequence for the HS test mode followed by the alignment pattern. 在 HS 測試模式下，設備的 Rx 應該預期 HS 數據。如果內建了比較器和（位元和錯誤）計數器來確定 BER，那麼這些寄存器應該被重置，並且設備應該在檢測到對齊模式（HS 時鐘/2 模式）後，立即進行時鐘-數據對齊，這適用於所有測試通道。對於多通道設備，這個功能可以用來確定哪些通道正在被測試。Tx 端應該與測試產生器做相同的操作。它應該發送 HS 測試模式的初始化序列，然後是對齊模式。
12.3 HS Test Mode 12.3 HS 測試模式
After the alignment pattern the test generator should send a sync word on all tested data lanes (0b00011101) to allow the device to do the symbol synchronization. On the clock lane the clock pattern should be sent continuously. The test pattern is vendor specific and can be one or more of the following 在對齊模式之後，測試生成器應該在所有測試數據通道上發送同步字（0b00011101），以允許設備進行符號同步。在時鐘通道上，時鐘模式應該持續發送。測試模式是供應商特定的，可以是以下一個或多個。
The compliance pattern (see CTS for definition) 合規模式（見 CTS 以獲取定義）
An application specific pattern. 一個特定應用的模式。
The PRBS9 is the preferred pattern. If the device supports this then for interoperability can be ensured. The definition of the pattern checkers follows the description of chapter 12 of the C-PHY Specification [MIPIO2]. For a clarification of the implementation, the following pattern should be expected [15:0] with a 16 bit seed register initialized 0x00FF: PRBS9 是首選模式。如果設備支持這一點，則可以確保互操作性。模式檢查器的定義遵循 C-PHY 規範 [MIPIO2] 第 12 章的描述。為了澄清實現，應該預期以下模式 [15:0]，具有初始化為 0x00FF 的 16 位種子寄存器：
If a vendor specific pattern is used, then the device vendor should supply the specification of the test pattern. Comparable results will be obtained in case that this pattern is balanced and the transition density is close to the value for a PRBS9 or the compliance pattern. 如果使用特定於供應商的模式，則設備供應商應提供測試模式的規範。如果該模式是平衡的，且轉換密度接近 PRBS9 或合規模式的值，則將獲得可比較的結果。
In case of internal pattern checkers, it is possible for the test generator and the pattern checkers to lose synchronization. In this case the BER will never get back to 0 again, even if the data are recognized properly again. In this case there are two possibilities: 在內部模式檢查器的情況下，測試生成器和模式檢查器可能會失去同步。在這種情況下，BER 將永遠無法再次回到 0，即使數據再次被正確識別。在這種情況下有兩種可能性：
One can be that the pattern checkers do a re-initialization with the default seed and wait for the seed pattern in case of a PRBS as test pattern, or wait for the first word(s) in the test pattern. In this case, the first word(s) should be somehow unique. The detection of a lost synchronization may be done internally, if too many errors occur (threshold vendor specific). 可以讓模式檢查器使用預設種子進行重新初始化，並在測試模式為 PRBS 的情況下等待種子模式，或等待測試模式中的第一個字（詞）。在這種情況下，第一個字（詞）應該在某種程度上是唯一的。如果發生過多錯誤（閾值由供應商具體定義），則可以在內部進行丟失同步的檢測。
The second possibility to re-initialize a synchronization loss may be to interrupt the clock. In this case, the re-initialization can be triggered from external by stopping the clock. The device should not exit from HS Test Mode. The de-serialization may be restarted by a sync word followed by the test pattern. An interruption of the clock should reset the PRBS generators, and the device should wait again for the sync pattern. The interruption detection time should set equal to the T_(Clk"-Miss ")\mathrm{T}_{\mathrm{Clk} \text {-Miss }} time (see Table 14). 重新初始化同步丟失的第二種可能性是中斷時鐘。在這種情況下，可以通過停止時鐘從外部觸發重新初始化。設備不應退出 HS 測試模式。去序列化可以通過同步字後跟測試模式重新啟動。時鐘的中斷應重置 PRBS 生成器，設備應再次等待同步模式。中斷檢測時間應設置為 T_(Clk"-Miss ")\mathrm{T}_{\mathrm{Clk} \text {-Miss }} 時間（見表 14）。
In case of using loopback (see Figure 65) for test mode, the test pattern should be send back via one or more Tx lanes (defined by the vendor). The loopback data signal should be retimed with the received clock. By this filtering, any jitter on data will be removed, while the clock received by the Rx should be routed through without any retiming. 在測試模式下使用迴路回路（見圖 65）時，測試模式應通過一個或多個 Tx 通道（由供應商定義）發送回測試模式。迴路回路數據信號應與接收到的時鐘重新定時。通過這種過濾，數據上的任何抖動將被去除，而 Rx 接收到的時鐘應無需重新定時直接路由。
Note: For PHY interoperability (without testing equipment), it is required that at least one device have integrated pattern generators and checkers (see Figure 64), and that both devices support the same test pattern. In this case, implementing the pattern-generators-and-checker method is recommended as this gives more flexibility then the loopback mode. 注意：對於 PHY 互操作性（無需測試設備），要求至少有一個設備具備集成的模式生成器和檢查器（見圖 64），並且兩個設備必須支持相同的測試模式。在這種情況下，建議實施模式生成器和檢查器方法，因為這比回路模式提供了更多的靈活性。
The equalization setting should be kept constant since the last HS setting before activating the test mode. Tx testing can be done by using a test generator applying the necessary pattern for Tx testing (see CTS). Triggering the Tx HS test pattern generation requires activating the test mode via an external interface. If the test mode was triggered by a test generator via the Rx side of the device, then the Tx needs to send the same data as received by Rx (loopback) or the counter values (error checkers). 均衡設定應保持不變，自上次 HS 設定以來，直到啟動測試模式。Tx 測試可以通過使用測試產生器應用必要的模式來進行 Tx 測試（參見 CTS）。觸發 Tx HS 測試模式生成需要通過外部介面啟動測試模式。如果測試模式是通過設備的 Rx 端由測試產生器觸發的，那麼 Tx 需要發送與 Rx 接收到的相同數據（回路回傳）或計數器值（錯誤檢查器）。
In case of using pattern checkers and counter register, the vendor should specify how to access these registers. Access to these counters can be implemented either via an external interface such as I2C or SPI, or else the device should send the counter values via its one D-PHY Tx lane. The counters should have enough depth to allow at least 20 seconds of operation without overrun. In case of overflow the counters should start over with 0 . The bit/frame counter register can contain a bit counter or a frame counter, in which the vendor needs to specify the factor between counter value and number of received bits. The error counter always should contain the number of errors. To support Tx testing of devices that support the test mode via pattern checkers, the Tx lanes can send the bit/error counters as continuous data stream; or, if the values of the counters are not sent via the link, it can automatically send a test pattern specified by the device vendor. 在使用模式檢查器和計數器寄存器的情況下，供應商應該指定如何訪問這些寄存器。對這些計數器的訪問可以通過外部接口實現，例如 I2C 或 SPI，或者設備應該通過其一個 D-PHY Tx 通道發送計數器值。計數器應具有足夠的深度，以允許至少 20 秒的操作而不會溢出。在溢出的情況下，計數器應該從 0 開始重新計算。位/幀計數器寄存器可以包含位計數器或幀計數器，供應商需要指定計數器值與接收位數之間的因子。錯誤計數器應始終包含錯誤的數量。為了支持通過模式檢查器的測試模式的設備的 Tx 測試，Tx 通道可以將位/錯誤計數器作為連續數據流發送；或者，如果計數器的值未通過鏈路發送，則可以自動發送由設備供應商指定的測試模式。
12.4 Special Case: Multi-Lane Testing 12.4 特殊情況：多車道測試
If the device allows using PRBS as test pattern on more than one lane, each lane should use a different seed. Lane 0 should use 0 xFF , lane 1 should use 0 xFE , and so on, to have different data crossing the link on each lane. This allows cross talk to be tested. If an application-specific pattern is used, these patterns should also be constructed such that they are different from lane to lane. The exact definition of applicationspecific test patterns is left to the device vendor, and must be documented by the device vendor. 如果設備允許在多條通道上使用 PRBS 作為測試模式，每條通道應使用不同的種子。通道 0 應使用 0 xFF，通道 1 應使用 0 xFE，依此類推，以便在每條通道上有不同的數據穿越鏈路。這樣可以測試串擾。如果使用特定應用的模式，這些模式也應構建為在不同通道之間有所不同。特定應用測試模式的確切定義由設備供應商決定，並必須由設備供應商進行文檔記錄。
12.5 Exiting from HS Test Mode 12.5 退出 HS 測試模式
After entering the test mode, the device should remain in test mode until directed to leave test mode, for example by an LP11 state applied for at least 500 ms , or by the device being power cycled. 進入測試模式後，設備應保持在測試模式，直到被指示離開測試模式，例如通過施加至少 500 毫秒的 LP11 狀態，或通過設備重新啟動。
If it is possible to configure the test mode via an external interface, then the same interface can also be used to exit the test mode. In this case, the device vendor must document the exit sequence. 如果可以通過外部介面配置測試模式，那麼同一介面也可以用來退出測試模式。在這種情況下，設備供應商必須記錄退出序列。
Annex A Logical PHY-Protocol Interface Description (informative) 附錄 A 邏輯 PHY 協議介面描述（資訊性）
The PHY Protocol Interface (PPI) is used to make a connection between the PHY Lane Modules and the higher protocol layers of a communication stack. The interface described here is intended to be generic and application independent. PHY 協議介面 (PPI) 用於在 PHY 通道模組和通信堆疊的更高協議層之間建立連接。此處描述的介面旨在通用且與應用無關。
This annex is informative only. Conformance to the D-PHY specification does not depend on any portion of the PPI defined herein. Because of that, this annex avoids normative language and does not use words like “shall” and “should.” Instead, present tense language has been used to describe the PPI, utilizing words like “is” and “does.” The reader may find it helpful to consider this annex to be a description of an example implementation, rather than a specification. The signaling interface described in this annex, The PHY Protocol Interface (PPI) is optional. However, if a module includes the PPI Interface, it shall implement it as described in this annex. 本附錄僅供參考。遵循 D-PHY 規範不依賴於此處定義的 PPI 的任何部分。因此，本附錄避免使用規範性語言，並不使用“應該”和“必須”等詞語。相反，使用現在時語言來描述 PPI，使用“是”和“做”等詞語。讀者可能會發現，將本附錄視為示例實現的描述，而不是規範，會更有幫助。本附錄中描述的信號接口，即 PHY 協議接口（PPI）是可選的。然而，如果模塊包含 PPI 接口，則必須按照本附錄中所述實現它。
This PPI is optimized for controlling a D-PHY and transmitting and receiving parallel data. The interface described here is defined as an on-chip connection, and does not attempt to minimize signal count or define timing parameters or voltage levels for the PPI signals. 此 PPI 經過優化，用於控制 D-PHY 並傳輸和接收並行數據。此處描述的接口定義為片上連接，並未嘗試最小化信號數量或定義 PPI 信號的定時參數或電壓水平。
A. 1 Signal Description A. 1 信號描述
Table 38 defines the signals used in the PPI. For a PHY with multiple Data Lanes, a set of PPI signals is used for each Lane. Each signal has been assigned into one of six categories: High-Speed transmit signals, High-Speed receive signals, Escape mode transmit signals, Escape mode receive signals, control signals, and error signals. Bi-directional High-Speed Data Lanes with support for bi-directional Escape mode include nearly all of the signals listed in the table. Unidirectional Lanes or Clock Lanes include only a subset of the signals. The direction of each signal is listed as “I” or “O”. Signals with the direction “I” are PHY inputs, driven from the Protocol. Signals with the direction “O” are PHY outputs, driven to the Protocol. For this logical interface, most clocks are described as being generated outside the PHY, although any specific PHY may implement the clock circuit differently. 表 38 定義了 PPI 中使用的信號。對於具有多個數據通道的 PHY，每個通道使用一組 PPI 信號。每個信號被分配到六個類別之一：高速發送信號、高速接收信號、逃逸模式發送信號、逃逸模式接收信號、控制信號和錯誤信號。支持雙向逃逸模式的雙向高速數據通道幾乎包括表中列出的所有信號。單向通道或時鐘通道僅包括信號的子集。每個信號的方向標示為“I”或“O”。方向為“I”的信號是 PHY 輸入，來自協議驅動。方向為“O”的信號是 PHY 輸出，驅動到協議。對於這個邏輯接口，大多數時鐘被描述為在 PHY 外部生成，儘管任何特定的 PHY 可能以不同的方式實現時鐘電路。
The “Categories” column in Table 38 indicates for which Lane Module types each signal applies. The category names are described in Table 1 and are summarized here for convenience. Each category is described using a four-letter acronym, defined as <Side, HS-capabilities, Escape-Forward, EscapeReverse>. The first letter, Side, can be M (Master) or S (Slave). The second letter, High-Speed capabilities, can be F (Forward data), R (Reverse and Forward data), or C (Clock). The third and fourth letters indicate Escape mode capability in the Forward and Reverse directions, respectively. For Data Lanes, the third letter can be A (All) or E (Events - Triggers and ULPS only), while the fourth letter can be A (All, including LPDT), E (Events, triggers and ULPS only), Y (Any but not None: so A or E) or N (None). For a Data Lane, any of the four identification letters can be replaced by an X , to indicate that each of the available options is appropriate. For a Clock Lane, only the first letter can be X , while the other three letters are always CNN. 表 38 中的“類別”欄位指示每個信號適用於哪些通道模組類型。類別名稱在表 1 中描述，這裡為方便起見進行總結。每個類別使用四個字母的縮寫來描述，定義為。第一個字母，Side，可以是 M（主控）或 S（從屬）。第二個字母，高速能力，可以是 F（前向數據）、R（反向和前向數據）或 C（時鐘）。第三和第四個字母分別表示前向和反向方向的逃逸模式能力。對於數據通道，第三個字母可以是 A（全部）或 E（事件 - 觸發和 ULPS 僅限），而第四個字母可以是 A（全部，包括 LPDT）、E（事件、觸發和 ULPS 僅限）、Y（任何但不是 None：即 A 或 E）或 N（無）。對於數據通道，四個識別字母中的任何一個都可以用 X 替換，以表示每個可用選項都是合適的。對於時鐘通道，只有第一個字母可以是 X，而其他三個字母始終是 CNN。
The signal description includes options for the designer to choose a data path width to simplify the task of timing closure between the D-PHY and high-level protocol logic. 信號描述包括供設計師選擇數據通路寬度的選項，以簡化 D-PHY 與高級協議邏輯之間的時序收斂任務。
The protocol and D-PHY will select data path widths as described in Table 38 that are most appropriate for the operation. The bus width selection is based on logical binary input as explained in TxDataWidthHS[1:0] and RxDataWidthHS[1:0]. Bus width can be modified based on operational requirements after the completion of the current burst. It is not necessary for the PPI data path width of the transmit function in one IC to match the PPI data path width of the receive function in another IC. The D-PHY has the ability to transmit and receive any integer number of words greater than zero, regardless of the width of the PPI Tx and Rx data paths. A set of data-valid signals accompany each set of data transferred over the PPI to indicate which words contain valid data to transmit or which words contain data that was actually received from the channel. 協議和 D-PHY 將根據表 38 中描述的最適合操作的數據通道寬度進行選擇。總線寬度的選擇基於邏輯二進制輸入，如 TxDataWidthHS[1:0] 和 RxDataWidthHS[1:0] 中所解釋的。總線寬度可以根據操作要求在當前突發完成後進行修改。在一個 IC 中的發送功能的 PPI 數據通道寬度不必與另一個 IC 中的接收功能的 PPI 數據通道寬度相匹配。D-PHY 能夠傳輸和接收任何大於零的整數字數，無論 PPI Tx 和 Rx 數據通道的寬度如何。每組通過 PPI 傳輸的數據都伴隨著一組數據有效信號，以指示哪些字包含有效數據以進行傳輸，或哪些字包含實際從通道接收到的數據。
All timing diagrams in this section refer to a one-byte bus-width case. 本節中的所有時序圖均指一字節總線寬度的情況。
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal.
Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal.| Data Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
TxDDRCIkHS-Q
I
MCNN
Clock Lane 高速傳輸 DDR 時鐘。此信號用於生成通道互連的高速時鐘信號。TxDDRCIkHS-Q（正交）時鐘信號相對於 TxDDRCIkHS-I 時鐘信號相位偏移。
Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal.
Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal.| Clock Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//81 / 8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//161 / 16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//321 / 32 the high-speed data rate.
High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate.| High-Speed Transmit Word Clock. |
| :--- |
| This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: |
| - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. |
| - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. |
| - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.
High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Transmit Data bus Width Select. |
| :--- |
| Selects the bus width of TxDataHS: |
| - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. |
| - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] |
| - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] |
| - TxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] TxDataHS[7:0]、TxDataHS[15:0]、或 TxDataHS[31:0]
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit.
High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit.| High-Speed Transmit Data bus width. |
| :--- |
| High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: |
| - 8-bit width - TxDataHS[7:0] |
| - 16-bit width - TxDataHS[15:0] |
| - 32-bit width - TxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
Symbol Dir Categories Description
High-Speed Transmit Signals
TxDDRCIkHS-I 1 "MXXX
MCNN" "Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal."
TxDDRCIkHS-Q I MCNN "Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal."
TxWordCIkHS 0 "MXXX
SRXX" "High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate."
TxDataWidthHS[1:0] I " MXXX
SRXX " "High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] I "MXXX
SRXX" "High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| High-Speed Transmit Signals | | | |
| TxDDRCIkHS-I | 1 | MXXX <br> MCNN | Data Lane High-Speed Transmit DDR Clock. <br> This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
| TxDDRCIkHS-Q | I | MCNN | Clock Lane High-Speed Transmit DDR Clock. <br> This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
| TxWordCIkHS | 0 | MXXX <br> SRXX | High-Speed Transmit Word Clock. <br> This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: <br> - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. <br> - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. <br> - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
| TxDataWidthHS[1:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SRXX } \end{aligned}$ | High-Speed Transmit Data bus Width Select. <br> Selects the bus width of TxDataHS: <br> - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. <br> - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] <br> - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] <br> - TxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] | I | MXXX <br> SRXX | High-Speed Transmit Data bus width. <br> High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: <br> - 8-bit width - TxDataHS[7:0] <br> - 16-bit width - TxDataHS[15:0] <br> - 32-bit width - TxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted.
High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted.| High-Speed Transmit Word Data Valid. |
| :--- |
| When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: |
| - 8-bit width - TxWordValidHS[0] |
| - 16-bit width - TxWordValidHS[1:0] |
| - 32-bit width - TxWordValidHS[3:0] |
| The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: |
| - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted |
| - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted |
| - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted |
| - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
TxEqActiveHS
I
MXXX
This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled. 這是一個級別敏感的標誌，表示均衡的活動狀態。當這個標誌為高時，表示均衡已啟用。當這個標誌為低時，表示均衡已禁用。
TxEqLevelHS
I
MXXX
This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( 3.5dB+//-1dB3.5 \mathrm{~dB}+/-1 \mathrm{~dB} ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( 7dB+//-1dB7 \mathrm{~dB}+/-1 \mathrm{~dB} ) is active. 這是一個級別敏感的標誌，表示均衡級別。當這個標誌為低（即零）時，表示低級別的均衡（ 3.5dB+//-1dB3.5 \mathrm{~dB}+/-1 \mathrm{~dB} ）是活動的。當這個標誌為高（即一）時，表示高級別的均衡（ 7dB+//-1dB7 \mathrm{~dB}+/-1 \mathrm{~dB} ）是活動的。
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low.
High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low.| High-Speed Transmit Request and Data Valid. |
| :--- |
| A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. |
| For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. |
| For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. |
| TxRequestHS is only asserted while TxRequestEsc is low. |
TxReadyHS
O
MXXX
SRXX
MXXX
SRXX| MXXX |
| :--- |
| SRXX |
高速傳輸準備就緒。此高電平信號表示 TxDataHS 已被通道模組接受以進行串行傳輸。TxReadyHS 在 TxWordCIkHS 的上升沿有效。可選地，TxReadyHS 可在去偏校準期間使用，以指示 SoT 已結束且數據通道正在傳輸去偏突發（時鐘模式）。
High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern).
High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern).| High-Speed Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. |
| Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
Symbol Dir Categories Description
"TxWordValidHS[0],
or
TxWordValidHS[1:0],
or
TxWordValidHS[3:0]" I "MXXX
SRXX" "High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted."
TxEqActiveHS I MXXX This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled.
TxEqLevelHS I MXXX This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( 3.5dB+//-1dB ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( 7dB+//-1dB ) is active.
TxRequestHS I "MXXX
SRXX
MCNN" "High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low."
TxReadyHS O "MXXX
SRXX" "High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern)."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxWordValidHS[0], <br> or <br> TxWordValidHS[1:0], <br> or <br> TxWordValidHS[3:0] | I | MXXX <br> SRXX | High-Speed Transmit Word Data Valid. <br> When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: <br> - 8-bit width - TxWordValidHS[0] <br> - 16-bit width - TxWordValidHS[1:0] <br> - 32-bit width - TxWordValidHS[3:0] <br> The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: <br> - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted <br> - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted <br> - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted <br> - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
| TxEqActiveHS | I | MXXX | This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled. |
| TxEqLevelHS | I | MXXX | This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( $3.5 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( $7 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. |
| TxRequestHS | I | MXXX <br> SRXX <br> MCNN | High-Speed Transmit Request and Data Valid. <br> A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. <br> For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. <br> For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. <br> TxRequestHS is only asserted while TxRequestEsc is low. |
| TxReadyHS | O | MXXX <br> SRXX | High-Speed Transmit Ready. <br> This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. <br> Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence.
High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence.| High-Speed Transmit Skew Calibration. |
| :--- |
| This is an optional pin to initiate the periodic deskew burst at the transmitter. |
| A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. |
| A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//81 / 8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//161 / 16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//321 / 32 the high-speed received data rate.
High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate.| High-Speed Receive Word Clock. |
| :--- |
| This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: |
| - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. |
| - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. |
| - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.
High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Receive Data Width Select. |
| :--- |
| Selects the bus width of RxDataHS: |
| - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] |
| - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] |
| - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] |
| - RxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] RxDataHS[7:0]、RxDataHS[15:0] 或 RxDataHS[31:0]
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit.
High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit.| High-Speed Receive Data. |
| :--- |
| High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: |
| - 8-bit width - RxDataHS[7:0] |
| - 16-bit width - RxDataHS[15:0] |
| - 32-bit width - RxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
Symbol Dir Categories Description
TxSkewCalHS I MXXX "High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence."
High-Speed Receive Signals
RxWordCIkHS 0 "MRXX
SXXX" "High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate."
RxDataWidthHS[1:0] I "MRXX
SXXX" "High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] 0 "MRXX
SXXX" "High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxSkewCalHS | I | MXXX | High-Speed Transmit Skew Calibration. <br> This is an optional pin to initiate the periodic deskew burst at the transmitter. <br> A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. <br> A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
| High-Speed Receive Signals | | | |
| RxWordCIkHS | 0 | MRXX <br> SXXX | High-Speed Receive Word Clock. <br> This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: <br> - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. <br> - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. <br> - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
| RxDataWidthHS[1:0] | I | MRXX <br> SXXX | High-Speed Receive Data Width Select. <br> Selects the bus width of RxDataHS: <br> - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] <br> - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] <br> - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] <br> - RxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] | 0 | MRXX <br> SXXX | High-Speed Receive Data. <br> High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: <br> - 8-bit width - RxDataHS[7:0] <br> - 16-bit width - RxDataHS[15:0] <br> - 32-bit width - RxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
Symbol 符號
Dir
Categories 類別
Description 描述
RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] RxValidHS[0]，或 RxValidHS[1:0]，或 RxValidHS[3:0]
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel.
High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel.| High-Speed Receive Data Valid. |
| :--- |
| This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. |
| The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: |
| - 8-bit width - RxValidHS[0] |
| - 16-bit width - RxValidHS[1:0] |
| - 32-bit width - RxValidHS[3:0] |
| The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: |
| - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel |
| - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel |
| - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel |
| - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
RxActiveHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
高速接收啟用。此高信號表示車道模組正在積極接收來自車道互連的高速傳輸。
High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect.
High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect.| High-Speed Reception Active. |
| :--- |
| This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted.
Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted.| Receiver Synchronization Observed. |
| :--- |
| This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
RxCIkActiveHS
0
SCNN
接收器時鐘啟用。此非同步的高電平信號表示時鐘通道正在接收 DDR 時鐘信號。
Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal.
Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal.| Receiver Clock Active. |
| :--- |
| This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low.
Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low.| Receiver DDR Clock. |
| :--- |
| This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State.
High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State.| High-Speed Receive Skew Calibration. |
| :--- |
| This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
Symbol Dir Categories Description
RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] O "MRXX
SXXX" "High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel."
RxActiveHS O "MRXX
SXXX" "High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect."
RxSyncHS 0 "MRXX
SXXX" "Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted."
RxCIkActiveHS 0 SCNN "Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal."
RxDDRCIkHS 0 SCNN "Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low."
RxSkewCalHS 0 SXXX "High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] | O | MRXX <br> SXXX | High-Speed Receive Data Valid. <br> This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. <br> The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: <br> - 8-bit width - RxValidHS[0] <br> - 16-bit width - RxValidHS[1:0] <br> - 32-bit width - RxValidHS[3:0] <br> The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: <br> - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel <br> - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel <br> - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel <br> - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
| RxActiveHS | O | MRXX <br> SXXX | High-Speed Reception Active. <br> This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
| RxSyncHS | 0 | MRXX <br> SXXX | Receiver Synchronization Observed. <br> This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
| RxCIkActiveHS | 0 | SCNN | Receiver Clock Active. <br> This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
| RxDDRCIkHS | 0 | SCNN | Receiver DDR Clock. <br> This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
| RxSkewCalHS | 0 | SXXX | High-Speed Receive Skew Calibration. <br> This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode.
Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode.| Escape mode Transmit Clock. |
| :--- |
| This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
TxRequestEsc
I
{:[MXXX],[SXXY]:}\begin{aligned} & M X X X \\ & S X X Y \end{aligned}
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low.
Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low.| Escape mode Transmit Request. |
| :--- |
| This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted.
Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted.| Escape mode Transmit Low-Power Data. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. |
| TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State.
Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State.| Transmit ULP Exit Sequence. |
| :--- |
| This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. |
| The PHY later drives the Stop state (LP-11) when |
| TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. |
| This signal is ignored when the Lane is not in the ULP State. |
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted.
Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted.| Escape mode Transmit Ultra-Low Power State. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. |
| TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
Symbol Dir Categories Description
Escape Mode Transmit Signals
TxClkEsc I " MXXX
SXXY " "Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode."
TxRequestEsc I "MXXX
SXXY" "Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low."
TxLpdtEsc I "MXAX
SXXA" "Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted."
TxUlpsExit I "MXXX
SXXY
MCNN" "Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State."
TxUlpsEsc I "MXXX
SXXY" "Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Escape Mode Transmit Signals | | | |
| TxClkEsc | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Clock. <br> This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
| TxRequestEsc | I | $\begin{aligned} & M X X X \\ & S X X Y \end{aligned}$ | Escape mode Transmit Request. <br> This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
| TxLpdtEsc | I | MXAX <br> SXXA | Escape mode Transmit Low-Power Data. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. <br> TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
| TxUlpsExit | I | MXXX <br> SXXY <br> MCNN | Transmit ULP Exit Sequence. <br> This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. <br> The PHY later drives the Stop state (LP-11) when <br> TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. <br> This signal is ignored when the Lane is not in the ULP State. |
| TxUlpsEsc | I | MXXX <br> SXXY | Escape mode Transmit Ultra-Low Power State. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. <br> TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger.
Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Transmit Trigger 0-3. |
| :--- |
| One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. |
| Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. |
| TxTriggerEsc[0] corresponds to Reset-Trigger. |
| TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| TxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc.
Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc.| Escape mode Transmit Data. |
| :--- |
| This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge.
Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge.| Escape mode Transmit Data Valid. |
| :--- |
| This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc.
Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc.| Escape mode Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic.
Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic.| Escape mode Receive Clock. |
| :--- |
| This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect.
Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Low-Power Data Receive mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect.
Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Ultra-Low Power (Receive) mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
Symbol Dir Categories Description
TxTriggerEsc[3:0] I " MXXX
SXXY " "Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger."
TxDataEsc[7:0] I "MXAX
SXXA" "Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc."
TxValidEsc I "MXAX
SXXA" "Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge."
TxReadyEsc O "MXAX
SXXA" "Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc."
Escape Mode Receive Signals
RxCIkEsc O MXXY SXXX "Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic."
RxLpdtEsc O MXXA SXAX "Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect."
RxUlpsEsc O "MXXY
SXXX" "Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxTriggerEsc[3:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Trigger 0-3. <br> One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. <br> Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. <br> TxTriggerEsc[0] corresponds to Reset-Trigger. <br> TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> TxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| TxDataEsc[7:0] | I | MXAX <br> SXXA | Escape mode Transmit Data. <br> This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
| TxValidEsc | I | MXAX <br> SXXA | Escape mode Transmit Data Valid. <br> This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
| TxReadyEsc | O | MXAX <br> SXXA | Escape mode Transmit Ready. <br> This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
| Escape Mode Receive Signals | | | |
| RxCIkEsc | O | MXXY SXXX | Escape mode Receive Clock. <br> This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
| RxLpdtEsc | O | MXXA SXAX | Escape Low-Power Data Receive mode. <br> This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
| RxUlpsEsc | O | MXXY <br> SXXX | Escape Ultra-Low Power (Receive) mode. <br> This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger.
Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Receive Trigger 0-3. |
| :--- |
| These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. |
| RxTriggerEsc[0] corresponds to Reset-Trigger. |
| RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| RxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc.
Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc.| Escape mode Receive Data. |
| :--- |
| This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data.
Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data.| Escape mode Receive Data Valid. |
| :--- |
| This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored.
Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored.| Turn Around Request. |
| :--- |
| This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0=0= Output). When Direction=1, the Lane is in receive mode (1=Input).
Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input).| Transmit/Receive Direction. |
| :--- |
| This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module.
Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module.| Disable Turn-around. |
| :--- |
| This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer.
Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer.| Force Lane Module Into Receive mode / Wait for Stop state. |
| :--- |
| This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
Symbol Dir Categories Description
RxTriggerEsc[3:0] O "MXXY
SXXX" "Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger."
RxDataEsc[7:0] O "MXXA
SXAX" "Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc."
RxValidEsc O "MXXA
SXAX" "Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data."
Control Signals
TurnRequest I "XRXX
XFXY" "Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored."
Direction 0 " XRXX
XFXY " "Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input)."
TurnDisable I " XRXX
XFXY " "Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module."
ForceRxmode I "MRXX
MXXY
SXXX" "Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxTriggerEsc[3:0] | O | MXXY <br> SXXX | Escape mode Receive Trigger 0-3. <br> These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. <br> RxTriggerEsc[0] corresponds to Reset-Trigger. <br> RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> RxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| RxDataEsc[7:0] | O | MXXA <br> SXAX | Escape mode Receive Data. <br> This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
| RxValidEsc | O | MXXA <br> SXAX | Escape mode Receive Data Valid. <br> This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
| Control Signals | | | |
| TurnRequest | I | XRXX <br> XFXY | Turn Around Request. <br> This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
| Direction | 0 | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Transmit/Receive Direction. <br> This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
| TurnDisable | I | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Disable Turn-around. <br> This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
| ForceRxmode | I | MRXX <br> MXXY <br> SXXX | Force Lane Module Into Receive mode / Wait for Stop state. <br> This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
Symbol 符號
Dir
Categories 類別
Description 描述
ForceTxStopmode
I
MXXX
SRXX
SXXY
MXXX
SRXX
SXXY| MXXX |
| :--- |
| SRXX |
| SXXY |
Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state. 強制通道模組進入傳輸模式 / 生成停止狀態。此信號允許協議在初始化或出現錯誤情況（例如超時）時強制通道模組進入傳輸模式和停止狀態。當此信號為高時，通道模組立即轉換為傳輸模式，模組狀態機被強制進入停止狀態。
Stopstate
O
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
通道處於停止狀態。這個高電平信號表示通道模組，無論是發射器還是接收器，當前都處於停止狀態。請注意，這個信號與 PPI 介面中的任何時鐘都是非同步的。此外，協議可能會使用這個信號間接確定 PHY 線路電平是否處於 LP-11 狀態。
Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state.
Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state.| Lane is in Stop state. |
| :--- |
| This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
Enable 啟用
I
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
啟用車道模組。此高電位信號強制車道模組脫離“關閉”狀態。當啟用信號為低時，所有線驅動器、接收器、終端和爭用檢測器都會關閉。此外，當啟用信號為低時，所有其他 PPI 輸入將被忽略，所有 PPI 輸出將被驅動到默認的非活動狀態。啟用信號是一個電平敏感信號，並不依賴於任何時鐘。
Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock.
Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock.| Enable Lane Module. |
| :--- |
| This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted.
Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted.| Transmit Ultra-Low Power State on Clock Lane. |
| :--- |
| This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect.
Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect.| Receive Ultra-Low Power State on Clock Lane. |
| :--- |
| This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted.
ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted.| ULP State (not) Active. |
| :--- |
| This active low signal is asserted to indicate that the Lane is in ULP state. |
| For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. |
| For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
Symbol Dir Categories Description
ForceTxStopmode I "MXXX
SRXX
SXXY" Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state.
Stopstate O "XXXX
XCNN" "Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state."
Enable I "XXXX
XCNN" "Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock."
TxUlpsClk I MCNN "Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted."
RxUlpsClkNot 0 SCNN "Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect."
UlpsActiveNot O "XXXX
XCNN" "ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| ForceTxStopmode | I | MXXX <br> SRXX <br> SXXY | Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state. |
| Stopstate | O | XXXX <br> XCNN | Lane is in Stop state. <br> This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
| Enable | I | XXXX <br> XCNN | Enable Lane Module. <br> This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
| TxUlpsClk | I | MCNN | Transmit Ultra-Low Power State on Clock Lane. <br> This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
| RxUlpsClkNot | 0 | SCNN | Receive Ultra-Low Power State on Clock Lane. <br> This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
| UlpsActiveNot | O | XXXX <br> XCNN | ULP State (not) Active. <br> This active low signal is asserted to indicate that the Lane is in ULP state. <br> For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. <br> For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
Symbol 符號
Dir
Categories 類別
Description 描述
Error Signals 錯誤信號
ErrSotHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
傳輸開始（SoT）錯誤。如果高速 SoT 領導序列損壞，但仍能實現適當的同步，則此主動高信號在 RxWordCIkHS 的一個週期內被斷言。這被視為領導序列中的“軟錯誤”，並且對有效載荷數據的信心降低。
Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced.
Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced.| Start-of-Transmission (SoT) Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
ErrSotSyncHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
傳輸開始同步錯誤。如果高速 SoT 領導序列以無法預期正確同步的方式損壞，則此高電平信號在 RxWordCIkHS 的一個週期內被置為有效。
Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS.
Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS.| Start-of-Transmission Synchronization Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state.
Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state.| Escape Entry Error. |
| :--- |
| If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state.
Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state.| Low-Power Data Transmission Synchronization Error. |
| :--- |
| If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state.
Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state.| Control Error. |
| :--- |
| This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
ErrContentionLPO
O
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
LPO 競爭錯誤。當通道模組在嘗試將線路拉低時檢測到線路上的競爭情況時，會啟用此高電平信號。
LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low.
LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low.| LPO Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
ErrContentionLP1
O
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
LP1 競爭錯誤。當通道模組在嘗試將線路拉高時檢測到線路上的競爭情況時，會啟用此高電平信號。
LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high.
LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high.| LP1 Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Symbol Dir Categories Description
Error Signals
ErrSotHS O "MRXX
SXXX" "Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced."
ErrSotSyncHS O "MRXX
SXXX" "Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS."
ErrEsc O "MXXY
SXXX" "Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state."
ErrSyncEsc O "MXXA
SXAX" "Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state."
ErrControl O "MXXY
SXXX" "Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state."
ErrContentionLPO O "MXXX
SXXY" "LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low."
ErrContentionLP1 O "MXXX
SXXY" "LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Error Signals | | | |
| ErrSotHS | O | MRXX <br> SXXX | Start-of-Transmission (SoT) Error. <br> If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
| ErrSotSyncHS | O | MRXX <br> SXXX | Start-of-Transmission Synchronization Error. <br> If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
| ErrEsc | O | MXXY <br> SXXX | Escape Entry Error. <br> If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrSyncEsc | O | MXXA <br> SXAX | Low-Power Data Transmission Synchronization Error. <br> If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrControl | O | MXXY <br> SXXX | Control Error. <br> This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
| ErrContentionLPO | O | MXXX <br> SXXY | LPO Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
| ErrContentionLP1 | O | MXXX <br> SXXY | LP1 Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Table 39 summarizes the signals that are affected by the choice of the transmit data path width. 表 39 總結了受傳輸數據通道寬度選擇影響的信號。
Table 39 Tx HS PPI Signals, Impact of Data Path Width 表 39 Tx HS PPI 信號，數據通路寬度的影響
8-bit 16-bit 32-bit
Tx HS Word Clock Rate 1/8 the HS bit rate 1/16 the HS bit rate 1/32 the HS bit rate
Tx HS Data Path TxDataHS[7:0] TxDataHS[15:0] TxDataHS[31:0]
HS Transmit Word Valid "TxWordValidHS[0] rarr
TxDataHS[7:0]" "TxWordValidHS[0] rarr TxDataHS[7:0];
TxWordValidHS[1] rarr TxDataHS[15:8]" "TxWordValidHS[0] rarr
TxDataHS[7:0];
TxWordValidHS[1] rarr
TxDataHS[15:8];
TxWordValidHS[2] rarr
TxDataHS[23:16];
TxWordValidHS[3] rarr
TxDataHS[31:24]"| | 8-bit | 16-bit | 32-bit |
| :---: | :---: | :---: | :---: |
| Tx HS Word Clock Rate | 1/8 the HS bit rate | 1/16 the HS bit rate | 1/32 the HS bit rate |
| Tx HS Data Path | TxDataHS[7:0] | TxDataHS[15:0] | TxDataHS[31:0] |
| HS Transmit Word Valid | TxWordValidHS[0] $\rightarrow$ <br> TxDataHS[7:0] | TxWordValidHS[0] $\rightarrow$ TxDataHS[7:0]; <br> TxWordValidHS[1] $\rightarrow$ TxDataHS[15:8] | TxWordValidHS[0] $\rightarrow$ <br> TxDataHS[7:0]; <br> TxWordValidHS[1] $\rightarrow$ <br> TxDataHS[15:8]; <br> TxWordValidHS[2] $\rightarrow$ <br> TxDataHS[23:16]; <br> TxWordValidHS[3] $\rightarrow$ <br> TxDataHS[31:24] |
Table 40 summarizes the signals that are affected by the choice of the transmit data path width. 表 40 總結了受傳輸數據通道寬度選擇影響的信號。
Table 40 Rx HS PPI Signals, Impact of Data Path Width 表 40 Rx HS PPI 信號，數據通路寬度的影響
8-bit 16-bit 32-bit
Rx HS Word Clock Rate 1/8 the HS bit rate 1/16 the HS bit rate 1/32 the HS bit rate
Rx HS Data Path RxDataHS[7:0] RxDataHS[15:0] RxDataHS[31:0]
HS Receive Word Valid RxValidHS[0] rarr RxDataHS[7:0] RxValidHS[0] rarr RxDataHS[7:0]; RxValidHS[1] rarr RxDataHS[15:8] "RxValidHS[0] rarr RxDataHS[7:0];
RxValidHS[1] rarr RxDataHS[15:8];
RxValidHS[2] rarr RxDataHS[23:16];
RxValidHS[3] rarr RxDataHS[31:24]"| | 8-bit | 16-bit | 32-bit |
| :---: | :---: | :---: | :---: |
| Rx HS Word Clock Rate | 1/8 the HS bit rate | 1/16 the HS bit rate | 1/32 the HS bit rate |
| Rx HS Data Path | RxDataHS[7:0] | RxDataHS[15:0] | RxDataHS[31:0] |
| HS Receive Word Valid | RxValidHS[0] $\rightarrow$ RxDataHS[7:0] | RxValidHS[0] $\rightarrow$ RxDataHS[7:0]; RxValidHS[1] $\rightarrow$ RxDataHS[15:8] | RxValidHS[0] $\rightarrow$ RxDataHS[7:0]; <br> RxValidHS[1] $\rightarrow$ RxDataHS[15:8]; <br> RxValidHS[2] $\rightarrow$ RxDataHS[23:16]; <br> RxValidHS[3] $\rightarrow$ RxDataHS[31:24] |
A. 2 High-Speed Transmit from the Master Side A. 2 高速從主端傳輸
Figure 66 shows an example of a High-Speed transmission on the Master side. While TxRequestHS is low, the Lane Module ignores the value of TxDataHS. To begin transmission, the protocol drives TxDataHS with the first byte of data and asserts TxRequestHS. This data byte is accepted by the PHY on the first rising edge of TxWordClkHS with TxReadyHS also asserted. At this point, the protocol logic drives the next data byte onto TxDataHS. After every rising clock cycle with TxReadyHS active, the protocol supplies a new valid data byte or ends the transmission. After the last data byte has been transferred to the Lane Module, TxRequestHS is driven low to cause the Lane Module to stop the transmission and enter Stop state. The minimum number of bytes transmitted could be as small as one. 圖 66 顯示了主端高速傳輸的示例。當 TxRequestHS 為低時，通道模組忽略 TxDataHS 的值。要開始傳輸，協議用第一個數據字節驅動 TxDataHS 並使 TxRequestHS 有效。這個數據字節在 TxWordClkHS 的第一次上升沿被 PHY 接受，並且 TxReadyHS 也被使能。此時，協議邏輯將下一個數據字節驅動到 TxDataHS。在每個上升時鐘週期中，只要 TxReadyHS 處於活動狀態，協議就會提供一個新的有效數據字節或結束傳輸。在最後一個數據字節傳輸到通道模組後，TxRequestHS 被驅動為低，以使通道模組停止傳輸並進入停止狀態。傳輸的最小字節數可以小至一個。
Figure 66 Example High-Speed Transmission from the Master Side (One-Byte Bus Width) 圖 66 來自主端的高速傳輸示例（單字節總線寬度）
A. 3 High-Speed Receive at the Slave Side A. 3 高速接收在從屬端
Figure 67 shows an example of a High-Speed reception at the Slave side. The RxActiveHS signal indicates that a receive operation is occurring. A normal reception starts with a pulse on RxSyncHS followed by valid receive data on subsequent cycles of RxWordClkHS. Note that the protocol is prepared to receive all of the data. There is no method for the receiving protocol to pause or slow data reception. 圖 67 顯示了從屬端的高速接收示例。RxActiveHS 信號表示正在進行接收操作。正常接收以 RxSyncHS 上的脈衝開始，隨後在 RxWordClkHS 的後續週期上有有效的接收數據。請注意，該協議已準備好接收所有數據。接收協議沒有暫停或減慢數據接收的方法。
If EoT Processing is performed inside the PHY, the RxActiveHS and RxValidHS signals transition low following the last valid data byte, Bn. See Figure 67. 如果在 PHY 內部執行 EoT 處理，則 RxActiveHS 和 RxValidHS 信號在最後一個有效數據字節 Bn 之後轉為低電平。請參見圖 67。
If EoT processing is not performed in the PHY, one or more additional bytes are presented after the last valid data byte. The first of these additional bytes, shown as byte “C” in Figure 67, is all ones or all zeros. Subsequent bytes may or may not be present, and can have any value. For a PHY that does not perform EoT processing, the RxActiveHS and RxValidHS signals transition low simultaneously some time after byte “C” is received. Once these signals have transitioned low, they remain low until the next High-Speed data reception begins. 如果在 PHY 中未執行 EoT 處理，則在最後一個有效數據字節之後會出現一個或多個附加字節。這些附加字節中的第一個，如圖 67 所示的字節“C”，是全為 1 或全為 0。隨後的字節可能存在也可能不存在，並且可以具有任何值。對於不執行 EoT 處理的 PHY，RxActiveHS 和 RxValidHS 信號在接收到字節“C”後的某個時刻同時轉為低電平。一旦這些信號轉為低電平，它們將保持低電平，直到下一次高速數據接收開始。
Figure 67 Example High-Speed Receive at the Slave Side (One-Byte Bus Width) 圖 67 範例 高速接收在從屬端（單字節總線寬度）
A. 4 High-Speed Transmit from the Slave Side A. 4 高速從從屬端傳輸
A Slave can only transmit at one-fourth the bandwidth of a Master. Because of this, the TxReadyHS signal is not constant high for a transmitting slave. Otherwise, the transmission is very much like that seen at the PPI interface of a transmitting Master-side Lane Module. Figure 68 shows an example of transmitting from the Slave side. 從屬設備的傳輸帶寬僅為主設備的四分之一。因此，對於傳輸中的從屬設備，TxReadyHS 信號並不是持續高電平。否則，傳輸與主設備側通道模組的 PPI 介面上看到的非常相似。圖 68 顯示了從從屬設備側傳輸的示例。
Figure 68 Example High-Speed Transmit from the Slave Side (One-Byte Bus Width) 圖 68 範例 高速從從屬端傳輸（單字節總線寬度）
A. 5 High-Speed Receive at the Master Side A. 5 高速接收在主端
Because a Slave is restricted to transmitting at one-fourth the bandwidth of a Master, the RxValidHS signal is only asserted one out of every four cycles of RxWordClkHS during a High-Speed receive operation at the Master side. An example of this is shown in Figure 69. Note that, depending on the bit rate, there may be one or more extra pulses on RxValidHS after the last valid byte, Bn, is received. 因為從屬設備的傳輸帶寬僅為主設備的四分之一，因此在主設備的高速接收操作中，RxValidHS 信號僅在每四個 RxWordClkHS 週期中有一個週期被置為有效。這在圖 69 中有示例。請注意，根據比特率的不同，在接收到最後一個有效字節 Bn 後，RxValidHS 上可能會有一個或多個額外的脈衝。
Figure 69 Example High-Speed Receive at the Master Side (One-Byte Bus Width) 圖 69 範例 高速接收在主端（單字節總線寬度）
A. 6 Low-Power Data Transmission A. 6 低功耗數據傳輸
For Low-Power data transmission the TxClkEsc is used instead of TxDDRClkHS-I/Q and TxWordClkHS. Furthermore, while the High-Speed interface signal TxRequestHS serves as both a transmit request and a data valid signal, on the Low-Power interface two separate signals are used. The Protocol directs the Data Lane to enter Low-Power data transmission Escape mode by asserting TxRequestEsc with TxLpdtEsc high. The Low-Power transmit data is transferred on the TxDataEsc lines when TxValidEsc and TxReadyEsc are both active at a rising edge of TxClkEsc. The byte is transmitted in the time after the TxDataEsc is accepted by the Lane Module (TxValidEsc=(T x V a l i d E s c= TxReadyEsc == high) and therefore the TxClkEsc continues running for some minimum time after the last byte is transmitted. The Protocol knows the byte transmission is finished when TxReadyEsc is asserted. After the last byte has been transmitted, the protocol de-asserts TxRequestEsc to end the Low-Power data transmission. This causes TxReadyEsc to return low, after which the TxClkEsc clock is no longer needed. Whenever TxRequestEsc transitions from high-to-low, it always remains in the low state for a minimum of two TxClkEsc clock cycles. Figure 70 shows an example LowPower data transmission operation. 對於低功耗數據傳輸，使用 TxClkEsc 代替 TxDDRClkHS-I/Q 和 TxWordClkHS。此外，雖然高速接口信號 TxRequestHS 同時作為傳輸請求和數據有效信號，但在低功耗接口中使用兩個獨立的信號。協議通過將 TxRequestEsc 與 TxLpdtEsc 設置為高電平來指示數據通道進入低功耗數據傳輸逃逸模式。當 TxValidEsc 和 TxReadyEsc 在 TxClkEsc 的上升沿都處於活動狀態時，低功耗傳輸數據在 TxDataEsc 線上傳輸。字節在 TxDataEsc 被通道模塊接受後的時間內傳輸（ (TxValidEsc=(T x V a l i d E s c= TxReadyEsc == 為高），因此 TxClkEsc 在最後一個字節傳輸後仍然繼續運行一段最小時間。當 TxReadyEsc 被設置為高時，協議知道字節傳輸已完成。在最後一個字節傳輸後，協議取消設置 TxRequestEsc 以結束低功耗數據傳輸。這會導致 TxReadyEsc 返回低電平，之後不再需要 TxClkEsc 時鐘。每當 TxRequestEsc 從高電平轉變為低電平時，它始終保持在低狀態至少兩個 TxClkEsc 時鐘週期。 圖 70 顯示了一個低功耗數據傳輸操作的例子。
Clock No 時鐘號碼
Figure 70 Low-Power Data Transmission 圖 70 低功耗數據傳輸
A. 7 Low-Power Data Reception A. 7 低功耗數據接收
Figure 71 shows an example Low-Power data reception. In this example, a Low-Power escape “clock” is generated from the Lane Interconnect by the logical exclusive-OR of the Dp and Dn lines. This “clock” is used within the Lane Module to capture the transmitted data. In this example, the “clock” is also used to generate RxClkEsc. 圖 71 顯示了一個低功耗數據接收的例子。在這個例子中，低功耗逃逸“時鐘”是通過 Dp 和 Dn 線的邏輯異或從通道互連生成的。這個“時鐘”在通道模塊內用於捕獲傳輸的數據。在這個例子中，“時鐘”也用於生成 RxClkEsc。
The signal RxLpdtEsc is asserted when the escape entry command is detected and stays high until the Lane returns to Stop state, indicating that the transmission has finished. It is important to note that because of the asynchronous nature of Escape mode transmission, the RxClkEsc signal can stop at anytime in either the high or low state. This is most likely to happen just after a byte has been received, but it could happen at other times as well. 當檢測到逃逸進入命令時，信號 RxLpdtEsc 被置為高電平，並保持高電平直到通道返回到停止狀態，這表示傳輸已經完成。需要注意的是，由於逃逸模式傳輸的非同步特性，RxClkEsc 信號可以在高電平或低電平狀態下隨時停止。這最有可能發生在接收到一個字節之後，但也可能在其他時間發生。
Figure 71 Example Low-Power Data Reception 圖 71 低功耗數據接收示例
A. 8 Turn-around A. 8 轉彎
If the Master side and Slave side Lane Modules are both bi-directional, it is possible to turn around the Link for High-Speed and/or Escape mode signaling. As explained in Section 6.5, which side is allowed to transmit is determined by passing a “token” back and forth. That is, the side currently transmitting passes the token to the receiving side. If the receiving side acknowledges the turn-around request, as indicated by driving the appropriate line state, the direction is switched. 如果主端和從端的通道模組都是雙向的，則可以為高速和/或逃逸模式信號轉換鏈路。如第 6.5 節所述，哪一方被允許傳輸是通過來回傳遞“令牌”來決定的。也就是說，當前正在傳輸的一方將令牌傳遞給接收方。如果接收方確認轉換請求，通過驅動適當的線路狀態來表示，則方向會切換。
23-Nov-2015
Figure 72 shows an example of two turn-around events. At the beginning, the local side is the transmitter, as shown by Direction=0. When the protocol on this side wishes to turn the Lane around (i.e. give the token to the other side), it asserts TurnRequest for at least one cycle of TxClkEsc. This initiates the turn-around procedure. The remote side acknowledges the turn-around request by driving the appropriate states on the Lines. When this happens, the local Direction signal changes from transmit (0) to receive (1). 圖 72 顯示了兩個轉向事件的例子。一開始，當地一方是發射器，如方向=0 所示。當這一方的協議希望將通道轉向（即將令牌交給另一方）時，它會在 TxClkEsc 的至少一個週期內發出 TurnRequest。這啟動了轉向程序。遠端一方通過在線路上驅動適當的狀態來確認轉向請求。當這發生時，當地的方向信號從發送（0）變為接收（1）。
Later in the example of Figure 72, the remote side initiates a turn-around request, passing the token back to the local side. When this happens, the local Direction signal changes back to transmit (0). Note that there is no prescribed way for a receiver to request access to the Link. The current transmitter is in control of the Link direction and decides when to turn the Link around, passing control to the receiver. 在圖 72 的例子中，遠端發起了一個回轉請求，將令牌傳回本地端。當這發生時，本地的方向信號會改回傳輸（0）。請注意，接收方沒有規定的方式來請求訪問鏈路。當前的發射器控制著鏈路方向，並決定何時將鏈路轉向，將控制權交給接收器。
If the remote side does not acknowledge the turn-around request, the Direction signal does not change. 如果遠端不承認回轉請求，方向信號不會改變。
Figure 72 Example Turn-around Actions Transmit-to-Receive and Back to Transmit 圖 72 例子 轉換動作 從發送到接收再回到發送
A. 9 Calibration A. 9 校準
Initiation of periodic deskew calibration from the transmitter can be done using the TxSkewCalHS pin on the PPI interface. This is an optional signal pin, and periodic deskew is an optional feature. Receiver deskew can be by-passable using the receiver configuration control. Figure 73 shows the PPI signal outputs as they operate during high-speed data transmission in normal mode. 從發射器啟動定期去斜校準可以使用 PPI 介面的 TxSkewCalHS 引腳。這是一個可選的信號引腳，定期去斜是一個可選的功能。接收器去斜可以通過接收器配置控制來繞過。圖 73 顯示了在正常模式下高速數據傳輸期間 PPI 信號輸出的運作情況。
Figure 73 Periodic Skew Calibration - PPI Signal in Normal Mode 圖 73 週期性偏斜校準 - 正常模式下的 PPI 信號
Figure 74 shows the PPI signal outputs as they operate during skew calibration in high-speed data transmission. It is possible for the RxWordClkHS to vary in frequency and duty cycle during the deskew operation. If the RxWordClkHS is varied, the period variation from clock period to clock period shall not be reduced by more than 0.5 UI with respect to the nominal period of RxWordClkHS. 圖 74 顯示了在高速數據傳輸中進行偏移校準時 PPI 信號輸出的情況。RxWordClkHS 在去偏移操作期間的頻率和佔空比可能會變化。如果 RxWordClkHS 發生變化，則每個時鐘週期之間的週期變化不得超過 RxWordClkHS 的標稱週期的 0.5 UI。
Figure 74 Periodic Skew Calibration - PPI Signal during Skew Calibration 圖 74 週期性偏斜校準 - 偏斜校準期間的 PPI 信號
A. 10 Optical Link Support A. 10 光學連接支援
A.10.1 System Setup A.10.1 系統設置
Figure 75 Typical System Setup with Optical Interconnect 圖 75 典型的光互連系統設置
Figure 75 shows a typical setup for a D-PHY system using an optical link. 圖 75 顯示了一個使用光鏈路的 D-PHY 系統的典型設置。
The setup consists of a D-PHY Master providing the master clock and data lanes, and a serializer which multiplexes the data content of N data lanes into a single bit stream with embedded clock. The HS clock provided on the master clock lane is used as a reference for the clock multiplying unit in the serializer. The single bit stream is then converted from an electrical signal to an optical signal by means of a laser driver and a laser diode (LD) connected to it. 該設置由一個提供主時鐘和數據通道的 D-PHY 主控器和一個將 N 個數據通道的數據內容多路復用為單一位流並嵌入時鐘的序列化器組成。主時鐘通道上提供的 HS 時鐘用作序列化器中時鐘倍增單元的參考。然後，單一位流通過連接到激光驅動器和激光二極管（LD）的方式，將電信號轉換為光信號。
The optical signal transmitted through the optical fiber is converted back to an electrical signal by means of a photo diode (PD) and a transimpedance amplifier (TIA). The de-serializer synchronizes to the clock embedded in the serial data stream and de-multiplexes the data content of N data lanes. The output of the de-serializer to the D-PHY Slave is composed of a set of N D-PHY-compliant data lanes and a D-PHY compliant clock lane which replicates the D-PHY signal input to the serializer. 透過光纖傳輸的光信號通過光二極體（PD）和跨阻放大器（TIA）轉換回電信號。去序列化器與嵌入在串行數據流中的時鐘同步，並對 N 個數據通道的數據內容進行解多路復用。去序列化器輸出到 D-PHY 從設備的信號由一組 N 個符合 D-PHY 標準的數據通道和一個符合 D-PHY 標準的時鐘通道組成，該時鐘通道複製了輸入到序列化器的 D-PHY 信號。
An optical link implemented in this manner provides a transparent interface between a D-PHY Master and a D-PHY Slave. 以這種方式實現的光學連接提供了 D-PHY 主設備和 D-PHY 從設備之間的透明介面。
A.10.2 Serializer and De-Serializer Block Diagrams A.10.2 序列化器和反序列化器區塊圖
Figure 76 Block Diagram of Typical Serializer for Optical Link 圖 76 光纖連接的典型序列器方塊圖
Figure 77 Block Diagram of Typical De-Serializer for Optical Link 圖 77 光纖連接典型反序列化器的方塊圖
Figure 76 and Figure 77 show typical block diagrams for serializers and de-serializers used to implement the optical link. 圖 76 和圖 77 顯示了用於實現光學連接的串行器和反串行器的典型方塊圖。
A.10.3 Timing Constraints A.10.3 時間限制
Figure 78 Delay Between Start of HS Clock and HS Data Transmission Without Optical Link 圖 78 HS 時鐘啟動與 HS 數據傳輸之間的延遲（無光學連接）
Figure 78 shows that in a purely electrical D-PHY interconnect, there is a timing delay between the start of HS clock transmission and the start of HS data transmission equal to the sum of T_(CLK"-PRE ")+T_(LPX)+T_(HS-)\mathrm{T}_{\mathrm{CLK} \text {-PRE }}+\mathrm{T}_{\mathrm{LPX}}+\mathrm{T}_{\mathrm{HS}-} settle. However if an optical link is added as shown in Figure 75, then the serializer’s clock multiplying unit (typically a PLL) and the de-serializer’s clock and data recovery (CDR) require synchronization times that exceed this timing delay. 圖 78 顯示，在純電氣 D-PHY 互連中，HS 時鐘傳輸開始與 HS 數據傳輸開始之間存在一個時間延遲，等於 T_(CLK"-PRE ")+T_(LPX)+T_(HS-)\mathrm{T}_{\mathrm{CLK} \text {-PRE }}+\mathrm{T}_{\mathrm{LPX}}+\mathrm{T}_{\mathrm{HS}-} 的總和。然而，如果如圖 75 所示添加了一個光學鏈路，則序列器的時鐘倍增單元（通常是 PLL）和反序列器的時鐘和數據恢復（CDR）需要的同步時間超過了這個時間延遲。
Therefore, for an optical D-PHY interconnect an additional wait time TWart-optical ^("shall ")^{\text {shall }} be inserted before any HS data is transmitted, in order to provide enough timing headroom for the optical link to establish synchronization. 因此，對於光學 D-PHY 互連，在傳輸任何 HS 數據之前，必須插入額外的等待時間 TWart-optical ^("shall ")^{\text {shall }} ，以便為光學鏈路建立同步提供足夠的時間裕度。
Figure 79 Delay Between Start of HS Clock and HS Data Transmission With Optical Link 圖 79 HS 時鐘啟動與 HS 數據傳輸之間的延遲（光纖連接）
Figure 79 illustrates the additional wait time T_("wait-optical ")\mathrm{T}_{\text {wait-optical }} inserted between the end of T_("Clk-pre ")\mathrm{T}_{\text {Clk-pre }} and the beginning of T_(LPX)\mathrm{T}_{\mathrm{LPX}} of the first data lane scheduled to switch from STOP state to HS data mode. The additional wait time T_("watr-optical ")T_{\text {watr-optical }} ensures that the optical link is fully synchronized by the time the first data lane switches from the STOP state to HS data mode. If the duration of the inserted T_("wait-optical ")\mathrm{T}_{\text {wait-optical }} is too 圖 79 顯示了在第一數據通道從停止狀態切換到高速數據模式的結束 T_("Clk-pre ")\mathrm{T}_{\text {Clk-pre }} 和開始 T_(LPX)\mathrm{T}_{\mathrm{LPX}} 之間插入的額外等待時間 T_("wait-optical ")\mathrm{T}_{\text {wait-optical }} 。額外的等待時間 T_("watr-optical ")T_{\text {watr-optical }} 確保在第一數據通道從停止狀態切換到高速數據模式時，光學鏈路已完全同步。如果插入的 T_("wait-optical ")\mathrm{T}_{\text {wait-optical }} 持續時間過長，
short, then the optical link will not be able to correctly transmit the beginning of the next HS data burst, resulting in loss of state information and of HS data. 如果短，則光學連接將無法正確傳輸下一個 HS 數據突發的開始，導致狀態信息和 HS 數據的丟失。
A.10.4 System Constraints A.10.4 系統限制
A.10.4.1 Bus Turnaround A.10.4.1 公車調頭
Due to the optical link’s inherently unidirectional nature, bus turnaround (BTA) may not be supported with an optical link. 由於光纖連接本質上是單向的，因此可能不支持光纖連接的總線回轉（BTA）。
A.10.4.2 Equalization (De-emphasis), Deskewing, and Spread Spectrum Clocking A.10.4.2 均衡（去強調）、去偏移和擴頻時鐘
Equalization (de-emphasis), deskewing and spread spectrum clocking may be supported by the optical link manufacturer. This must be stated in the corresponding datasheet of the optical link. If these features are included in the optical link, then the electrical inputs of the optical link shall follow the D-PHY specification for a D-PHY RX, and the electrical outputs of the optical link shall follow the specification for a D-PHY TX for these features. System integrators must take care to ensure compliance during implementation. 均衡（去強調）、去傾斜和擴頻時鐘可能由光鏈路製造商支持。這必須在光鏈路的相應數據表中說明。如果這些功能包含在光鏈路中，則光鏈路的電氣輸入應遵循 D-PHY RX 的 D-PHY 規範，光鏈路的電氣輸出應遵循這些功能的 D-PHY TX 規範。系統集成商必須在實施過程中確保合規性。
A.10.4.3 TWAIT-OPTICAL
Table 41 specifies T_("wait-optical, ")\mathrm{T}_{\text {wait-optical, }}, the parameter for additional wait time for synchronization of the optical link. 表 41 指定了 T_("wait-optical, ")\mathrm{T}_{\text {wait-optical, }} ，光學鏈路同步的額外等待時間參數。
Table 41 Timing with Optical Link 表 41 光學連接的時序
Parameter 參數
Description 描述
Min
Units 單位
TWAIT-OPTICAL
Additional wait time for synchronization of the optical link 光鏈路同步的額外等待時間
150,000
UI (lane data bit)
Parameter Description Min Units
TWAIT-OPTICAL Additional wait time for synchronization of the optical link 150,000 UI (lane data bit)| Parameter | Description | Min | Units |
| :---: | :---: | :---: | :---: |
| TWAIT-OPTICAL | Additional wait time for synchronization of the optical link | 150,000 | UI (lane data bit) |
Annex B Interconnect Design Guidelines (informative) 附錄 B 互連設計指導方針（資訊性）
This appendix contains design guidelines in order to meet the interconnect requirements as specified in Section 8. 本附錄包含設計指導方針，以滿足第 8 節中規定的互連要求。
B. 1 Practical Distances B. 1 實際距離
The maximum Lane flight time is defined at two nanoseconds. Assuming less than 100ps wiring delay within the RX-TX modules each, the physical distance that can be bridged with external interconnect is around 54cm//sqrtepsi54 \mathrm{~cm} / \sqrt{\varepsilon}. For most practical PCB and flex materials this corresponds to maximum distances around 25-30 cm. 最大通道飛行時間定義為兩納秒。假設每個 RX-TX 模塊內的布線延遲少於 100 皮秒，則可以通過外部互連橋接的物理距離約為 54cm//sqrtepsi54 \mathrm{~cm} / \sqrt{\varepsilon} 。對於大多數實用的 PCB 和柔性材料，這對應於最大距離約為 25-30 厘米。
B. 2 RF Frequency Bands: Interference B. 2 RF 頻率頻段：干擾
On one side of the Lane there are the RF interference frequencies, which disturb the signals of the Lane. Most likely the dominant interferers are the transmit band frequencies of wireless interconnect standards. On the other side there are the frequencies for which generated EMI by the Lane should be as low as possible because very weak signals in these bands must be received by the radio IC. Some important frequency bands are: 在巷道的一側是射頻干擾頻率，這些頻率會干擾巷道的信號。最有可能的主要干擾源是無線互連標準的發射頻帶頻率。另一方面，有些頻率的產生電磁干擾應該盡可能低，因為這些頻段中的非常微弱信號必須被無線電集成電路接收。一些重要的頻帶包括：
Transmit Bands 傳輸頻段
GSM 850 (824-849 MHz) GSM 850 (824-849 兆赫)
GSM 900 (880-915 MHz) GSM 900 (880-915 兆赫)
GSM DCS (1710-1785 MHz)
GSM PCS (1850-1910 MHz)
WCDMA (1920-1980 MHz)
FLASH-OFDM, GSM (450 MHz)
Receive Bands: 接收頻道：
GSM 850 (869-894 MHz)
GSM 900 (925-960 MHz ) GSM 900 (925-960 兆赫)
GSM DCS (1805-1880 MHz)
GSM PCS (1930-1990 MHz)
WCDMA (2110-2170 MHz)
GPS (1574-1577 MHz)
It is important to identify the lowest interference frequency with significant impact, as this sets ’ f_("INTMin ")\mathrm{f}_{\text {INTMin }} '. For this specification, f_(INT,MIN)\mathrm{f}_{\mathrm{INT}, \mathrm{MIN}} is decided to be 450 MHz , because this frequency will most likely be used as the new WCDMA band in the USA in the future. 重要的是要確定對影響最大的最低干擾頻率，因為這設置了 ' f_("INTMin ")\mathrm{f}_{\text {INTMin }} '。對於這個規範， f_(INT,MIN)\mathrm{f}_{\mathrm{INT}, \mathrm{MIN}} 決定為 450 MHz，因為這個頻率在未來最有可能被用作美國的新 WCDMA 頻段。
B. 3 Transmission Line Design B. 3 傳輸線設計
In most cases the transmission lines will either be designed as striplines and/or micro-striplines. The coupling between neighboring lines within a pair is small if the distance between them is > 2x>2 \mathrm{x} the dielectric thickness. For the separation of multiple pairs it is highly recommended to interleave the pairs with a ground or supply line in order to reduce coupling. 在大多數情況下，傳輸線將設計為條形線和/或微條形線。如果一對相鄰線之間的距離小於介電厚度 > 2x>2 \mathrm{x} ，則它們之間的耦合很小。為了減少耦合，強烈建議在多對之間插入接地或供電線。
B. 4 Reference Layer B. 4 參考層
In order to achieve good signal integrity and low EMI it is recommended that either a ground plane or a ground signal is in close proximity of any signal line. 為了實現良好的信號完整性和低電磁干擾，建議在任何信號線附近有接地平面或接地信號。
B. 5 Printed-Circuit Board B. 5 印刷電路板
For boards with a large number of conductor layers the dielectric spacing between layers may become so small that it would be hard to meet the characteristic impedance requirements. In those cases a microstripline in the top or bottom layers may be a better solution. 對於具有大量導體層的電路板，層之間的介電間距可能變得非常小，以至於難以滿足特徵阻抗要求。在這些情況下，頂層或底層的微帶線可能是一個更好的解決方案。
B. 6 Flex-foils B. 6 彈性薄膜
Either two conductor layers or a reasonable connected cover layer makes it much easier to meet the specifications 無論是兩層導體層還是合理連接的覆蓋層，都使滿足規範變得更加容易
B. 7 Series Resistance B. 7 系列電阻
The DC series resistance of the interconnect should be less than 5 Ohms in order to meet the specifications. It is strongly recommended to keep the resistance in the ground connection below 0.2 Ohm. Furthermore, it is recommended that the DC ground shift be less than 50 mV , which may require an even lower value if a large current is flowing through this ground. The lower this ground series resistance value can be made, the better it is for reliability and robustness. 互連的直流系列電阻應小於 5 歐姆，以符合規範。強烈建議將接地連接的電阻保持在 0.2 歐姆以下。此外，建議直流接地偏移應小於 50 毫伏，如果通過此接地流動大電流，則可能需要更低的值。這個接地系列電阻值越低，對於可靠性和穩健性越有利。
B. 8 Connectors B. 8 連接器
Connectors usually cause some impedance discontinuity. It is important to carefully minimize these discontinuities by design, especially with respect to the through-connection of the reference layer. Although connectors are typically rather small in size, the wrong choice can mess-up signals completely. Please note that the contact resistance of connectors is part of the total series resistance budget and should therefore be sufficiently low. 連接器通常會造成一些阻抗不連續性。重要的是要通過設計仔細最小化這些不連續性，特別是在參考層的通過連接方面。雖然連接器通常尺寸相當小，但錯誤的選擇可能會完全干擾信號。請注意，連接器的接觸電阻是總串聯電阻預算的一部分，因此應該足夠低。
Annex C 8b9b Line Coding for D-PHY (normative) 附件 C 8b9b D-PHY 的行編碼（規範）
Raw data transmission without constraining the data set does not allow in-band control signaling (control symbols inserted into the data stream) during transmission. Line coding conditions the possible bit sequences on the wires and provides reserved codes to include additional control features. Useful additional features may be, for example, idle symbols, specific-event identifiers, sync patterns, and protocol markers. 在傳輸過程中，未對數據集進行約束的原始數據傳輸不允許進行帶內控制信號（插入數據流中的控制符號）。行編碼對電線上的可能位序列進行條件化，並提供保留代碼以包含額外的控制功能。有用的額外功能可能包括，例如，空閒符號、特定事件標識符、同步模式和協議標記。
Comma codes, bit sequences that do not appear anywhere in the data stream (in the absence of bit errors) unless these are intentionally transmitted, provide synchronization features and are very useful to increase robustness. 逗號碼，位元序列在數據流中不會出現（在沒有位元錯誤的情況下），除非這些是故意傳輸的，提供同步功能，並且對提高穩健性非常有用。
Furthermore, a line-coding scheme that guarantees a minimum edge density improves the signaling quality and enables skew calibration in the PHY. 此外，一種保證最小邊緣密度的行編碼方案可以改善信號質量並使物理層中的偏斜校準成為可能。
Figure 80 shows how the line coding sub-layer fits into the standard hierarchy. The line coding can be considered as a separate sub-layer on top of the basic D-PHY. Optimizations by merging layers are allowed if the resulting solution complies with the PHY specification. These optimization choices are left to implementers. 圖 80 顯示了行編碼子層如何適應標準層次結構。行編碼可以被視為位於基本 D-PHY 之上的一個獨立子層。如果合併層後的解決方案符合 PHY 規範，則允許進行優化。這些優化選擇留給實施者。
Figure 80 Line Coding Layer Example 圖 80 行編碼層範例
Note that the line coding sub-layer is optional. Protocols may exploit only the baseline PHY without line coding. This feature is provided for compatibility with existing protocols. However, in case a protocol decides to use line coding, it shall be implemented as described in this annex. 請注意，行編碼子層是可選的。協議可以僅利用基線物理層而不使用行編碼。此功能是為了與現有協議的兼容性而提供的。然而，如果某個協議決定使用行編碼，則應按照本附錄中所述進行實施。
The PHY-protocol interface above the line coding sub-layer (EPPI) is very similar to the PPI. Some additional signals enable a more functional and flexible control of the PHY with Line Coding. For details of the EPPI see Section C.5. 在行編碼子層之上的 PHY 協議介面（EPPI）與 PPI 非常相似。一些額外的信號使得對 PHY 與行編碼的控制更加功能性和靈活。關於 EPPI 的詳細信息，請參見 C.5 節。
C. 1 Line Coding Features C. 1 行編碼特徵
The 8b9b line coding scheme provides features to both the PHY and protocol layers. 8b9b 線編碼方案為物理層和協議層提供了功能。
C.1.1 Enabled Features for the Protocol C.1.1 協議的啟用功能
Comma code marker for special protocol features 特殊協議功能的逗號代碼標記
Word synchronization/resynchronization during transmission bursts 傳輸突發期間的字同步/重新同步
Automatic idling support; no need for TX to always provide valid data during transmission 自動怠速支援；在傳輸過程中無需 TX 始終提供有效數據
C.1.2 Enabled Features for the PHY C.1.2 已啟用的 PHY 功能
On-the-fly word resynchronization 即時字詞重新同步
Simplification of EoT signaling EoT 信號簡化
Reduced latency 降低延遲
Automatic idle symbol insertion and removal in absence of data 在缺少數據的情況下自動插入和移除閒置符號
Skew calibration in the RX possible RX 中的偏斜校準可能
C. 2 Coding Scheme C. 2 編碼方案
This section describes the details of the coding scheme. 本節描述了編碼方案的詳細信息。
C.2.1 8b9b Coding Properties C.2.1 8b9b 編碼屬性
The 8b9b coding has the following properties: 8b9b 編碼具有以下特性：
All code words are nine bits long. Data is encoded byte-wise into 9-bit words, which corresponds to a 12.5%12.5 \% coding overhead. 所有代碼字長九位元。數據以字節為單位編碼為九位元字，這對應於 12.5%12.5 \% 編碼開銷。
Sixteen regular exception codes, i.e. code words that do not appear as regular data words, but require word sync for reliable recognition, are available. 有十六個常規例外代碼，即不作為常規數據字出現的代碼字，但需要字同步以確保可靠識別。
Six unique exception codes, i.e. code words that do not appear within any sliding window except when that code word is transmitted, are available. 六個獨特的例外代碼，即在任何滑動窗口中都不會出現的代碼字，除非該代碼字被傳輸，現已可用。
Guaranteed minimum edge density of at least two polarity transitions per word. Therefore, each word contains at least two ones and two zeros. 保證每個單詞至少有兩個極性轉換的最小邊密度。因此，每個單詞至少包含兩個一和兩個零。
Simple logical functions for encoding and decoding 簡單的邏輯函數用於編碼和解碼
Run length is limited to a maximum of seven bits. Data codes have a maximum run length of five bits, unique exception codes have run lengths of six or seven bits. 運行長度限制為最多七位元。數據碼的最大運行長度為五位元，唯一的例外碼的運行長度為六或七位元。
C.2.2 Data Codes: Basic Code Set C.2.2 數據代碼：基本代碼集
Assume the following notation for the input data word and the coded data word: 假設以下符號表示輸入數據字和編碼數據字：
The 256 data codes are denoted by Dxxx, where xxx is the value of the corresponding 8-bit data byte. 這 256 個數據代碼用 Dxxx 表示，其中 xxx 是相應的 8 位數據字節的值。
The 8-bit data byte shall be the input for the encoding, and result of the decoding, function. There can be any arbitrary bijective 8b-to-8b logical transformation function between real source data bytes from the protocol and the input data bytes for encoding, as long as the inverse function is present at the receiver side. If such a function is used, it shall be defined in the protocol specification. 8 位元資料位元組應為編碼的輸入和解碼的結果。可以在協議的實際來源資料位元組與編碼的輸入資料位元組之間使用任何任意的雙射 8b 到 8b 邏輯轉換函數，只要接收端存在反函數。如果使用此類函數，則應在協議規範中定義。
The bits {B_(1),B_(2),B_(3),X_(1),X_(2)}\left\{\mathrm{B}_{1}, \mathrm{~B}_{2}, \mathrm{~B}_{3}, \mathrm{X}_{1}, \mathrm{X}_{2}\right\} appear directly in the code words as can be seen in the code word structure. 這些位元 {B_(1),B_(2),B_(3),X_(1),X_(2)}\left\{\mathrm{B}_{1}, \mathrm{~B}_{2}, \mathrm{~B}_{3}, \mathrm{X}_{1}, \mathrm{X}_{2}\right\} 直接出現在代碼字中，如代碼字結構所示。 {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} are the remaining three bits in the data byte, which are encoded into {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} using {X_(1),X_(2)}\left\{\mathrm{X}_{1}, \mathrm{X}_{2}\right\}. The decoding of {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} into {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} does not require {X_(1),X_(2)}\left\{\mathrm{X}_{1}, \mathrm{X}_{2}\right\}. {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} 是數據字節中剩餘的三個位，這些位使用 {X_(1),X_(2)}\left\{\mathrm{X}_{1}, \mathrm{X}_{2}\right\} 編碼為 {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} 。將 {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} 解碼為 {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} 不需要 {X_(1),X_(2)}\left\{\mathrm{X}_{1}, \mathrm{X}_{2}\right\} 。
The relation between Q_(i),X_(i)\mathrm{Q}_{\mathrm{i}}, \mathrm{X}_{\mathrm{i}} and Y_(i)\mathrm{Y}_{\mathrm{i}} is shown in Table 42. Q_(i),X_(i)\mathrm{Q}_{\mathrm{i}}, \mathrm{X}_{\mathrm{i}} 和 Y_(i)\mathrm{Y}_{\mathrm{i}} 之間的關係顯示在表 42 中。
Table 42 Encoding Table for 8b9b Line Coding of Data Words 表 42 8b9b 數據字的行編碼編碼表
Note: 注意： x=x= don’t care x=x= 不在乎
The logical relation for encoding between {Q_(1),Q_(2),Q_(3),X_(1),X_(2)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}, \mathrm{X}_{1}, \mathrm{X}_{2}\right\} and {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} is given by the following equations: 在 {Q_(1),Q_(2),Q_(3),X_(1),X_(2)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}, \mathrm{X}_{1}, \mathrm{X}_{2}\right\} 和 {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} 之間的編碼邏輯關係由以下方程式給出：
The logical relation for decoding between {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} and {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} is: 解碼時 {Y_(1),Y_(2),Y_(3),Y_(4)}\left\{\mathrm{Y}_{1}, \mathrm{Y}_{2}, \mathrm{Y}_{3}, \mathrm{Y}_{4}\right\} 和 {Q_(1),Q_(2),Q_(3)}\left\{\mathrm{Q}_{1}, \mathrm{Q}_{2}, \mathrm{Q}_{3}\right\} 之間的邏輯關係是：
These logical functions show that the encoding and decoding can be implemented with a few dozen logic gates and therefore do not require additional hardware such as a lookup table or storage of history data. 這些邏輯函數顯示編碼和解碼可以用幾十個邏輯閘來實現，因此不需要額外的硬體，例如查找表或歷史數據的存儲。
Unique means that these codes are uniquely identifiable in the data stream because these sequences do not occur in any encoding or across word boundaries, assuming no bits are corrupted. The data-encoding scheme described in Section C.2.2 enables a very simple run-length limit based unique exception code mechanism. 唯一的意思是這些代碼在數據流中是唯一可識別的，因為這些序列不會出現在任何編碼中或跨越單詞邊界，假設沒有位元被損壞。第 C.2.2 節中描述的數據編碼方案使得一個非常簡單的基於運行長度限制的唯一例外代碼機制成為可能。
There are four code sequences available, called Type A Comma codes, with a run length of six bits, and two code sequences, called Type B Comma codes, with a run length of seven bits. Currently, four Comma codes are sufficient to cover the required features and therefore only Type A Comma codes are used. Type B Comma codes are reserved for future use. 目前有四個可用的代碼序列，稱為 A 型逗號代碼，運行長度為六位元，還有兩個代碼序列，稱為 B 型逗號代碼，運行長度為七位元。目前，四個逗號代碼足以涵蓋所需的功能，因此僅使用 A 型逗號代碼。B 型逗號代碼則保留用於未來使用。
Table 43 Comma Codes 表 43 逗號代碼
Type 類型
Run Length, bits 運行長度，位元
Code Name 代號
Comma code
Feature 特徵
Type A A 型
6
C600
011111100
Protocol 協議
C611
100000011
EoT
C610
100000010
Idle/Sync 1 閒置/同步 1
C601
011111101
Idle/Sync 2
Type B B 型
7
C701
100000001
Reserved 1 保留 1
C710
011111110
Reserved 2 保留 2
Type Run Length, bits Code Name Comma code Feature
Type A 6 C600 011111100 Protocol
C611 100000011 EoT
C610 100000010 Idle/Sync 1
C601 011111101 Idle/Sync 2
Type B 7 C701 100000001 Reserved 1
C710 011111110 Reserved 2| Type | Run Length, bits | Code Name | Comma code | Feature |
| :---: | :---: | :---: | :---: | :---: |
| Type A | 6 | C600 | 011111100 | Protocol |
| | | C611 | 100000011 | EoT |
| | | C610 | 100000010 | Idle/Sync 1 |
| | | C601 | 011111101 | Idle/Sync 2 |
| Type B | 7 | C701 | 100000001 | Reserved 1 |
| | | C710 | 011111110 | Reserved 2 |
C.2.4 Control Codes: Regular Exception Codes C.2.4 控制碼：常規例外碼
The normal data set does not use all codes with a maximum run-length of five bits. There are two combinations of the {X_(i),Y_(i)}\left\{\mathrm{X}_{\mathrm{i}}, \mathrm{Y}_{\mathrm{i}}\right\} bits that do not appear in any data code word that are available as regular exception codes. Since Comma Codes are defined to have a run-length of six or seven bits, this gives three freely usable bits per code word and results in 2**2^(3)=162 * 2^{3}=16 different Regular Exception Codes. The syntax of the Regular Exception Code words is given in Table 44, where the bits B_(1),B_(2)B_{1}, B_{2} and B_(3)B_{3} can have any binary value. 正常數據集不使用所有最大運行長度為五位的代碼。有兩種 {X_(i),Y_(i)}\left\{\mathrm{X}_{\mathrm{i}}, \mathrm{Y}_{\mathrm{i}}\right\} 位的組合在任何數據代碼字中都不會出現，這些組合可作為常規例外代碼。由於逗號代碼被定義為具有六或七位的運行長度，這為每個代碼字提供了三個可自由使用的位，並產生了 2**2^(3)=162 * 2^{3}=16 個不同的常規例外代碼。常規例外代碼字的語法在表 44 中給出，其中位 B_(1),B_(2)B_{1}, B_{2} 和 B_(3)B_{3} 可以具有任何二進制值。
These code words are not unique sequences like the Comma codes described in Table 43, but can only be used as exception codes if word sync is already accomplished. These codes are currently reserved and not yet allocated to any function. 這些代碼詞並不是像表 43 中描述的逗號代碼那樣的唯一序列，而只能在已經完成單詞同步的情況下用作例外代碼。這些代碼目前是保留的，尚未分配給任何功能。
C.2.5 Complete Coding Scheme C.2.5 完整編碼方案
The complete code table can be found in Table 46. 完整的代碼表可以在表 46 中找到。
C. 3 Operation with the D-PHY C. 3 與 D-PHY 的操作
The line coding impacts the payload of transmission bursts. Section C.3.1 described the generic issues for both HS and LP transmission. Section C.3.2 and Section C.3.3 describe specific details for HS and LP transmission, respectively. 行編碼影響傳輸突發的有效載荷。C.3.1 節描述了 HS 和 LP 傳輸的通用問題。C.3.2 節和 C.3.3 節分別描述了 HS 和 LP 傳輸的具體細節。
C.3.1 Payload: Data and Control C.3.1 負載：數據和控制
The payload of a HS or LP transmission burst consists of concatenated serialized 9-bit symbols, representing both data and control information. HS 或 LP 傳輸突發的有效載荷由串聯的序列化 9 位元符號組成，代表數據和控制信息。
C.3.1.1 Idle/Sync Comma Symbols C.3.1.1 空閒/同步逗號符號
Idle/Sync Comma code words can be present as symbols within the payload of a transmission burst. These symbols are inserted either on specific request of the protocol, or autonomously when there is a transmission request but there is no valid data available either at the beginning, or anywhere, during transmission. The Idle pattern in the latter case is an alternating C601 and C610 sequence, until there is valid data available to transmit, or transmission has ended. Idle periods may begin with either of the two prescribed Idle symbols. The RX-side PHY shall remove Idle/Sync symbols from the stream and flag these events to the protocol. 空閒/同步逗號代碼字可以作為符號存在於傳輸突發的有效載荷中。這些符號要麼是根據協議的特定要求插入，要麼是在有傳輸請求但在傳輸開始時或傳輸過程中沒有有效數據可用時自動插入。在後一種情況下，空閒模式是一個交替的 C601 和 C610 序列，直到有有效數據可供傳輸，或傳輸已結束。空閒期間可以以兩個規定的空閒符號中的任一個開始。RX 端 PHY 應從流中移除空閒/同步符號並將這些事件標記給協議。
C.3.1.2 Protocol Marker Comma Symbol C.3.1.2 協議標記逗號符號
Comma symbol C600 (Protocol Marker) is allocated for use by protocols on top of the D-PHY. This symbol shall be inserted in the stream on request of the TX-side protocol and flagged by the receiving PHY to the RX-side protocol. 逗號符號 C600（協議標記）被分配給 D-PHY 上的協議使用。此符號應在 TX 端協議的要求下插入流中，並由接收 PHY 標記給 RX 端協議。
C.3.1.3 EoT Marker C.3.1.3 EoT 標記
Comma symbol C611 is allocated as the EoT Marker symbol. 逗號符號 C611 被分配為結束標記符號。
C.3.2 Details for HS Transmission C.3.2 HS 傳輸的詳細信息
C.3.2.1 SoT
The SoT procedure remains the same as the raw data D-PHY SoT. See Section 6.4.2. The SoT sequence itself is NOT encoded, but can be easily recognized. SoT 程序與原始數據 D-PHY SoT 相同。請參見第 6.4.2 節。SoT 序列本身並未編碼，但可以輕易識別。
The first bit of the first transmitted code symbol of a burst shall be aligned with the rising edge of the DDR clock. 第一個突發傳輸的代碼符號的第一位應與 DDR 時鐘的上升沿對齊。
C.3.2.2 HS Transmission Payload C.3.2.2 HS 傳輸有效載荷
The transmitted burst shall consist of concatenated serialized 9-bit symbols as described in Section C.3.1. 傳輸的突發應由串接的序列化 9 位元符號組成，如 C.3.1 節所述。
The TX-side PHY can idle by sending the Idle sequences as described in Section C.3.1.1 TX 端 PHY 可以通過發送如 C.3.1.1 節所述的空閒序列來閒置。
C.3.2.3 EoT
The TX-side PHY shall insert an EoT marker symbol at the moment the request for HS transmission is withdrawn. The transmitter can pad additional bits after this EoT-Marker symbol before actually switching to LP mode (EoT sequence). TX 端的 PHY 應在高速度傳輸請求被撤回的時刻插入一個 EoT 標記符號。發射器可以在實際切換到低功耗模式（EoT 序列）之前，在這個 EoT 標記符號之後填充額外的位元。
The RX-side PHY shall remove the EoT-Marker symbol and any additional bits appearing after it. Note that with line coding, EoT-processing by backtracking on LP-11 detection to avoid (unreliable) non-payload bits on the PPI is no longer required as the EoT marker symbol notifies the RX-side PHY before the End-ofTransmission. RX 端的物理層應移除 EoT 標記符號及其後出現的任何附加位元。請注意，隨著行編碼，通過回溯 LP-11 檢測進行 EoT 處理以避免 PPI 上的（不可靠）非有效載荷位元不再需要，因為 EoT 標記符號在傳輸結束之前通知 RX 端物理層。
C.3.3 Details for LP Transmission C.3.3 LP 傳輸的詳細信息
C.3.3.1 SoT
The start of LP transmission is identical to basic D-PHY operation. LP 傳輸的開始與基本 D-PHY 操作相同。
C.3.3.2 LP Transmission Payload C.3.3.2 LP 傳輸有效載荷
The transmitted burst shall consist of concatenated serialized 9-bit symbols as described in Section C.3.1. 傳輸的突發應由串接的序列化 9 位元符號組成，如 C.3.1 節所述。
During LPDT, the TX-side PHY can idle in two ways: either it can send the Idle sequences as described in Section C.3.1.1 and implicitly provide a clock signal to the RX-side PHY, or it can pause the transmission by keeping the Lines at LP-00 (Space) for a certain period of time between bits, which interrupts the clock on the RX side, but minimizes power consumption. 在 LPDT 期間，TX 端 PHY 可以以兩種方式閒置：要麼它可以發送如 C.3.1.1 節所述的閒置序列，並隱式地向 RX 端 PHY 提供時鐘信號；要麼它可以通過在位元之間的某段時間內將線路保持在 LP-00（空格）來暫停傳輸，這會中斷 RX 端的時鐘，但最小化功耗。
C.3.3.3 EoT
The TX-side PHY shall insert an EoT marker symbol at the moment the request for LP transmission is withdrawn. The TX-side PHY can pad additional (spaced-one-hot) bits after the EoT-Marker symbol before actually ending the transmission by switching via Mark to Stop state (End of LPDT procedure). TX 端 PHY 應在撤回 LP 傳輸請求的時刻插入 EoT 標記符號。TX 端 PHY 可以在實際結束傳輸之前，在 EoT 標記符號後填充額外的（間隔一熱）位，通過切換到停止狀態（LPDT 程序結束）來結束傳輸。
The RX-side PHY shall remove the EoT-marker symbol and any additional bits appearing after it. RX 端的 PHY 應移除 EoT 標記符號及其後出現的任何附加位元。
C. 4 Error Signaling C. 4 錯誤信號
The usage of a line code scheme enables the detection of many signaling errors. These errors include: 使用行碼方案可以檢測許多信號錯誤。這些錯誤包括：
Non-existing code words 不存在的代碼詞
Non-aligned Comma symbols 非對齊逗號符號
EoT detection without detection of EoT-Marker 未檢測 EoT 標記的 EoT 檢測
Detection and flagging of errors is not required, but may help the protocol to recover faster from an error situation. 檢測和標記錯誤不是必需的，但可能有助於協議更快地從錯誤情況中恢復。
C. 5 Extended PPI C. 5 擴展 PPI
The interface to the protocol shall be extended with functional handles (TX) and flags (RX) to manage the usage of Comma symbols. Whenever necessary, the transmitting PHY can hold the data delivery from the protocol to the TX PHY with the TxReadyHS or TxReadyEsc signal. This is already provided for in the current PPI. 該協議的介面將擴展功能句柄（TX）和標誌（RX），以管理逗號符號的使用。每當需要時，發送 PHY 可以通過 TxReadyHS 或 TxReadyEsc 信號將數據傳遞從協議保持到 TX PHY。這在當前的 PPI 中已經提供。
The PPI shall be extended with a TX Valid signal for HS data transmission, TxValidHS. Encoded operation allows for Idling of the Link when there is no new valid data. If the transmitter is ready and the provided data is not valid, an Idle symbol shall be inserted into the stream. Note, contrary to the basic PHY PPI, the Valid signals for a coded PHY can be actively used to manage the data on both TX and RX sides. This arrangement provides more flexibility to the PHY and Protocol layers. For LPDT, this Valid signaling already exists in the PPI. Addition of TxValidHS signal eliminates the constraint in the PPI description for TxRequestHS that the “protocol always provides valid data”. PPI 將擴展為具有 TX Valid 信號的 HS 數據傳輸，TxValidHS。編碼操作允許在沒有新有效數據時閒置鏈路。如果發射器準備就緒且提供的數據無效，則應在流中插入一個閒置符號。請注意，與基本 PHY PPI 相反，編碼 PHY 的有效信號可以主動用於管理 TX 和 RX 兩側的數據。這種安排為 PHY 和協議層提供了更多的靈活性。對於 LPDT，這種有效信號已經存在於 PPI 中。添加 TxValidHS 信號消除了 PPI 描述中對 TxRequestHS 的約束，即“協議始終提供有效數據”。
On the RX side, errors may be flagged to the protocol in case unexpected sequences are observed. Although many different errors are detectable, it is not required that all these errors flags be implemented. The number of error flags implemented depends on the cost/benefit trade-off to be made by the implementer. These error features do not impact compliance of the D-PHY. The signals are mentioned here for informative purposes only. 在 RX 端，如果觀察到意外的序列，可能會將錯誤標記給協議。雖然可以檢測到許多不同的錯誤，但並不要求實現所有這些錯誤標記。實現的錯誤標記數量取決於實施者所做的成本/效益權衡。這些錯誤特徵不會影響 D-PHY 的合規性。這裡提到的信號僅供參考。
All control signals shall remain synchronous to the TxWordClk, or RxWordClk. The control signal clock frequency shall be equal to or greater than 1//(n**9)1 /(n * 9) of the serial bit rate, where nn is the data bus width in bytes. 所有控制信號應與 TxWordClk 或 RxWordClk 保持同步。控制信號的時鐘頻率應等於或大於 1//(n**9)1 /(n * 9) 的串行比特率，其中 {{1 }} 是數據總線的寬度（以字節為單位）。
Table 45 lists the additional signals for the PPI on top of the coding sub-layer (EPPI) for an 8-bit interface only. 表 45 列出了僅適用於 8 位介面的 PPI 除編碼子層 (EPPI) 之外的附加信號。
Table 45 Additional Signals for (Functional) PPI 表 45 附加信號 (功能) PPI
Symbol 符號
Dir
Categories 類別
Description 描述
TxProMarkerEsc
I
MXAX
(SXXA)
MXAX
(SXXA)| MXAX |
| :--- |
| (SXXA) |
功能把手，用於在 LPDT 的串行流中插入協議標記符號。有效高信號
Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal
Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| LPDT. |
| Active HIGH signal |
TxProMarkerHS
I
MXXX
(SRXX)
MXXX
(SRXX)| MXXX |
| :--- |
| (SRXX) |
功能手柄，用於在串行流中插入協議標記符號以進行 HS 傳輸。有效高信號
Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal
Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| HS transmission. |
| Active HIGH signal |
Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal
Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal| Functional handle for the protocol to hold on providing data to the PHY |
| :--- |
| without ending the HS transmission. In the case of a continued transmission |
| request without Valid data, the PHY coding layer inserts Idle symbols. |
| Active HIGH signal |
RxAlignErrorEsc
O
SXAX
(MXXA)
SXAX
(MXXA)| SXAX |
| :--- |
| (MXXA) |
標誌以指示在 LPDT 流中觀察到的逗號代碼未與假定的單詞邊界對齊。主動高信號（可選）
Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)
Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)| Flag to indicate that a Comma code has been observed in the LPDT stream |
| :--- |
| that was not aligned with the assumed word boundary. |
| Active HIGH signal (optional) |
Symbol Dir Categories Description
TxProMarkerEsc I "MXAX
(SXXA)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal"
TxProMarkerHS I "MXXX
(SRXX)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal"
TxValidHS I "MXXX
(SRXX)" "Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal"
RxAlignErrorEsc O "SXAX
(MXXA)" "Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)"| Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| TxProMarkerEsc | I | MXAX <br> (SXXA) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> LPDT. <br> Active HIGH signal |
| TxProMarkerHS | I | MXXX <br> (SRXX) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> HS transmission. <br> Active HIGH signal |
| TxValidHS | I | MXXX <br> (SRXX) | Functional handle for the protocol to hold on providing data to the PHY <br> without ending the HS transmission. In the case of a continued transmission <br> request without Valid data, the PHY coding layer inserts Idle symbols. <br> Active HIGH signal |
| RxAlignErrorEsc | O | SXAX <br> (MXXA) | Flag to indicate that a Comma code has been observed in the LPDT stream <br> that was not aligned with the assumed word boundary. <br> Active HIGH signal (optional) |
{:[" Flag to indicate that a Comma code has been observed during HS reception "],[" that was not aligned with the assumed word boundary. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received using LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received in HS mode. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Indication flag that Idle patterns are observed at the Lines during LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
(MRXX)
Symbol Dir Categories Description
RxAlignErrorHS O " SXXX
(MRXX) " " Flag to indicate that a Comma code has been observed during HS reception
that was not aligned with the assumed word boundary.
Active HIGH signal (optional) "
RxBadSymbolEsc O " SXAX
(MXXA) " " Flag to indicate that a non-existing symbol was received using LPDT.
Active HIGH signal (optional) "
RxBadSymbolHS O " SXXX
(MRXX) " " Flag to indicate that a non-existing symbol was received in HS mode.
Active HIGH signal (optional) "
RxEoTErrorEsc O " SXAX
(MXXA) " " Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleEsc O " SXXX
(MRXX) " " Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleHS O " SXAX
(MXXA) " " Indication flag that Idle patterns are observed at the Lines during LPDT.
Active HIGH signal (optional) "
(MRXX) | Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| RxAlignErrorHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxEoTErrorEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleEsc | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleHS | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| (MRXX) | | | |
(\left.\begin{array}{l}Indication flag that Idle patterns are observed at the Lines in HS mode. 在 HS 模式下，指示標誌顯示在行中觀察到閒置模式。
Active HIGH signal (optional)\end{array}\right]) Active HIGH signal (optional)
C. 6 Complete Code Set C. 6 完整代碼集
Table 46 Code Set (8b9b Line Coding) 表 46 代碼集 (8b9b 行編碼)
The list below includes those persons who participated in the Working Group that developed this Specification and who consented to appear on this list. 以下名單包括參與制定本規範的工作組成員，以及同意出現在此名單上的人員。
Ahmed F. Aboulella, Mixel, Inc. Bhupendra Ahuja, NVIDIA Mario Ackers, Toshiba Corporation
Giovanni Angelo, Freescale Semiconductor Radha Atukula, NVIDIA Changhoon Baek, Samsung Electronics, Co. Andrew Baldman, MIPI Alliance, Inc. Cedric Bertholom, STMicroelectronics Gerrit den Besten, NXP Semiconductor Ignatius Bezzam, Arasan Chip Systems, Inc. Thomas Blon, Silicon Line GmbH Mark Braun, Motorola Mobility, LLC George Brocklehurst, Mindspeed Technologies, Inc. Dominique Brunel, STMicroelectronics Thierry Campiche, LeCroy Corporation Mara Carvalho, Synopsys, Inc. Kuochin Chang, OmniVision Technologies, Inc. Min-Jie Chong, Keysight Technologies Inc. Laurent Claramond, STMicroelectronics Kirill Dimitrov, SanDisk Corporation Keyur Diwan, Tektronix, Inc Dan Draper, Mindspeed Technologies, Inc. Ken Drottar, Intel Corporation Mahmoud El-Banna, Mixel, Inc. Michael Fleischer-Reumann, Keysight Technologies Inc. 喬凡尼·安傑洛，Freescale Semiconductor 拉達·阿圖庫拉，NVIDIA 張洪白，三星電子公司 安德魯·巴爾德曼，MIPI Alliance, Inc. 塞德里克·貝爾托洛姆，STMicroelectronics 傑里特·登·貝斯滕，NXP Semiconductor 伊格納修斯·貝扎姆，Arasan Chip Systems, Inc. 托馬斯·布隆，Silicon Line GmbH 馬克·布勞恩，摩托羅拉流動性，LLC 喬治·布羅克赫斯特，Mindspeed Technologies, Inc. 多米尼克·布魩內爾，STMicroelectronics 蒂埃里·坎皮切，LeCroy Corporation 瑪拉·卡瓦略，Synopsys, Inc. 郭欽·張，OmniVision Technologies, Inc. 關敏杰，Keysight Technologies Inc. 洛朗·克拉拉蒙，STMicroelectronics 基里爾·迪米特羅夫，SanDisk Corporation 基尤爾·迪萬，Tektronix, Inc. 丹·德雷珀，Mindspeed Technologies, Inc. 肯·德羅塔，英特爾公司 馬哈茂德·艾爾-巴納，Mixel, Inc. 邁克爾·弗萊舍-羅伊曼，Keysight Technologies Inc.
Ralf Gaisbauer, Toshiba Corporation 拉爾夫·蓋斯鮑爾，東芝公司
Ajay Garg, Synopsys, Inc.
Joaquim Gomes, Synopsys, Inc. 喬基姆·戈梅斯，Synopsys, Inc.
Will Harris, Advanced Micro Devices, Inc. 威爾·哈里斯，超微半導體公司。
Frederic Hasbani, STMicroelectronics
Hiroaki Hayashi, Sony Corporation 林弘明，索尼公司
Michael Herz, BlackBerry Limited 邁克爾·赫茲，黑莓有限公司
Ols Hidri, Silicon Line GmbH
Ken Hunt, Micron Technology, Inc. 肯·亨特，美光科技公司。
Henrik Icking, Intel Corporation 亨利克·伊金，英特爾公司
SeungLi Kim, Samsung Electronics, Co. SeungLi Kim, 三星電子有限公司
Marcin Kowalewski, Synopsys, Inc.
Myoungbo Kwak, Samsung Electronics, Co.
Luke Lai, NVIDIA
Thomas Langer, Toshiba Corporation 托馬斯·朗格，東芝公司
Ricky Lau, ATI Technologies, Inc. 劉偉強，ATI 科技公司
Ed Liu, NVIDIA
Thomas Marik, BitifEye Digital Test Solutions GmbH 托馬斯·馬里克，比特眼數位測試解決方案有限公司
David Meltzer, Seiko Epson Corp. 大衛·梅爾策，精工愛普生公司。
Patrick Mone, Texas Instruments Incorporated 帕特里克·莫恩，德州儀器公司
Marcus Muller, Nokia Corporation 馬庫斯·穆勒，諾基亞公司
Raj Kumar Nagpal, Synopsys, Inc. 拉吉·庫馬爾·納格帕爾，Synopsys, Inc.
Akira Nakada, Seiko Epson Corp. 中田晃、精工愛普生公司
Long Nguyen, Mixel, Inc.
Jim Ohannes, National Semiconductor
Upneet Pannu, NVIDIA
Joao Pereira, Synopsys, Inc. 喬奧·佩雷拉，Synopsys, Inc.
Harold Perik, NXP Semiconductor 哈羅德·佩里克，NXP 半導體
Tim Pontius, NXP Semiconductor
Duane Quiet, Intel Corporation 杜安·奎特，英特爾公司
Parthasarathy Raju, Tektronix, Inc
Juha Rakkola, Nokia Corporation
Jim Rippie, IEEE-ISTO (staff) 吉姆·里皮，IEEE-ISTO（員工）
Ravindra Rudraraju, Intel Corporation 拉文德拉·魯德拉拉朱，英特爾公司
Victor Sanchez-Rico, BitifEye Digital Test Solutions GmbH
Jose Sarmento, Synopsys, Inc.
Roland Scherzinger, Keysight Technologies Inc.
DC Sessions, NXP Semiconductor
Sridhar Shashidharan, Arasan Chip Systems, Inc.
Sergio Silva, Synopsys Inc
Bill Simms, NVIDIA 比爾·西姆斯，NVIDIA
Vikas Sinha, Texas Instruments Incorporated Vikas Sinha, 德州儀器公司
Ian Jackson, Silicon Line GmbH Ahmed Shaban, Mixel, Inc.
James Jaussi, Intel Corporation 詹姆斯·贾西，英特爾公司
Tatsuya Sugioka, Sony Corporation
Ashraf Takla, Mixel, Inc.
Aravind Vijayakumar, Cadence Design Systems, Inc.
Peter Vinson, Texas Instruments Incorporated 彼得·文森，德州儀器公司
Martti Voutilainen, Nokia Corporation 馬爾蒂·沃蒂萊寧，諾基亞公司
Manuel Weber, Toshiba Corporation 曼努埃爾·韋伯，東芝公司
Heiner Wiese, Toshiba Corporation 海納·維塞，東芝公司
Dong Hyun Song, SK Hynix 董炫成，SK 海力士
Dale Stolitzka, Samsung Electronics, Co. Dale Stolitzka, 三星電子公司
George Wiley, Qualcomm Incorporated 喬治·威利，高通公司
Charles Wu, OmniVision Technologies, Inc. 查爾斯·吳，OmniVision Technologies, Inc.
Kunihiko Yamagishi, Toshiba Corporation 山岸邦彦，東芝公司
Seiji Yamamoto, Renesas Electronics Corporation 山本誠司，瑞薩電子公司
Yunfeng Zhuo, Intel Corporation 雲峰卓，英特爾公司
Christoph Zimmermann, Toshiba Corporation 克里斯托夫·齊默曼，東芝公司
