mipialliance

Specification for D-PHY ${}^{\text{SM}}$${}^{\text{SM }}$^("SM "){ }^{\text {SM }}
D-PHY ${}^{\text{SM}}$${}^{\text{SM }}$^("SM "){ }^{\text {SM }} 規範

NOTICE OF DISCLAIMER 免責聲明通知

Contents 內容

Figures 數字

Tables 表格

Release History 發行歷史

1 Introduction 1 介紹

1.1 Scope 1.1 範圍

• Explicit specification of signals of the clock generator unit. Of course, the D-PHY specification does implicitly require some minimum performance from the clock signals. Intentionally, only the behavior on the interface pins is constrained. Therefore, the clock generation unit is excluded from this specification, and will be a separate functional unit that provides the required clock signals to the D-PHY in order to meet the specification. This allows all kinds of implementation trade-offs as long as these do not violate this specification. More information can be found in Section 5.
  時鐘產生單元的信號明確規範。當然，D-PHY 規範隱含地要求時鐘信號具備某些最低性能。故意地，僅對介面引腳的行為進行約束。因此，時鐘產生單元不在此規範之內，將作為一個獨立的功能單元，為 D-PHY 提供所需的時鐘信號，以滿足規範。這允許各種實現上的權衡，只要這些不違反此規範。更多信息可以在第 5 節找到。
• Test modes, patterns, and configurations. Obviously testability is very important, but because the items to test are mostly application specific or implementation related, the specification of tests is deferred to either the higher layer specifications or the product specification. Furthermore MIPI D-PHY compliance testing is not included in this specification.
  測試模式、模式和配置。顯然，測試性非常重要，但因為要測試的項目大多是應用特定或實現相關的，因此測試的規範被推遲到更高層的規範或產品規範。此外，MIPI D-PHY 合規性測試不包括在此規範中。
• Procedure to resolve contention situations. The D-PHY contains several mechanisms to detect Link contention. However, certain contention situations can only be detected at higher levels and are therefore not included in this specification.
  解決爭用情況的程序。D-PHY 包含幾種檢測鏈路爭用的機制。然而，某些爭用情況只能在更高的層次上檢測到，因此未包含在本規範中。
• Ensure proper operation of a connection between different Lane Module types. There are several different Lane Module types to optimally support the different functional requirements of several applications. This means that next to some base-functionality there are optional features which can be included or excluded. This specification only ensures correct operation for a connection between matched Lane Modules types, which means: Modules that support the same features and have complementary functionality. In case the two sides of the Lane are not the same type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the Lane Module(s) that the provided additional functionality does not corrupt operation. This can be easiest accomplished if the additional functionality can be disabled by other means independent of the MIPI D-PHY interface, such that the Lane Modules behave as if they were the same type.
  確保不同通道模組類型之間的連接正常運作。有幾種不同的通道模組類型，以最佳支持多個應用的不同功能需求。這意味著除了某些基本功能外，還有可選的功能可以包含或排除。本規範僅確保匹配的通道模組類型之間的連接正常運作，這意味著：支持相同功能並具有互補功能的模組。如果通道的兩側不是相同類型，並且這些模組應該正常運作，則應由通道模組的製造商確保所提供的附加功能不會損害運作。如果附加功能可以通過其他獨立於 MIPI D-PHY 介面的方式禁用，則可以最輕鬆地實現這一點，使通道模組的行為如同它們是相同類型。
• ESD protection level of the IO. The required level will depend on a particular application environment and product type.
  IO 的 ESD 保護級別。所需的級別將取決於特定的應用環境和產品類型。
• Exact Bit-Error-Rate (BER) value. The actual value of the achieved BER depends on the total system integration and the hostility of the environment. Therefore, it is impossible to specify a BER for individual parts of the Link. This specification allows for implementations with a BER $<{10}^{-12}$$<{10}^{-12}$< 10^(-12)<10^{-12}.
  精確的位元錯誤率（BER）值。實際達成的 BER 值取決於整體系統整合和環境的惡劣程度。因此，無法為鏈路的各個部分指定 BER。此規範允許實現 BER $<{10}^{-12}$$<{10}^{-12}$< 10^(-12)<10^{-12} 。
• Specification of the PHY-Protocol Interface. The D-PHY specification includes a PHY-Protocol Interface (PPI) annex that provides one possible solution for this interface. This annex is limited to the essential signals for normal operation in order to clarify the kind of signals needed at this
  PHY 協議介面的規範。D-PHY 規範包括一個 PHY 協議介面（PPI）附錄，提供了這個介面的一種可能解決方案。這個附錄僅限於正常操作所需的基本信號，以便澄清在此所需的信號類型。
  interface. For power reasons this interface will be internal for most applications. Practical implementations may be different without being inconsistent with the D-PHY specification.
  介面。出於功率原因，這個介面對於大多數應用將是內部的。實際實現可能會有所不同，但不會與 D-PHY 規範不一致。
• Implementations. This specification is intended to restrict the implementation as little as possible. Various sections of this specification use block diagrams or example circuits to illustrate the concept and are not in any way claimed to be the preferred or required implementation. Only the behavior on the D-PHY interface pins is normative.
  實現。此規範旨在盡可能少地限制實現。此規範的各個部分使用方塊圖或示例電路來說明概念，並不以任何方式聲稱是首選或必需的實現。只有 D-PHY 介面引腳上的行為是規範性的。

1.2 Purpose 1.2 目的

2 Terminology 2 術語

2.1 Use of Special Terms
2.1 特殊術語的使用

2.2 Definitions 2.2 定義

2.3 Abbreviations 2.3 縮寫

2.4 Acronyms 2.4 縮寫詞

3 References 3 參考文獻

4 D-PHY Overview 4 D-PHY 概述

4.1 Summary of PHY Functionality
4.1 PHY 功能摘要

4.2 Mandatory Functionality
4.2 強制功能

5 Architecture 5 建築學

5.1 Lane Modules 5.1 車道模組

A PHY configuration contains a Clock Lane Module and one or more Data Lane Modules. Each of these PHY Lane Modules communicates via two Lines to a complementary part at the other side of the Lane Interconnect.
一個 PHY 配置包含一個時鐘通道模組和一個或多個數據通道模組。這些 PHY 通道模組中的每一個通過兩條線與通道互連另一側的互補部分進行通信。

5.2 Master and Slave
5.2 主從

5.3 High Frequency Clock Generation
5.3 高頻時鐘生成

5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface
5.4 時鐘通道、數據通道和 PHY 協議介面

A complete Link contains, beside Lane Modules, a PHY Adapter Layer that ties all Lanes, the Clock Multiplier Unit, and the PHY Protocol Interface together. Figure 2 shows a PHY configuration example for a Link with two Data Lanes plus a separate Clock Multiplier Unit. The PHY Adapter Layer, though a component of a PHY, is not within the scope of this specification.
一個完整的連結除了通道模組外，還包含一個將所有通道、時鐘倍增單元和 PHY 協議介面連接在一起的 PHY 適配層。圖 2 顯示了一個具有兩個數據通道和一個單獨時鐘倍增單元的連結的 PHY 配置示例。雖然 PHY 適配層是 PHY 的一個組件，但不在本規範的範疇內。
The logical PHY-Protocol interface (PPI) for each individual Lane includes a set of signals to cover the functionality of that Lane. As shown in Figure 2, Clock signals may be shared for all Lanes. The reference clock and control signals for the Clock Multiplier Unit are not within the scope of this specification.
每個獨立通道的邏輯 PHY 協議介面（PPI）包括一組信號，以涵蓋該通道的功能。如圖 2 所示，時鐘信號可以在所有通道之間共享。時鐘倍增單元的參考時鐘和控制信號不在本規範的範疇內。

5.5 Selectable Lane Options
5.5 可選車道選項

• Bi-directional (featuring Turnaround and some Reverse communication functionality)
  雙向（具備回轉和某些反向通信功能）
• Unidirectional (without Turnaround or any kind of Reverse communication functionality)
  單向（不帶回轉或任何形式的反向通信功能）

• High-Speed Reverse data communication
  高速反向數據通信
• Low-Power Reverse Escape mode (including or excluding LPDT)
  低功耗反向逃逸模式（包括或不包括 LPDT）

• Single or Multiple Data Lanes
  單一或多個數據通道
• Bi-directional and/or Unidirectional Data Lane (per Lane)
  雙向和/或單向數據通道（每通道）
• Supported types of Reverse communication (per Lane)
  支持的反向通信類型（按通道）
• Functionality supported by Escape mode (for each direction per Lane)
  逃脫模式支持的功能（每條車道的每個方向）
• Data transmission can be with 8-bit raw data (default) or using 8b9b encoded symbol (see Annex C)
  數據傳輸可以使用 8 位原始數據（默認）或使用 8b9b 編碼符號（見附錄 C）

Figure 3 is a flow graph of the option selection process. Practical configuration examples can be found in Section 5.7.
圖 3 是選項選擇過程的流程圖。實際配置示例可以在第 5.7 節找到。

5.6 Lane Module Types
5.6 車道模組類型

Figure 4 shows a Universal Lane Module Diagram with a global overview of internal functionality of the CIL function. This Universal Module can be used for all Lane Types. The requirements for the ‘Control and Interface Logic’ (CIL) function depend on the Lane type and Lane side. Section 6 and Annex A implicitly specify the contents of the CIL function. The actual realization is left to the implementer.
圖 4 顯示了一個通用車道模組圖，提供了 CIL 功能內部功能的全球概覽。這個通用模組可以用於所有車道類型。對於“控制和介面邏輯”（CIL）功能的要求取決於車道類型和車道側。第 6 節和附錄 A 隱含地指定了 CIL 功能的內容。實際實現則留給實施者。

1. “Any” is any combination of one or more functions.
   “任何”是由一個或多個函數的任意組合。
2. Only valid for Data Lanes, means “F” or “R”.
   僅適用於數據通道，表示“F”或“R”。

5.6.1 Unidirectional Data Lane
5.6.1 單向數據通道

5.6.2 Bi-directional Data Lanes
5.6.2 雙向數據通道

5.6.2.1 Bi-directional Data Lane without High-Speed Reverse Communication
5.6.2.1 雙向數據通道無高速反向通信

5.6.2.2 Bi-directional Data Lane with High-Speed Reverse Communication
5.6.2.2 雙向數據通道與高速反向通信

5.6.3 Clock Lane 5.6.3 鐘路

5.7 Configurations 5.7 配置

In order to create an abstraction level, the Lane Modules are represented in this section by Lane Module Symbols. Figure 5 shows the syntax and meaning of symbols.
為了創建一個抽象層級，本節中用車道模組符號表示車道模組。圖 5 顯示了符號的語法和含義。

This 這個	Other Options 其他選項	Meaning 意義
C1CCCCCCC1		Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) 支持的高速數據傳輸方向（雙向或單向）
C1[I-][In][IH]1	C1C[I-][I-]1	Clock Lane 時鐘巷
$⟷$$⟷$longleftrightarrow\longleftrightarrow	$⟶$$⟶$longrightarrow\longrightarrow	Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) 支持的逃逸模式方向，排除 LPDT（雙向或僅前進）
$⊮⟶$$⊮⟶$⊮ longrightarrow\nVdash \longrightarrow	$⋙\ll$$⋙\ll$⋙≪\ggg \ll	支持的逃逸模式方向包括 LPDT（雙向、僅向前或僅向後） Supported Directions for Escape mode including LPDT (Bi-directional, Forward Only or Reverse Only) Supported Directions for Escape mode including LPDT (Bi-directional, Forward Only or Reverse Only)| Supported Directions for Escape mode including LPDT | | :--- | | (Bi-directional, Forward Only or Reverse Only) |
$\to$$\to$rarr\rightarrow	$\leftarrow$$\leftarrow$larr\leftarrow	時鐘方向（根據定義從主設備到從設備，必須指向與“僅時鐘通道”箭頭相同的方向） Clock Direction (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) Clock Direction (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)| Clock Direction | | :--- | | (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
		PPI: PHY-Protocol Interface PPI：PHY-協議介面

This Other Options Meaning C1CCCCCCC1 https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792 Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) C1[I-][In][IH]1 C1C[I-][I-]1 Clock Lane longleftrightarrow longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) ⊮ longrightarrow ⋙≪ "Supported Directions for Escape mode including LPDT (Bi-directional, Forward Only or Reverse Only)" rarr larr "Clock Direction (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)" https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607 PPI: PHY-Protocol Interface| This | Other Options | Meaning | | :---: | :---: | :---: | | <smiles>C1CCCCCCC1</smiles> |  | Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) | | <smiles>C1[I-][In][IH]1</smiles> | <smiles>C1C[I-][I-]1</smiles> | Clock Lane | | $\longleftrightarrow$ | $\longrightarrow$ | Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) | | $\nVdash \longrightarrow$ | $\ggg \ll$ | Supported Directions for Escape mode including LPDT <br> (Bi-directional, Forward Only or Reverse Only) | | $\rightarrow$ | $\leftarrow$ | Clock Direction <br> (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) | |  | | PPI: PHY-Protocol Interface |

For multiple Data Lanes a large variety of configurations is possible. Figure 6 shows an overview of symbolic representations for different Lane types. The acronyms mentioned for each Lane type represent the functionality of each module in a short way. This also sets the requirements for the CIL function inside each Module.
對於多個數據通道，可以有多種配置。圖 6 顯示了不同通道類型的符號表示概述。提到的每個通道類型的縮寫簡要表示了每個模塊的功能。這也設置了每個模塊內部 CIL 功能的要求。

5.7.1 Unidirectional Configurations
5.7.1 單向配置

5.7.1.1 PHY Configuration with a Single Data Lane
5.7.1.1 單數據通道的 PHY 配置

This configuration includes one Clock Lane and one Unidirectional Data Lane from Master to Slave. Communication is therefore only possible in the Forward direction. Figure 7 shows an example configuration without LPDT. This configuration requires four interconnect signal wires.
此配置包括一個時鐘通道和一個單向數據通道，從主設備到從設備。因此，通信僅能在前向方向進行。圖 7 顯示了一個不包含 LPDT 的示例配置。此配置需要四條互連信號線。

5.7.1.2 PHY Configuration with Multiple Data Lanes
5.7.1.2 多數據通道的 PHY 配置

This configuration includes one Clock Lane and multiple Unidirectional Data Lanes from Master to Slave. Bandwidth is extended, but communication is only possible in the Forward direction. The PHY specification does not require all Data Lanes to be active simultaneously. In fact, the Protocol layer controls all Data Lanes individually. Figure 8 shows an example of this configuration for three Data Lanes. If N is the number of Data Lanes, this configuration requires $2\ast (\mathrm{N}+1)$$2\ast (\mathrm{N}+1)$2**(N+1)2 *(\mathrm{~N}+1) interconnect wires.
此配置包括一個時鐘通道和多個從主設備到從設備的單向數據通道。帶寬得以擴展，但通信僅能在前向方向進行。PHY 規範並不要求所有數據通道同時處於活動狀態。事實上，協議層單獨控制所有數據通道。圖 8 顯示了三個數據通道的此配置示例。如果 N 是數據通道的數量，則此配置需要 $2\ast (\mathrm{N}+1)$$2\ast (\mathrm{N}+1)$2**(N+1)2 *(\mathrm{~N}+1) 互連線。

5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes)
5.7.1.3 雙簡單路徑（雙向單向車道）

This case is the same as two independent (dual), unidirectional (simplex) Links: one for each direction. Each direction has its own Clock Lane and may contain either a single, or multiple, Data Lanes. Please note that the Master and Slave side for the two different directions are opposite. The PHY configuration for each
此案例與兩個獨立的（雙向）單向（簡單）鏈路相同：每個方向各有一個。每個方向都有自己的時鐘通道，並且可以包含單個或多個數據通道。請注意，兩個不同方向的主端和從端是相對的。每個的 PHY 配置
direction shall comply with the D-PHY specifications. As both directions are conceptually independent, the bit rates for each direction do not have to match. However, for practical implementations, it is attractive to match rates and share some internal signals as long as both Links fulfill all specifications externally. Figure 9 shows an example of this dual PHY configuration.
方向應遵循 D-PHY 規範。由於兩個方向在概念上是獨立的，因此每個方向的比特率不必匹配。然而，對於實際實現，匹配速率並共享一些內部信號是有吸引力的，只要兩個鏈路在外部滿足所有規範。圖 9 顯示了這種雙 PHY 配置的示例。

5.7.2 Bi-Directional Half-Duplex Configurations
5.7.2 雙向半雙工配置

5.7.2.1 PHY Configurations with a Single Data Lane
5.7.2.1 單數據通道的 PHY 配置

This configuration includes one Clock Lane and one of any kind of bi-directional Data Lane. This allows time-multiplexed data traffic in both Forward and Reverse directions. Figure 10 shows this configuration with a Data Lane that supports both High-Speed and Escape (without LPDT) communication in both directions. Other possibilities are that only one type of reverse communication is supported or LPDT is also included in one or both directions. All these configurations require four interconnect wires.
此配置包括一個時鐘通道和一個任意類型的雙向數據通道。這允許在前向和反向方向上進行時間多路復用的數據流量。圖 10 顯示了此配置，其中數據通道支持雙向的高速和逃逸（不帶 LPDT）通信。其他可能性是僅支持一種類型的反向通信，或在一個或兩個方向上也包括 LPDT。所有這些配置都需要四根互連線。

5.7.2.2 PHY Configurations with Multiple Data Lanes
5.7.2.2 多數據通道的 PHY 配置

This configuration includes one Clock Lane and multiple bi-directional Data Lanes. Communication is possible in both the Forward and Reverse direction for each individual Lane. The maximum available bandwidth scales with the number of Lanes for each direction. The PHY specification does not require all Data Lanes to be active simultaneously or even to be operating in the same direction. In fact, the Protocol layer controls all Data Lanes individually. Figure 11 shows an example configuration with two Data Lanes. If N is the number of Data Lanes, this configuration requires $2\ast (\mathrm{N}+1)$$2\ast (\mathrm{N}+1)$2**(N+1)2 *(\mathrm{~N}+1) interconnect wires.
此配置包括一個時鐘通道和多個雙向數據通道。每個通道都可以在前向和反向方向上進行通信。每個方向的最大可用帶寬隨通道數量的增加而增加。PHY 規範不要求所有數據通道同時處於活動狀態，甚至不要求它們在相同方向上運行。事實上，協議層單獨控制所有數據通道。圖 11 顯示了具有兩個數據通道的示例配置。如果 N 是數據通道的數量，則此配置需要 $2\ast (\mathrm{N}+1)$$2\ast (\mathrm{N}+1)$2**(N+1)2 *(\mathrm{~N}+1) 互連線。

5.7.3 Mixed Data Lane Configurations
5.7.3 混合數據通道配置

Instead of using only one Data Lane type, PHY configurations may combine different unidirectional and bidirectional Data Lane types. Figure 12 shows an example configuration with one bi-directional and one unidirectional Data Lane, both without LPDT.
除了使用單一的數據通道類型外，PHY 配置可以結合不同的單向和雙向數據通道類型。圖 12 顯示了一個配置示例，其中包含一個雙向和一個單向數據通道，兩者均不使用 LPDT。

6 Global Operation 6 全球運營

6.1 Transmission Data Structure
6.1 傳輸數據結構

6.1.1 Data Units 6.1.1 數據單位

6.1.2 Bit order, Serialization, and De-Serialization
6.1.2 位元順序、序列化和反序列化

6.1.3 Encoding and Decoding
6.1.3 編碼與解碼

6.1.4 Data Buffering 6.1.4 數據緩衝

6.2 Lane States and Line Levels
6.2 車道狀態和線級

1. During High-Speed transmission the Low-Power Receivers observe LP-00 on the Lines.
   在高速傳輸期間，低功耗接收器在信號線上觀察到 LP-00。
2. If LP-11 occurs during Escape mode the Lane returns to Stop state (Control Mode LP-11).
   如果在逃生模式下發生 LP-11，車道將返回停止狀態（控制模式 LP-11）。

6.3 Operating Modes: Control, High-Speed, and Escape
6.3 操作模式：控制、高速和逃逸

6.4 High-Speed Data Transmission
6.4 高速數據傳輸

6.4.1 Burst Payload Data
6.4.1 突發有效載荷數據

6.4.2 Start-of-Transmission
6.4.2 傳輸開始

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6.4.3 End-of-Transmission
6.4.3 傳輸結束

6.4.4 HS Data Transmission Burst
6.4.4 HS 數據傳輸突發

Figure 14 shows the sequence of events during the transmission of a Data Burst. Transmission can be started and ended independently for any Lane by the protocol. However, for most applications the Lanes will start synchronously but may end at different times due to an unequal amount of transmitted bytes per Lane. The handshake with the protocol-layer is described in Annex A.
圖 14 顯示了數據突發傳輸過程中的事件序列。根據協議，任何通道的傳輸可以獨立開始和結束。然而，對於大多數應用來說，通道將同步開始，但由於每個通道傳輸的字節數不等，可能會在不同的時間結束。與協議層的握手在附錄 A 中描述。

Figure 14 High-Speed Data Transmission in Bursts
圖 14 高速數據突發傳輸
Figure 15 shows the state machine for High-Speed data transmission that is described in Table 5.
圖 15 顯示了表 5 中描述的高速數據傳輸的狀態機。

6.5 Bi-directional Data Lane Turnaround
6.5 雙向數據通道轉換