by 通过

Thesis presented in partial fulfilment of the requirements for the degree Master of Science in Engineering at the University of Stellenbosch
提交给斯泰伦博斯大学科学工程硕士学位部分要求的论文

Department of Electrical and Electronic Engineering
电子与信息工程系

University of Stellenbosch
斯坦陵布什大学

Private Bag X1, 7602 Matieland, South Africa
私人信箱 X1，7602 马蒂兰德，南非

Supervisor: Prof H. du T. Mouton
指导教师：胡德图·莫顿教授

Co-supervisor: B. Putzeys
联合导师：B. Putzeys

By submitting this thesis electronically, I declare that the entirety of the work contained therein is my own, original work, that I am the sole author thereof (save to the extent explicitly otherwise stated), that reproduction and publication thereof by Stellenbosch University will not infringe any third party rights and that I have not previously in its entirety or in part submitted it for obtaining any qualification.
通过电子方式提交此论文，我声明其中的全部工作是我自己的原创工作，我是该工作的唯一作者（除非另有明确说明），Stellenbosch 大学的复制和发表不会侵犯任何第三方权利，且我之前并未将其整体或部分提交以获得任何资格。

March 2012 三月 2012 年

Copyright (C) 2012 Stellenbosch University
版权所有 © 2012 斯特伦堡大学

All rights reserved. 版权所有。

The class-D audio power amplifier has found widespread use in both the consumer and professional audio industry for one reason: efficiency. A higher efficiency leads to a smaller and cheaper design, and in the case of mobile devices, a longer battery life.
类-D 音频功率放大器在消费和专业音频行业得到了广泛的应用，原因只有一个：效率。更高的效率导致了更小、更便宜的设计，对于移动设备而言，这意味着更长的电池寿命。

Unfortunately, the basic class-D amplifier has some serious drawbacks. These include high distortion levels, a load dependent frequency response and the potential to radiate EMI.
不幸的是，基本的类-D 放大器有一些严重的缺点。这些包括高失真水平，负载依赖的频率响应和可能辐射 EMI 的风险。
Except for EMI, the aforementioned issues can be mitigated by the proper implementation of global negative feedback. Negative feedback also has the potential to indirectly reduce EMI, since the timing requirements of the output devices can be relaxed.
除了 EMI 外，上述问题可以通过正确实施全球负反馈来缓解。负反馈还有可能间接减少 EMI，因为输出设备的时间要求可以得到放松。

This thesis discusses the design of a clocked analogue controlled pulse-width modulated class-D audio amplifier with global negative feedback. The analogue control loop is converted to the z-domain by modeling the PWM comparator as a sampling operation.
本论文讨论了设计一个带有全球负反馈的时钟控制模拟控制脉冲宽度调制类-D 音频放大器的方案。模拟控制回路通过将 PWM 比较器建模为采样操作转换到 z 域。
A method is implemented that improves clip recovery and ensures stability during over-modulation. Loop gain is shaped to provide a high gain across the audio band, and ripple compensation is implemented to minimize the negative effect of ripple feedback.
实现了一种方法，该方法提高了剪辑恢复性能并确保了在过调制期间的稳定性。通过塑造环路增益来提供音频频带内的高增益，并实施了振铃补偿以最小化振铃反馈的负面影响。
Experimental results are presented.
实验结果呈现如下。

Die klas-D klankversterker geniet wydverspreide gebruik in beide die verbruiker en professionele oudio industrie vir een rede: benuttingsgraad. 'n Hoër benuttingsgraad lei tot 'n kleiner en goedkoper ontwerp, en in die geval van draagbare toestelle, tot langer batterylewe.
D 类音频放大器广泛应用于消费和专业音频行业，原因在于其利用率。更高的利用率导致更小、更经济的设计，对于便携式设备而言，这意味着更长的电池寿命。

Ongelukkig het die basiese klas-D klankversterker ernstige tekortkominge, naamlik hoë distorsievlakke, 'n lasafhanklike frekwensierespons en die vermoë om EMI te genereer.
不幸的是，基本的类 D 音频放大器存在严重不足，包括高失真水平、频率响应的依赖性和产生电磁干扰的能力。
Behalwe vir EMI kan hierdie kwessies deur die korrekte toepassing van globale negatiewe terugvoer aangespreek word. Negatiewe terugvoer het ook die potensiaal om EMI indirek te verminder, aangesien die tydvereistes van die skakel stadium verlaag kan word.
为了 EMI，可以通过正确应用全球负反馈来解决这些问题。负反馈还有潜力间接减少 EMI，因为切换阶段的时间要求可以降低。

Hierdie tesis bespreek die ontwerp van 'n geklokte analoog-beheerde pulswydte-modulerende klas-D klankversterker met globale negatiewe terugvoer. Die analoogbeheerlus word omgeskakel na die z-vlak deur die PWM vlakvergelyker as 'n monster operasie te modelleer.
这篇论文讨论了一种全球负反馈控制的脉冲宽度调制类-D 音频放大器的设计，该放大器具有可切换的模拟控制级。模拟控制级通过将 PWM 平面模拟器作为操作放大器模型来切换到 z 平面。
'n Metode word geïmplementeer wat die stabiliteit van die lus verseker tydens oormodulasie. Die lusaanwins word gevorm om 'n hoë aanwins in die oudioband te verseker en riffelkompensasie word geïmplementeer om die negatiewe effek van terugvoerriffel teen te werk.
实施了一种方法，以确保在过模数转换期间环路的稳定性。环路增益形成以确保音频带中的高增益，并实施折返补偿以抵消反馈折返的负面影响。
Eksperimentele resultate word voorgelê.
实验结果被呈现。

The author would like to thank the following people for their contribution towards this project:
作者想感谢以下人员为本项目做出的贡献：

Declaration ..... i 声明 ..... i
Abstract ..... ii 摘要... ii
Uittreksel ..... iii 摘要 iii
Acknowledgements ..... iv
致谢 ..... iv
Contents ..... v 内容 ...... v
Nomenclature ..... viii 名词术语 ...... viii
List of Figures ..... x
目录插图 ...... x
List of Tables ..... xiv
目录中的表格......xiv
1 Introduction ..... 1
1 引言 ..... 1
1.1 Background ..... 1
1.1 背景 ..... 1
1.2 Thesis Objectives ..... 4
1.2 论文目标......4
1.3 Thesis Outline ..... 5
1.3 论文大纲 ... 5
2 Literature Review ..... 6
2 文献综述......6
2.1 The Harmonics of Ideal PWM ..... 6
2.1 理想 PWM 的谐波分析......6
2.2 Class-D Distortion Mechanisms ..... 7
2.2 类-D 失真机制......7
2.3 Discrete-Time Modelling of Continuous-Time Pulse-Width Modulator Loops ..... 13
2.3 离散时间建模连续时间脉冲宽度调制回路......13
2.4 Ripple Compensation ..... 17
2.4 溢流补偿......17
2.5 Stabilising a High-Order Modulator Under Overload Conditions ..... 20
2.5 在过载条件下稳定高阶调制器......20
2.6 Contribution to Existing Literature ..... 23
2.6 对现有文献的贡献......23
3 Output Stage Design ..... 25
3 输出阶段设计......25
3.1 Introduction ..... 25
3.1 引言 ..... 25
3.2 Overview ..... 25
3.2 概览......25
3.3 Gate Drive Circuitry ..... 27
3.3 门驱动电路......27
3.4 MOSFET Power Loss ..... 33
3.4 MOSFET 功率损耗 ..... 33
3.5 Heat-sink Design ..... 38
3.5 散热器设计 ..... 38
3.6 Snubber Design ..... 38
3.6 阻尼器设计......38
3.7 Demodulation Filter ..... 39
3.7 解调滤波器......39
3.8 Circuit Board Layout ..... 41
3.8 电路板布局......41
3.9 Adjustments ..... 42
3.9 调整......42
3.10 Open Loop Measurements ..... 44
3.10 开环测量......44
3.11 Summary ..... 48
3.11 总结......48
4 Carrier Generator ..... 50
4 信道生成器......50
4.1 Introduction ..... 50
4.1 引言 ..... 50
4.2 FPGA ..... 51
4.2 FPGA...... 51
4.3 DAC ..... 51
4.4 Power Distribution ..... 54
4.4 电源分配......54
4.5 Carrier Data Generation ..... 54
4.5 承载数据生成......54
4.6 Measurements ..... 55
4.6 测量......55
4.7 Summary ..... 55
4.7 总结......55
5 Developing the Control Loop Topology ..... 57
5 发展控制环路拓扑结构......57
5.1 Introduction ..... 57
5.1 引言 ..... 57
5.2 Building Blocks ..... 58
5.2 构建模块......58
5.3 The Complete Continuous-Time Control Loop ..... 62
5.3 完整的连续时间控制回路......62
5.4 Summary ..... 62
5.4 总结......62
6 Conversion to the Z-Domain ..... 64
6 转换至 Z 域......64
6.1 Introduction ..... 64
6.1 引言 ..... 64
6.2 The Impulse Invariant Transform ..... 64
6.2 冲击不变变换 .... 64
6.3 Calculating the Comparator Gain ..... 66
6.3 计算比较器增益......66
6.4 Embedding the Discrete-Time Comparator Model in the Control Loop ..... 69
6.4 在控制回路中嵌入离散时间比较器模型......69
6.5 Summary ..... 71
6.5 总结......71
7 Control Loop Design ..... 72
7 控制回路设计 ..... 72
7.1 Introduction ..... 72
7.1 引言 ..... 72
7.2 The Load and its Effect on Stability ..... 72
7.2 负载及其对稳定性的影响 ..... 72
7.3 Design Strategy ..... 75
设计策略......75
7.4 Selecting the Switching Frequency ..... 77
选择切换频率......77
7.5 The Optimal Loop ..... 77
7.5 最优循环......77
7.6 Estimation Filter ..... 81
7.6 估计滤波器......81
7.7 Scaling the Loop Filter Output Level ..... 82
7.7 调整环路滤波器输出级别......82
7.8 Analysis of the Control Loop Design ..... 84
7.8 控制回路设计的分析......84
7.9 Carrier Pre-Filter Transfer Function ..... 88
7.9 承载预滤器传输函数......88
7.10 Miscellaneous ..... 89
7.10 其他......89
7.11 Summary ..... 91
7.11 总结......91
8 Simulations ..... 92
8 模拟......92
8.1 Introduction ..... 92
8.1 引言 ..... 92
8.2 Simulink ..... 92
8.2 Simulink...... 92
8.3 SPICE ..... 95
8.4 Summary ..... 95
8.4 总结......95
9 Measurements ..... 97
9 测量......97
9.1 Introduction ..... 97
9.1 引言 ..... 97
9.2 Clipping Behaviour ..... 97
9.2 剪辑行为......97
9.3 Distortion ..... 97
9.3 扭曲......97
9.4 Spectral Analysis ..... 100
9.4 光谱分析......100
9.5 Frequency Response ..... 102
9.5 频率响应......102
9.6 Output Impedance ..... 104
9.6 输出阻抗......104
9.7 Power Supply Rejection Ratio ..... 105
9.7 电源拒绝比率......105
9.8 The Effect of Ripple Compensation ..... 106
9.8 滚动补偿的影响......106
9.9 Efficiency ..... 108
9.9 效率 ..... 108
9.10 Summary ..... 109
9.10 总结......109
10 Conclusions ..... 111
结论 10 ... 111
10.1 Overview ..... 111
10.1 概览 ..... 111
10.2 Improvements and Future Work ..... 112
10.2 改进和未来工作......112
10.3 General Conclusions ..... 113
10.3 总结 .... 113
Bibliography ..... 114 参考文献 ..... 114
Appendices ..... 118 附录 ..... 118
A Complete Circuit Schematics ..... 119
完整电路原理图......119

Abbreviations 缩写

alternating current  交流电

DAC digital to analogue converter
DAC 数字到模拟转换器

DC direct current 直流电

EMI electromagnetic interference
EMI 电磁干扰

ETF error transfer function
ETF 误差转移函数

FFT fast Fourier transform
快速傅里叶变换

FPGA field-programmable gate array
FPGA 可编程门阵列

I/O input/output 输入/输出

LUT lookup table 查找表 LUT

MOSFET metal-oxide-semiconductor field-effect transistor
MOSFET 金属氧化物半导体场效应晶体管

NSPWM naturally sampled pulse-width modulation
自然采样脉冲宽度调制

NSSSPWM naturally sampled single-sided pulse-width modulation
NSSSPWM 自然采样单边脉冲宽度调制

PAE pulse amplitude error
PAE 脉冲幅度误差

PCB printed circuit board
PCB 印刷电路板

PLL phase-locked loop PLL 频率锁定环

PSRR power supply rejection ratio
PSRR 电源抑制比

PTE pulse timing error
PTE 脉冲定时误差

PWM pulse-width modulation/modulator
PWM 脉冲宽度调制/调制器

RMS root mean square
RMS 根均方

STF signal transfer function
STF 信号传输函数

THD total harmonic distortion
总谐波失真

ETF The error transfer function is normally defined as the transfer function from the error source to the point directly after the error source. However, in this thesis the error transfer function is defined as the transfer function from the error source to the amplifier output.
ETF 错误转移函数通常定义为从错误源到错误源直接之后的点的转移函数。然而，在本论文中，错误转移函数定义为从错误源到放大器输出的转移函数。

Linear The term linear as used in this thesis may refer to three different concepts. Firstly, it may refer to the linearity of a system or process. A linear system is one that mathematically satisfies the superposition principle. In this sense PWM, for example, is non-linear.
线性 在本论文中使用的“线性”一词可能指三个不同的概念。首先，它可能指的是系统或过程的线性。线性系统是指在数学上满足叠加原理的系统。在这种意义上，例如 PWM 是非线性的。
Secondly, linear may refer to the "linear" operating region of a device. Thirdly, it may refer to something that is distortion free. The context in which the word is used should make its meaning self-explanatory.
其次，“线性”可能指的是设备的“线性”操作区域。第三，“线性”也可能指的是无失真现象。根据上下文，这个词的意思应该是显而易见的。

1.1 Basic class-D operation. ..... 2
1.1 基本的类-D 操作。...... 2
1.2 NSPWM waveforms for the converter of Figure 1.1. ..... 2
1.2 NSPWM 波形图 1.1 所示转换器的... 2
2.1 Calculated magnitude spectrum of ideal NSSSPWM. ..... 7
2.1 理想 NSSSPWM 的理想幅度谱......7
2.2 Simplified half-bridge inverter with current-source load. ..... 8
2.2 简化的一半桥式逆变器，带有电流源负载。..... 8
2.3 The effect of dead time on converter waveforms ..... 9
2.3 死时间对转换器波形的影响......9
2.4 Simplified half-bridge converter. ..... 11
2.4 简化的一半桥转换器. ..... 11
2.5 Idealised inductor and supply current waveforms. ..... 12
2.5 理想化电感器和电源电流波形。...... 12
2.6 Small-signal comparator model [1]. ..... 14
2.6 小信号比较器模型 [1]. ..... 14
2.7 Comparator waveforms [1]. ..... 14
2.7 比较器波形 [1] ..... 14
2.8 Comparator model embedded in a feedback loop. ..... 15
2.8 在反馈回路中嵌入比较器模型。...... 15
2.9 Discrete-time comparator model embedded in a feedback loop. ..... 15
2.9 离散时间比较器模型嵌入反馈回路中。...... 15
2.10 Simple PWM feedback loop with ripple compensation [2]. ..... 17
2.10 简单的 PWM 反馈回路，带有纹波补偿 [2] ..... 17
2.11 Ripple compensation waveforms for a first-order loop [2]. ..... 18
2.11 第一阶回路的 Ripple 补偿波形 [2] ..... 18
2.12 Three equivalent implementations of the ripple compensation technique. ..... 19
2.12 三种等效的移相补偿技术实现方法。...... 19
2.13 Generic output stage embedded in a feedback loop. ..... 21
2.13 通用输出阶段嵌入在反馈循环中。...... 21
2.14 Modified control loop with deviation detection filter. ..... 21
修改后的控制回路，带有偏差检测滤波器。......21
2.15 Output stage with passive lead network. ..... 22
2.15 输出阶段，被动负载网络。..... 22
2.16 Transistor-based loop filter saturation circuit. ..... 23
2.16 晶体管为基础的环路滤波器饱和电路。..... 23
3.1 Half-bridge topology. ..... 26
3.1 半桥拓扑结构. ..... 26
3.2 IRS20957S gate driver implementation. ..... 28
3.2 IRS20957S 门驱动器实现。...... 28
3.3 Low-side supply ..... 30
3.3 低侧 供电...... 30
3.4 IRFI4019H-117P gate charge versus gate-to-source voltage [3]. ..... 32
3.4 IRFI4019H-117P 栅极电荷与栅极-源极电压[3]......32
3.5 IRFI4019H-117P floating input voltage supply [3]. ..... 34
3.5 IRFI4019H-117P 浮输入电压供电 [3] ..... 34
3.6 Current through MOSFET with a sinusoidal current source as load. ..... 34
3.6 MOSFET 0#下的电流，作为负载的正弦波电流源。......34
3.7 Square of the current through MOSFET with a sinusoidal current source
3.7 MOSFET 通过正弦波电流源的电流的平方
as load. ..... 35
作为负载。......35
3.8 Current through MOSFET with a sinusoidal current source as load. ..... 36
3.8 MOSFET 在带有正弦电流源作为负载的情况下通过电流 。...... 36
3.9 Idealised MOSFET switching waveforms. ..... 36
3.9 理想化 MOSFET 开关波形。..... 36
LIST OF FIGURES ..... xi
目录插图 ...... xi
3.10 Calculated frequency response of the ideal demodulation filter. ..... 41
3.10 理想解调滤波器的计算频率响应。......41
3.11 Top layer of PCB. ..... 42
3.11 PCB 的顶层......42
3.12 Bottom layer of PCB. ..... 42
3.12 PCB 的底层......42
3.13 Calculated input impedance and magnitude response of the demodulation filter. ..... 44
3.13 计算了解调滤波器的输入阻抗和幅度响应。...... 44
3.14 Calculated demodulation filter input current ..... 44
3.14 计算解调滤波器输入电流......44
3.15 Oscilloscope measurement of the amplifier output signal. ..... 45
3.15 频率响应测量：放大器输出信号。......45
3.16 Oscilloscope measurement of switching node voltage with and without RC
3.16 无源 RC 时的示波器测量开关节点电压
snubber ..... 46 箝位器 ..... 46
3.17 Open loop THD+N versus output power ..... 47
3.17 开环 THD+N 与输出功率......47
3.18 FFT of distortion residue with 100 mW into . ..... 47
3.18 FFT of 100 mW distortion residue at . ..... 47
3.19 Open loop THD +N versus frequency for 10 W into and ..... 48
3.19 开环 THD+N 与频率的关系，功率为 10W，对应 和 ......48
3.20 Measured open loop frequency response for various output loads ..... 49
3.20 测量的开环频率响应对于各种输出负载......49
4.1 Block-diagram of the FPGA-based carrier generator. ..... 50
4.1 FPGA 基础的载波生成器的块图。......50
4.2 DAC output filter and buffer. ..... 52
4.2 DAC 输出滤波器和缓冲器......52
4.3 Filtered sawtooth signal for a 5th order Bessel and Butterworth filter ..... 53
4.3 五阶贝塞尔和巴特沃斯滤波器的过滤锯齿波信号......53
4.4 Frequency response of the DAC output filter. ..... 53
4.4 DAC 输出滤波器的频率响应。......53
4.5 Power distribution of the carrier generator board. ..... 54
4.5 载波生成板的功率分配. ..... 54
4.6 Measured carrier generator output for a sawtooth waveform. . ..... 56
4.6 测量锯齿波形的载波生成器输出。 . ..... 56
4.7 Measured carrier generator output for a sawtooth waveform. . ..... 56
4.7 测量锯齿波形的载波生成器输出。 . ..... 56
5.1 Basic control loop structure. ..... 57
5.1 基本控制回路结构. ..... 57
5.2 Shunt voltage feedback op-amp circuit and its balanced equivalent. ..... 58
5.2 并联电压反馈运算放大器电路及其平衡等效。......58
5.3 Output stage with passive lead compensation. ..... 58
5.3 输出阶段，带有被动负载补偿。......58
5.4 Control system block-diagram of output stage with passive compensation. ..... 59
5.4 输出阶段带有被动补偿的控制系统方块图。......59
5.5 Third-order integrating loop filter with local feedback and feed-forward sum-
第三级积分环路滤波器，带有局部反馈和前馈求和
mation. ..... 60 信息。......60
5.6 Single op-amp third-order integrating loop filter. ..... 60
5.6 单运放三级积分环路滤波器。......60
5.7 Control system block diagram of single op-amp third-order integrating loop
5.7 单运放第三阶积分环的控制系统的方块图
filter. ..... 61 过滤器。......61
5.8 Complete control system diagram ..... 62
5.8 完整的控制系统图 ..... 62
6.1 Block diagram illustration of the impulse invariant method ..... 64
6.1 冲击不变方法的块图说明 ..... 64
6.2 Continuous-time and discrete-time impulse responses. ..... 65
6.2 连续时间和离散时间的脉冲响应。..... 65
6.3 Block diagram for comparator gain calculation. ..... 67
6.3 比较器增益计算的块图. ..... 67
6.4 Continuous-time inner loop. ..... 69
6.4 连续时间内部循环。......69
6.5 Inner loop with sampling comparator model. ..... 69
6.5 内循环与采样比较器模型。..... 69
6.6 Continuous-time complete loop. ..... 70
6.6 连续时间完整环路. ..... 70
6.7 Complete loop with sampling comparator model ..... 70
6.7 完成采样比较器模型闭环......70
7.1 Simplified equivalent circuit of a moving-coil transducer. ..... 73
7.1 简化型动圈式转换器的电路图. ..... 73
7.2 Calculated impedance of the simplified loudspeaker and the first-order approx-
7.2 简化扬声器和一阶近似的计算阻抗
imation. ..... 74 信息。......74
7.3 Calculated demodulation filter transfer function. ..... 75
7.3 计算调制解调滤波器传输函数。......75
7.4 Output stage with single pole passive lead compensation ..... 78
7.4 输出阶段，单极被动领先补偿......78
7.5 Single op-amp third-order integrating loop filter. ..... 80
7.5 单运放第三阶积分环路滤波器。..... 80
7.6 Estimation filter stage circuit. ..... 81
7.6 估计滤波器阶段电路。...... 81
7.7 Calculated closed-loop transfer function of the inner loop. ..... 82
7.7 计算内部回路的闭环传递函数 ....... 82
7.8 General control system with estimation filter. ..... 82
7.8 一般控制系统与估计滤波器......82
7.9 Root locus of the inner control loop with an output load of . ..... 84
7.9 内部控制环路的根轨迹，输出负载为 ......84
7.10 Root locus of complete control loop with an output load of . ..... 85
7.10 完整控制回路在输出负载为 时的根轨迹.....85
7.11 Bode plot of for a and a propagation delay of ..... 85
7.11 Bode 图对于 的 和传播延迟 ......85
7.12 Bode plot of for a and a propagation delay of
7.12 Bode 图表示 在 和传播延迟下的值
. ..... 86
7.13 Gain margin and phase margin versus propagation delay for different loads ..... 86
7.13 不同负载下的增益裕度和相位裕度与传播延迟的关系......86
7.14 Calculated magnitude versus frequency of and for an
7.14 计算的幅度与频率对于 的 和
load. ..... 87 载荷。......87
7.15 Calculated closed-loop transfer function of the complete loop. ..... 88
7.15 计算完整闭环的闭环传递函数 ....... 88
7.16 Open-loop frequency response of the OPA1611 op-amp, and transfer functions
7.16 OPA1611 运算放大器的开环频率响应及其传输函数
and ..... 88
和 ..... 88
7.17 The LM306 comparator circuit ..... 90
7.17 LM306 比较器电路......90
7.18 Transistor-based loop filter saturation circuit. ..... 90
7.18 由晶体管为基础的回路滤波器饱和电路。..... 90
8.1 Magnitude spectrum of simulated amplifier output with only the inner loop
8.1 模拟放大器内部回路输出的幅度谱
active and with both loops active. ..... 93
活跃的，且两个循环都处于激活状态。......93
8.2 Magnitude spectrum of simulated amplifier output without ripple compensa-
8.2 模拟放大器输出无纹波补偿后的幅度谱
tion with only the inner loop active and with both loops active. ..... 93
与仅内循环激活和两个循环都激活的情况。......93
8.3 Simulated comparator gain with and without ripple compensation. ..... 94
8.3 模拟比较器增益，有和无纹波补偿。......94
8.4 Simulated comparator input reference signal without ripple compensation and
8.4 仿真比较器输入参考信号无纹波补偿
with ripple compensation. ..... 94
带有涟漪补偿。......94
8.5 Spice simulation of amplifier output and outer loop filter output during over-
8.5 超载情况下放大器输出和外环滤波器输出的香料模拟
modulation for . ..... 95
调制对于 ... 95
8.6 Spice simulation of amplifier output and outer loop filter output during over-
8.6 超载情况下放大器输出和外环滤波器输出的香料模拟
modulation for . ..... 96
调制对于 ......96
9.1 Oscilloscope measurements of the output of the amplifier and the output of
9.1 示波器测量放大器输出和放大器输出
the outer loop filter for . ..... 98
外循环滤波器对于 . ..... 98
9.2 Measured THD+N versus output power at 1 kHz . ..... 99
9.2 测量的 THD+N 与 1 kHz 时的输出功率......99
LIST OF FIGURES ..... xiii
插图列表 ..... xiii
9.3 Measured THD +N versus frequency at 10 W . ..... 100
9.3 测量的 THD+N 随频率变化在 10W 时......100
9.4 FFT of the open loop distortion residue with 10 W at 1 kHz into . ..... 101
9.4 开环失真残留的 FFT，1kHz 处输入 10W， . ..... 101
9.5 FFT of the distortion residue with the inner loop active with 10 W at 1 kHz
9.5 内环激活时，1 kHz 处 10 瓦的失真残留的 FFT
into . ..... 101
输入 . ..... 101
9.6 FFT of the distortion residue with both loops active with 10 W at 1 kHz into
9.6 带两个环路激活时，10 W 在 1 kHz 时的失真残留的 FFT
. ..... 102
9.7 Normalised FFT of the amplifier output with 18 kHz and 20 kHz input tones. ..... 103
9.7 正常化的 FFT 放大器输出，针对 18 kHz 和 20 kHz 输入音调。...... 103
9.8 Measured closed loop frequency response of the inner loop. ..... 103
9.8 内环的测量闭环频率响应。......103
9.9 Measured closed loop frequency response of the complete control loop. ..... 104
9.9 完整控制回路的测量闭环频率响应。......104
9.10 Output impedance measurement setup ..... 105
9.10 输出阻抗测量设置......105
9.11 Measured output impedance for PS1 and PS2. ..... 105
9.11 PS1 和 PS2 的测量输出阻抗......105
9.12 PSRR measurement setup. ..... 106
9.12 PSRR 测量设置。...... 106
9.13 Measured PSRR as a function of frequency. ..... 107
9.13 测量的 PSRR 作为频率的函数。...... 107
9.14 Measured THD+N versus frequency of PS1 different values of . ..... 108
9.14 测量的 THD+N 与 PS1 的不同值的频率......108
9.15 Measured THD +N versus frequency of PS2 for different values of . ..... 108
9.15 测量的 THD+N 与 PS2 的频率之间的关系，对于不同的 值......108
9.16 Measured THD +N versus frequency of PS 1 at 10 W with and
9.16 测量的 THD+N 与 PS 1 在 10W 功率下的频率关系，使用
..... 109
9.17 FFT of the distortion residue of PS1 with 10 W at 1 kHz into for
9.17 FFT 分析在 1 kHz 频率下，PS1 在 10 W 功率下的失真残留进入 的结果。
..... 109
A. 1 Output stage schematic. ..... 120
A. 1 输出阶段示意图。......120
A. 2 Control stage schematic (part one) ..... 121
A. 第二控制阶段示意图（一）......121
A. 3 Control stage schematic (part two) ..... 122
A. 3 控制阶段示意图（第二部分）......122
A. 4 FPGA carrier generator schematic (part one). ..... 123
A. 4 FPGA 载体生成器原理图（第一部分）......123
A. 5 FPGA carrier generator schematic (part two). ..... 124
A. 5 FPGA 载体生成器原理图（第二部分）......124
A. 6 FPGA carrier generator schematic (part three). ..... 125
A. 6 FPGA 载体生成器原理图（第三部分）......125
A. 7 FPGA carrier generator schematic (part four) ..... 126
A. 第四部分 7 FPGA 承载生成器原理图 ..... 126

3.1 IRFI4019H-117P characteristic values [3] ..... 27
3.1 IRFI4019H-117P 特性值 [3] ..... 27
3.2 Gate driver characteristic values [4]. ..... 28
3.2 门驱动特性值 [4]. ..... 28
3.3 Circuit and MOSFET parameter values. ..... 37
3.3 电路和 MOSFET 参数值。...... 37
4.1 Component values for the DAC post-filter and buffer. ..... 52
4.1 DAC 后滤波器和缓冲器的组件值......52
7.1 Component values for loudspeaker equivalent circuit. ..... 74
7.1 扬声器等效电路的元件值。..... 74
7.2 Optimisation constraints. ..... 77
7.2 最优化约束. ..... 77
7.3 Inner loop component and parameter values. ..... 79
7.3 内循环组件和参数值。...... 79
7.4 Complete loop component and parameter values. ..... 80
7.4 完成循环组件和参数值。......80

A class-D audio amplifier is an amplifier in which the power devices are, ideally, either fully on or fully of at any given time.
类-D 音频放大器是在其中，理想情况下，功率器件在任何给定时间要么完全开启要么完全关闭的放大器。
No power is dissipated in the ideal class-D power stage, since the output devices never have a current through and a voltage across them at the same time.
理想类-D 功率阶段中，没有任何能量被消耗，因为输出设备在同一时间既没有电流通过，也没有电压作用于其上。
This is in contrast to class-A, class-B and other linear amplifier topologies where there is a current through and a voltage across the output devices for significant periods of time.
这与 A 类、B 类和其他线性放大器拓扑结构形成对比，在这些结构中，输出设备在相当长的时间内有电流通过和电压存在。
Consequently, the efficiency of class-D amplifiers is superior to that of conventional linear amplifiers.
因此，D 类放大器的效率高于传统线性放大器。

In its simplest form a class-D amplifier is similar to a DC to AC converter. Figure 1.1 illustrates the basic principle for a half-bridge converter.
在最简单的形式中，类-D 放大器类似于直流到交流转换器。图 1.1 说明了半桥转换器的基本原理。
The MOSFET switches are switched complementary and the gate-signals of the switches are generated through pulse-width modulation (PWM).
MOSFET 开关是互补切换的，开关的门信号通过脉冲宽度调制（PWM）生成。
The simplest way to generate the PWM signal is by comparing a low-frequency reference signal to a high-frequency carrier waveform, typically a sawtooth or triangle wave.
生成 PWM 信号最简单的方法是将一个低频参考信号与一个高频载波波形，通常是锯齿波或三角波进行比较。
This is called naturally sampled PWM (NSPWM), since the switching transition occurs at the natural intersection of the reference and carrier waveforms. Figure 1.2 shows the waveforms associated with NSPWM for a sawtooth carrier and a sinusoidal reference signal . The amplitude of the carrier and the reference signal is and , respectively. The amplitude modulation index, normally referred to as just the modulation index, is defined as the ratio between the reference and carrier amplitude, or
这称为自然采样 PWM（NSPWM），因为开关转换发生在参考波形和载波波形的自然交点处。图 1.2 展示了 NSPWM 与 0#锯齿波载波和 1#正弦参考信号相关的波形。载波和参考信号的幅度分别为 和 。幅度调制指数，通常简称为调制指数，定义为参考信号和载波幅度之间的比率，或

The frequency of the carrier is also the switching frequency, denoted by . The ratio between the reference signal frequency and the carrier frequency is the frequency modulation index, or
载波的频率也是开关频率，表示为 。参考信号频率 与载波频率 之间的比率是频率调制指数，或者

The amplified PWM waveform contains an amplified version of the reference waveform (assuming ) as well as components at harmonics of the switching frequency and their associated side-bands [5]. The high-frequency components are removed from the signal by a demodulation filter, which is typically a passive LC low-pass filter.
放大 PWM 波形 包含参考波形（假设 ）的放大版本，以及开关频率的谐波及其相关的旁瓣[5]。通过通常的被动 LC 低通滤波器，高频成分从信号 中被移除。

The DC to AC inverter becomes an audio power amplifier when the sinusoidal reference is replaced by an audio signal. Both the modulation index and the frequency modulation index now varies with time.
直流到交流逆变器在将正弦波参考替换为音频信号时成为音频功率放大器。此时，调制度 和频率调制度 都随时间变化。
The switching frequency is chosen significantly higher than the maximum expected audio frequency (generally 20 kHz ) in order to minimise the magnitude of the carrier side-bands in the audio band and to allow proper attenuation of the high-frequency components by the filter.
切换频率被选择得远高于预期的最大音频频率（通常为 20 kHz），以最小化音频带内的载波旁瓣的幅度，并允许滤波器适当地衰减高频成分。

Figure 1.1: Basic class-D operation.
图 1.1：基本的类-D 操作。

Figure 1.2: NSPWM waveforms for the converter of Figure 1.1.
图 1.2：图 1.1 所示转换器的 NSPWM 波形。

Unfortunately, the basic class-D topology has some drawbacks. The basic class-D amplifier suffers from the following ailments that degrade sonic performance:
遗憾的是，基本的类-D 拓扑结构存在一些缺点。基本的类-D 放大器在声学性能方面存在以下问题：

The distortion in a class-D power stage is usually dominated by the non-linear PTE caused by dead time [5], which is required to prevent cross-conduction of the switching devices.
类-D 功率阶段中的失真通常由死时间[5]引起，死时间是为防止开关设备交叉导通而必需的，这种非线性 PTE 导致的失真。
Decreasing the dead time results in lower distortion, but decreases the efficiency due to increased shoot-through currents.
减少死时间导致失真降低，但因增加射穿电流而导致效率下降。

A class-D amplifier also has the potential to generate significant electromagnetic interference (EMI) due to the high rate of change of voltages and currents in the power switching stage.
类-D 放大器也有可能因功率开关阶段电压和电流变化率高而导致产生显著的电磁干扰（EMI）。
Radiated EMI can be reduced by reducing the switching speed of the power switches, but this in turn increases PTE related distortion.
辐射电磁干扰可以通过降低电源开关的切换速度来减少，但这反过来又会增加与 PTE 相关的失真。

The only way to effectively address all of the problems associated with a class-D power stage is through the implementation of global feedback error control.
要有效地解决与类-D 功率阶段相关的所有问题，唯一的方法是通过实施全局反馈误差控制。
If properly implemented, global negative feedback will mitigate power stage and output filter errors, improve power supply rejection and ensure a less load dependent frequency response.
如果正确实施，全球负反馈将减轻功率阶段和输出滤波器的误差，提高电源拒绝率并确保频率响应较少依赖于负载。
When feedback is applied we can tolerate a higher level of open loop distortion and consequently lower the switching speeds to reduce EMI. Furthermore, we can allow a longer dead time and thereby increase efficiency.
当提供反馈时，我们可以容忍更高的开环失真水平，从而降低开关速度以减少 EMI。此外，我们可以允许更长的死时间，从而提高效率。

It should be noted, however, that closing a feedback loop around a pulse-width modulator is not without its problems. The comparator behaves like a sampling operation [1] and high-frequency components that are fed back through the loop can alias into the audio band.
然而，需要注意的是，围绕脉冲宽度调制器关闭反馈回路并非没有问题。比较器行为类似于采样操作[1]，并通过回路反馈的高频成分可以混叠到音频带内。
This has been a topic of much research and recently several techniques to mitigate this effect have emerged .
这一直是研究的热点话题，最近已经出现了几种减轻这种影响的技术。

Closing a feedback loop around the output stage opens the door to another PWM scheme, which is self-oscillating modulation. A self-oscillating amplifier generates its own carrier by operating in a limit cycle [1]. This obviates the need for external carrier generator circuitry.
关闭反馈循环的输出阶段，打开了另一种 PWM 方案的大门，即自振荡调制。自振荡放大器通过在极限环中运行来生成自己的载波[1]。这消除了对外部载波生成电路的需求。
However, the switching frequency of a self-oscillating amplifier is a function of modulation index. In multichannel audio systems the difference in switching frequency between channels can lead to audible beat tones.
然而，自激放大器的切换频率是调制指数的函数。在多声道音频系统中，不同声道之间的切换频率差异可能导致可听的拍频音。

At this point we should make a distinction between digital and analogue with regard to class-D amplifiers. Class-D amplifiers are sometimes referred to as digital amplifiers.
到此为止，我们应该在类-D 放大器方面区分数字和模拟。有时类-D 放大器被称为数字放大器。

This term can be misleading since the power amplifier itself, consisting of the switching stage and demodulation filter, is inherently analogue and is delivering an analogue signal to the loudspeaker.
这个术语可能会误导人，因为它本身是由开关阶段和解调滤波器组成的功率放大器，本质上是模拟的，并向扬声器提供模拟信号。
We can make a distinction between analogue controlled and digitally controlled class-D amplifiers. In a digitally controlled class-D amplifier the gate signals of the switches are generated digitally.
我们可以将模拟控制和数字控制的类 D 放大器区分开。在数字控制的类 D 放大器中，开关的门信号是通过数字方式生成的。
Note that a digitally controlled class-D amplifier also suffers from all the non-idealities mentioned earlier, and as such will benefit greatly from global feedback.
请注意，数字控制的 D 类放大器也遭受之前提到的所有非理想性，因此将大大受益于全局反馈。
Global feedback can be implemented in a digitally controlled class-D amplifier through analogue-to-digital conversion of the amplifier output voltage.
全球反馈可以通过数字控制的类-D 放大器的输出电压的模数转换来实现。
Such a design can achieve very good performance, but performance is limited by the analogueto-digital converter in the feedback path [2].
这样的设计可以实现非常好的性能，但性能受到反馈路径中的模数转换器的限制 [2]。

The objective of this thesis is to design, simulate, build and measure a high-performance, analogue controlled, clocked (ie. not self-oscillating), class-D amplifier. This is a fairly general statement, but the following is specifically required:
本论文的目标是设计、模拟、构建并测量一个高性能、模拟控制、时钟驱动（即非自激振荡）的类 D 放大器。这是一个相当通用的陈述，但以下内容是具体要求：

In addition to the above, the measured results must be compared to theoretical expectations. In this context, high-performance refers to the audio performance of the amplifier and not the efficiency or EMI performance.
除了上述内容外，测量结果必须与理论预期进行比较。在此背景下，高性能指的是放大器的音频性能，而不是效率或电磁兼容性。
The primary research focus is on the control method and not the power converter itself.
主要研究重点是控制方法，而不是功率转换器本身。
Note that the performance of the control method is evaluated based on its ability to improve the performance of the amplifier compared to open loop class-D operation, and not on the absolute value of the closed-loop performance measurements.
请注意，控制方法的性能评估基于其相对于开环类-D 操作提高放大器性能的能力，而不是闭环性能测量的绝对值。

That being said, we would like the closed-loop amplifier to compare favourably with a high-performance linear amplifier. The following performance targets are set for the closed-loop amplifier:
既然如此，我们希望闭环放大器能够与高性能线性放大器相媲美。对于闭环放大器，我们设定了以下性能目标：

Chapter 2 discusses the literature that forms the foundation for the remainder of the thesis. This includes, among other topics, the discrete-time modelling of continuous-time PWM loops and ripple compensation.
第二章讨论了构成论文其余部分基础的文献。这包括但不限于离散时间建模连续时间 PWM 环路和纹波补偿等主题。

Chapter 3 covers the design of the class-D output stage, which includes the power switching stage and associated circuitry, and the demodulation filter. Measurements of the open loop class-D amplifier are presented.
第三章涵盖了类-D 输出级的设计，包括功率开关阶段和相关电路，以及解调滤波器。展示了开环类-D 放大器的测量结果。

Chapter 4 discusses the design of an FPGA-based carrier generator. Carrier data is generated off-line and stored in a lookup table in the FPGA. The data is then clocked to a high-speed digital-to-analogue converter.
第四章讨论了基于 FPGA 的载波生成器的设计。载波数据在离线状态下生成，并存储在 FPGA 中的查找表中。然后将数据时钟到高速数字到模拟转换器。

Chapter 5 concerns the development of the control loop topology. The analogue circuitry that is required to implement the control loop is discussed and the complete continuous-time loop is presented.
第五章讨论了控制环路拓扑的发展。实现了控制环路所需的模拟电路进行了讨论，并呈现了完整的连续时间环路。

In Chapter 6 the continuous-time control loop developed in Chapter 5 is converted to the z-domain through the impulse invariant transform. An expression fot the equivalent gain of the comparator is derived by means of Fourier series. Important transfer functions are presented.
第 6 章中，通过脉冲不变变换，将第 5 章中开发的连续时间控制回路转换到 z 域。通过傅里叶级数推导出比较器等效增益的表达式。重要传输函数被呈现。

Chapter 7 covers the detail design of the control loop. The load that the loudspeaker presents to the amplifier, and its effect on stability, is investigated. A control loop is designed that provides at least 50.8 dB rejection of output stage errors in the audio band.
第七章详细介绍了控制回路的设计。探讨了扬声器对放大器的负载及其对稳定性的影响。设计了一个控制回路，该回路在音频频带内至少可以抵消输出级错误 50.8 dB。

It should be noted that Chapter 5, Chapter 6 and Chapter 7 are very closely knit and essentially form one unit.
应指出，第五章、第六章和第七章内容紧密相连，本质上形成一个整体。

Chapter 8 presents simulation results of the control loop that is designed in the preceding chapters. The simulation results verify the correct operation of the control loop.
第八章呈现了前几章设计的控制回路的仿真结果。这些仿真结果验证了控制回路的正确运行。

Chapter 9 presents and discusses measurements of the complete amplifier. The measurements are compared to theoretical expectations. It is confirmed that the control method effectively mitigates the non-idealities of the open loop system.
第九章介绍了并讨论了完整放大器的测量。这些测量结果与理论预期进行了比较。确认了控制方法有效地减轻了开环系统的非理想性。

This thesis ends with a conclusion in Chapter 10. Recommendations for further research are also given.
本论文在第 10 章结束时得出结论。还提出了进一步研究的建议。

This chapter reviews the literature that forms the foundation of the remainder of the thesis.
本章回顾了构成论文其余部分基础的文献。

In [11] it is shown that an ideal naturally sampled single-sided pulse-width modulating (NSSSPWM) waveform that is generated by comparing a reference signal with a sawtooth carrier can be decomposed as the sum of three functions
在[11]中显示，通过将参考信号与锯齿波载波进行比较生成的理想自然采样单边脉宽调制（NSSSPWM）波形 可以分解为三个函数的和

where 在哪里

over the interval . The last term in (2.1.1) can be written in terms of its Fourier series expansion to obtain
在区间 上。等式(2.1.1)的最后一项可以通过其傅里叶级数展开来表示，从而得到

For the special case where , we can use the Jacobi-Anger identity
对于特殊情况 ，我们可以使用雅可比-安格恒等式

to rewrite (2.1.3) as
将（2.1.3）重写为

where is the 'th order Bessel function of the first kind [11]. Equation (2.1.5) is the well-known double Fourier series expression for a NSSSPWM waveform [12]. Equation (2.1.5) shows that the PWM waveform contains the following signal components:
其中 是第 阶第一类贝塞尔函数 [11]。式 (2.1.5) 是 NSSSPWM 波形的广为人知的双傅里叶级数表达式 [12]。式 (2.1.5) 显示 PWM 波形 包含以下信号成分：

Figure 2.1 shows the spectrum of with a 1 Hz reference signal for a modulation index of and a frequency modulation index of . It should be clear that, in ideal PWM, only the side-band components contribute to distortion in the audio band, provided that the switching frequency is outside the audio band. Increasing will reduce the magnitude of the side-band components in the audio band.
图 2.1 展示了在调制指数为 和频率调制指数为 时， 的 1 Hz 参考信号的频谱。应清楚，在理想 PWM 中，只要开关频率位于音频带之外，仅边带成分对音频带的失真做出贡献。增加 将减少音频带中的边带成分的幅度。

Figure 2.1: Calculated magnitude spectrum of ideal NSSSPWM for and .
图 2.1：理想 NSSSPWM 在 和 时的计算幅值谱。

Note that the side-bands in Figure 2.1 decay fairly rapidly. However, non-ideal effects like dead-time and finite switching times will cause the side-bands to decay less rapidly than for ideal PWM [5].
注意图 2.1 中的边带衰减相当迅速。然而，非理想效应如死时间以及有限的切换时间会导致边带的衰减速度比理想 PWM [5] 慢。

In an ideal NSPWM class-D amplifier output stage, the only contribution to distortion in the audio band is the carrier side-bands [5]. However, several distortion mechanisms are
在理想的 NSPWM 类-D 放大器输出阶段，音频带中的失真仅由载波旁瓣贡献 [5]。然而，存在几种失真机制
present in a practical, non-ideal, class-D amplifier. This section gives a brief overview of the distortion mechanisms present in a class-D amplifier.
在实用的、非理想状态下的类-D 放大器中存在。本节简要介绍了类-D 放大器中存在的失真机制。

As mentioned earlier, the switches in a class-D power stage are switched complementary. However, A MOSFET is not an ideal switch and cannot switch from the on to off state and vice versa instantaneously.
如前所述，类-D 功率阶段中的开关是互补切换的。然而，MOSFET 并不是一个理想的开关，不能瞬间从开状态切换到关状态，反之亦然。
For a small time the MOSFET will operate in its linear region, having both a current through it and a voltage across it. To prevent both switches conducting simultaneously during a switching transition, the modulator waits for a time after one switch is off before switching on the next switch. The time in which both switches are off is known as the dead time. Dead time leads to pulse-timing errors (PTEs), and is a major source of distortion in a class-D power stage.
源文本：对于一小段时间，MOSFET 将在其线性区域工作，既有电流通过它，也有电压在其上。为了避免在开关转换期间两个开关同时导通，调制器在其中一个开关关闭后等待时间 ，然后再开启下一个开关。两个开关都关闭的时间被称为死时间。死时间会导致脉冲定时错误（PTEs），并且是 D 类功率级中失真的主要来源。 翻译文本：

Figure 2.2 shows a simplified half-bridge inverter with ideal switches and , and ideal diodes and . Figure 2.3 shows the gate signals of the switches and the unfiltered output voltage . The ideal gate and output waveforms are shown in grey.
图 2.2 显示了一个带有理想开关 和 以及理想二极管 和 的简化半桥逆变器。图 2.3 显示了开关的门信号和未滤波的输出电压 。理想门和输出波形以灰色显示。

Figure 2.2: Simplified half-bridge inverter with current-source load.
图 2.2：带有电流源负载的简化半桥逆变器。

Consider the case when switches from off to on and from on to off. If , conducts during the dead time interval and the output voltage is , while the ideal output voltage at this time is . If conducts during the dead time interval and the output voltage is , which is the correct output voltage.
考虑当 从关切换到开， 从开切换到关的情况。如果 ， 在死时间间隔内导通，输出电压为 ，而此时的理想输出电压为 。如果 在死时间间隔内导通，输出电压为 ，这是正确的输出电压。

In a similar manner, when switches from on to off and from off to on the output voltage is correct when , and incorrect when .
类似地，当 从开切换到关， 从关切换到开时，输出电压正确，当 ；当 从关切换到开， 从开切换到关时，输出电压不正确，当 。

At small values of the inductor current changes polarity twice during a switching cycle and the effect of dead time is reduced to only a time delay of . At larger values of the inductor current polarity is primarily determined by the polarity of the reference signal and is distinctly positive or negative for several switching cycles at a time.
在 值较小时，电感电流在一个开关周期内改变极性两次，死时间的影响仅减少到 的时间延迟。在 值较大时，电感电流的极性主要由参考信号的极性决定，在一段时间内，电感电流的极性会明显为正或为负，同时存在多个开关周期。
The output voltage error now changes with the polarity of the reference signal, which results in distortion of the output waveform inside the audio band.
输出电压误差现在随参考信号的极性变化，导致音频带内的输出波形失真。

Figure 2.3: The effect of dead time on converter waveforms. Ideal waveforms are shown in grey.
图 2.3：死时间对转换器波形的影响。理想波形以灰色显示。

Viewed in isolation, dead time contributes only to odd harmonic distortion in the audio band. However, in [5] it was shown that introducing dead time also increases the magnitude of the side-band switching harmonics inside the audio band for larger values of . Distortion due to dead time increases for increasing values of . Also note that dead time distortion, and distortion due to PTEs in general, increase with an increase in switching frequency.
孤立地看，死时间仅对音频带内的奇次谐波失真有所贡献。然而，在[5]中显示，引入死时间也会在音频带内，对于 的较大值，增加边带切换谐波的幅度。随着 值的增加，死时间引起的失真也会增加。另外需要注意的是，死时间引起的失真，以及一般由 PTEs 引起的失真，随着开关频率的增加而增加。

The turn-on and turn-off delays of a MOSFET is a function of the current through the MOSFET [5]. Since the current changes with the reference signal these delays will manifest as PTEs. At low values of , when the current changes polarity twice during a switching cycle, the change in turn-on on turn-off delays is continuous. This continuous change in delays results in even and odd baseband harmonics that decay fairly rapidly with frequency. However, at larger values of when the inductor current is distinctly positive or negative for several switching cycles at a time, the change in delays is discontinuous. The baseband harmonics do not decay as rapidly as was the case with small values of , and results in a significantly higher level of distortion.
MOSFET 的开启和关闭延迟是 MOSFET 中电流的函数[5]。由于电流随参考信号变化，这些延迟会表现为 PTE。在 值较低时，当一个开关周期内电流极性变化两次时，开启和关闭延迟的变化是连续的。这种连续的变化导致了频率较快衰减的偶数和奇数基带谐波。然而，在 值较大时，当电感电流在一段时间内明显为正或负时，延迟的变化是不连续的。基带谐波的衰减速度不如 值较小时的情况快，导致失真水平显著提高。

As with dead time, the turn-on and turn-off delays also increase the magnitude of the side-band switching harmonics in the audio band at larger values of . Distortion
如同死时间一样，开关延迟也会在音频带宽中，随着 值的增大，增加副边带切换谐波的幅度。失真
increases for longer delay times.
增加随着延迟时间的延长。

Non-linear non-zero switching transitions affect distortion in a similar manner to turnon and turn-off delays [5].
非线性非零开关转换对失真的影响与开启和关断延迟以相同的方式影响。

In [5] it was shown that the ringing of the pulse output waveform due to circuit parasitics and reverse recovery leads to pulse amplitude errors (PAEs), but contributes negligible distortion compared to the PTEs mentioned above.
在[5]中显示，由于电路寄生效应和反向恢复导致的脉冲输出波形的振铃，会引起脉冲幅度误差（PAEs），但与上述 PTEs 相比，它造成的失真几乎可以忽略不计。
That being said, ringing of the pulse waveform increases radiated EMI and can therefore indirectly increase the distortion in an analogue modulator through self-pollution.
既然如此，脉冲波形的振铃会增加辐射的 EMI，并且因此可以通过自我污染间接增加模拟调制器中的失真。

The PTEs discussed above can be minimised by increasing the switching speed. However, increasing the switching speed results in higher values of and in the PWM waveform before the demodulation filter. This leads to increased radiated EMI, which can contaminate the signals at the comparator input in an analogue modulator. This can potentially lead to severe distortion of the output waveform, especially at larger values of . A decrease in open-loop distortion due to faster switching times is therefore partially offset by an increase in distortion due to self-pollution.
上述讨论的 PTEs 可以通过提高切换速度来最小化。然而，提高切换速度会导致 PWM 波形在解调滤波器之前 和 的值增加。这会导致辐射 EMI 增加，可能污染模拟调制器比较器输入的信号。这可能导致输出波形严重失真，尤其是在 较大时。因此，由于更快的切换时间导致的开环失真减少部分被自我污染导致的失真增加所抵消。

Note that in an amplifier with a digital modulator, self-pollution will contribute much less to open-loop distortion.
请注意，在带有数字调制器的放大器中，自污染对开环失真贡献要小得多。
Indeed, it was found that a power stage with little regard for EMI performance yielded good distortion measurements in a digital feedback design [2], but was almost completely useless in an analogue control loop.
确实，发现了一个不太考虑电磁干扰性能的功率阶段，在数字反馈设计中 [2] 提供了良好的失真测量值，但在模拟控制回路中几乎完全无用。
In an analogue modulator the EMI performance of the amplifier directly influences the audio performance.
在模拟调制器中，放大器的 EMI 性能直接影响音频性能。
Even though this design is an experimental system and does not officially have to pass any EMI standards, careful attention still has to be paid to EMI performance, if only to maximise the audio performance.
尽管这个设计是一个实验系统，不需要正式通过任何电磁干扰（EMI）标准，但在 EMI 性能方面仍然需要仔细关注，仅为了最大化音频性能。

In a half-bridge converter the situation can occur where there is a net flow of energy from the load back to a supply rail [13]. Consider the circuit of Figure 2.4. We assume that the filter capacitor is large enough that the output voltage is approximately constant over a switching cycle. Figure 2.5 (a) shows the idealised inductor and supply current waveforms for a duty cycle of over a single switching cycle. The average inductor current, and load current, is zero. Current flows to and from both sources, but the net energy transfer is zero.
在半桥转换器中，可能出现负载向供电轨回流能量的情况[13]。考虑图 2.4 中的电路。我们假设滤波电容 足够大，使得在开关周期内输出电压 大致保持恒定。图 2.5（a）展示了在单个开关周期内，占空比为 的理想电感和供电电流波形。平均电感电流和负载电流为零。电流流向和来自两个源，但总的能量传输为零。

Figure 2.4: Simplified half-bridge converter.
图 2.4：简化的一半桥转换器。

Figure 2.5 (b) shows the same waveforms for a duty cycle of . The average inductor current is now greater than zero and energy flows from the positive supply to the load. However, it is observed that there is also a net flow of energy into the negative voltage supply.
图 2.5（b）显示了占空比为 时的相同波形。平均电感电流现在大于零，能量从正电源流向负载。然而，观察到也有净能量流入负电压电源。
If the power supply has no way to absorb the energy, as is the case with a passive power supply and most linear supplies, the bus voltage will increase [13]. This is known as "bus pumping". The open-loop gain of the amplifier is proportional to the power supply voltage.
如果电源无法吸收能量，就像被动电源和大多数线性电源的情况一样，总线电压会增加 [13]。这被称为“总线泵送”。放大器的开环增益与电源电压成正比。
If bus pumping causes significant supply voltage fluctuations, this will lead to distortion. However, with a large storage capacitance in the power supply and a control loop that provides error rejection in the audio band the effect of supply pumping should be negligible.
如果公交车泵送导致显著的供电电压波动，这将导致失真。然而，如果电源中具有大量存储电容，并且控制回路在音频带内提供误差抵消，那么供电泵送的影响应该可以忽略不计。
This, of course, assumes that the program material does not contain significant power at very low frequencies.
当然，这假设程序材料在非常低的频率下不包含显著的功率。

In open-loop tests the effect of bus pumping should be kept in mind. Contrary to an ideal PWM modulator, in a practical amplifier it is unlikely that a carrier with no DC offset will result in a PWM output signal with no DC offset.
在开环测试中，应考虑到公共线泵送的影响。与理想的 PWM 调制器不同，在实际放大器中，不太可能得到没有直流偏置的载波，从而导致 PWM 输出信号也没有直流偏置。
This is due to the difference in turn-on and turn-off delay times between the top and bottom power switches.
这是由于上下电源开关的开启和关闭延迟时间不同所导致的。
In openloop tests the carrier should be tuned such that the switching stage output signal does not have a significant DC offset, otherwise the supply voltage will increase and the amplifier might get damaged.
在开环测试中，应调整载波，使得开关阶段的输出信号没有显著的直流偏置，否则供电电压将增加，放大器可能会受损。

The passive components of the demodulation filter are not ideal and can contribute to distortion. Due to the high frequency power signal that enters the demodulation filter, it is necessary to use a ferrite core inductor. Unfortunately a ferrite core is non-linear [14].
解调滤波器中的被动元件并非理想，可能会导致失真。由于进入解调滤波器的高频功率信号，需要使用铁氧体磁芯电感器。不幸的是，铁氧体磁芯是非线性的 [14]。
The inductor will become increasingly non-linear as the flux density in the core nears the saturation flux density of the core material.
电感器在磁芯中的磁通密度接近磁芯材料的饱和磁通密度时，将变得越来越非线性。

It should be noted that the physical design of the output filter will also have an influence on distortion. The parasitic parallel capacitance of the filter inductor and the parasitic series inductance of the filter capacitor will cause the filter to behave like a high-
应注意到，输出滤波器的物理设计也会影响失真。滤波电感的寄生并联电容和滤波电容的寄生串联电感会使滤波器表现出高-

(a)

(b)

Figure 2.5: Idealised inductor and supply current waveforms for (a) and (b) .
图 2.5：理想化电感器和电源电流波形，(a) 和 (b) 。

pass filter at higher frequencies. If these parasitics are not minimised, the edges of the PWM waveform will show up as voltage spikes in the amplifier output waveform. These high-frequency spikes will radiate off attached cables, leading to increased self-pollution.
在较高频率下通过滤波器。如果这些寄生效应没有最小化，PWM 波形的边缘将在放大器输出波形中表现为电压尖峰。这些高频尖峰会从连接的电缆辐射出去，导致自污染增加。

All of the aforementioned distortion mechanisms can be mitigated by applying global negative feedback. However, closing a feedback loop around a class-D power stage introduces additional distortion mechanisms that are not present in an open loop system [7].
所有上述失真机制都可以通过应用全局负反馈来缓解。然而，在类-D 功率阶段周围闭合反馈回路引入了在开环系统中不存在的额外失真机制 [7]。
If these sources of distortion are not mitigated, they can dominate the overall distortion level.
如果这些失真来源没有得到缓解，它们可能会主导整体失真水平。

In [1] it was shown that the comparator is effectively a sampling operation. The PWM waveform that is fed back through the loop to the comparator input contains harmonics of the switching frequency and their associated side-bands.
在[1]中显示，比较器实际上是一种采样操作。通过闭环反馈到比较器输入的 PWM 波形包含开关频率的谐波及其相关的旁瓣。
When this signal is sampled at the comparator input, some of these components will alias into the audio band.
当这个信号在比较器输入处采样时，一些这些组件会混叠到音频带宽中。

Furthermore, the effective comparator gain is a function of the slope of the comparator input signal at the sampling instance [1]. Since the feedback ripple signal is a filtered
此外，有效比较器增益是采样时刻比较器输入信号斜率的函数[1]。由于反馈纹波信号是经过滤的

PWM waveform, its shape depends on duty cycle. It therefore follows that the slope of the signal at the comparator input, and hence the comparator gain, will depend on duty cycle. This is an additional non-linearity.
PWM 波形的形状取决于占空比。因此，比较器输入信号的斜率，以及因此的比较器增益，将取决于占空比。这是额外的非线性。

Distortion due to ripple feedback can be greatly minimised by implementing the ripple compensation technique described in Section 2.4.
由于振铃反馈引起的失真可以通过在第 2.4 节描述的振铃补偿技术的实施来大大减小。

In an ideal pulse-width-modulator, the comparator is the only non-linear element and is traditionally linearised into an equivalent gain [14].
在理想的脉冲宽度调制器中，比较器是唯一的非线性元件，并且传统上被等效为等效增益[14]。
However, the linearised continuoustime model fails to account for the high frequency behaviour of the comparator, and stability margins cannot be determined accurately .
然而，线性化连续时间模型未能考虑到比较器的高频行为，因此无法准确确定稳定性裕度。

A very accurate model in which the comparator is modelled as a sampling operation and the continuous-time loop is converted to discrete-time was presented in [1] and [15].
在[1]和[15]中，提出了一种非常准确的模型，在该模型中，比较器被建模为采样操作，连续时间循环被转换为离散时间。
This model accounts for non-linear effects of pulse-width modulation like aliasing and the formation of image components. Furthermore, the comparator frequency response is accurately modelled to above the switching frequency and loop stability can be determined more accurately.
该模型考虑了脉冲宽度调制的非线性效应，如混叠和图像组件的形成。此外，比较器的频率响应被准确地建模到开关频率之上，从而可以更准确地确定闭环稳定性。

A small-signal model describes the AC behaviour of a system linearised around a steadystate operating point. A pulse-width modulator operates in steady-state when the modulator output is a duty cycle periodic pulse waveform. Figure 2.6 shows the conceptual small-signal model of an ideal comparator [1]. The small-signal model consists of two identical comparator models. One receives a periodic carrier as input, while the other receives the same periodic carrier with a small superimposed perturbation signal . The comparator's small-signal response is the difference between the outputs of the two comparators. The ideal comparator and power stage is modelled as a gain followed by saturation to the power stage supply voltage .
小信号模型描述了系统在稳态运行点线性化后的 AC 行为。脉宽调制器在稳态运行时，调制器输出为具有 0#占空比的周期脉冲波形。图 2.6 展示了理想比较器的理想小信号模型[1]。小信号模型由两个完全相同的比较器模型组成。一个接收周期性载波 作为输入，而另一个接收相同的周期性载波，但带有小的叠加扰动信号 。比较器的小信号响应是两个比较器输出的差值。理想比较器和功率级被建模为增益 ，随后是到功率级供电电压 的饱和。

Figure 2.7 shows the waveforms associated with the small-signal model. The carrier is periodic with frequency and has two uniformly spaced zero crossings per period. For a short time at the zero crossings of the comparator acts as a linear gain . Outside this time interval the comparator is saturated and cannot respond to a change in input. The time interval is approximately
图 2.7 展示了小信号模型相关的波形。载波 是周期性的，频率为 ，每个周期有两个均匀间隔的零交叉。在 的零交叉点附近持续时间 的时间内，比较器作为线性增益 。在这一时间区间之外，比较器饱和，无法响应输入的变化。这个时间区间大约为

Figure 2.6: Small-signal comparator model [1].
图 2.6：小信号比较器模型 [1]。

where is the slope of the carrier signal at a zero-crossing. The small-signal PWM response is effectively the product between and a pulse train of amplitude and pulse duration .
在零穿越点处，载波信号 的斜率是 。小信号 PWM 响应 实际上是 与振幅为 、脉冲持续时间为 的脉冲串 的乘积。

Figure 2.7: Comparator waveforms [1].
图 2.7：比较器波形 [1]

The area of each pulse of is
每个脉冲的区域是 的面积

Note that the area of a pulse of is independent of the magnitude of a pulse and that for large values of . The periodic pulse waveform can therefore be
注意脉冲面积 与脉冲的幅度 无关，且对于较大的 值， 也成立。因此，周期性脉冲波形 可以
approximated by a Dirac comb of frequency [16]. Multiplication by a Dirac comb in the time domain is equivalent to sampling. The comparator therefore acts as a sampling operation with sampling frequency , followed by a gain which is the mean value of :
由频率 的狄拉克梳状函数近似表示[16]。时间域中的狄拉克梳状函数乘法等同于采样。因此，比较器作为具有频率 的采样操作，随后是增益 ，该增益是 的平均值：

In the case of natural sampling PWM where the carrier is a triangle or sawtooth wave with amplitude , the comparator gain is
在自然采样 PWM 的情况下，当载波 是一个幅度为 的三角波或锯齿波时，比较器增益 是

Figure 2.8 shows the comparator model embedded in a feedback loop. is a loop filter and and model noise and distortion that is added at the comparator input and output, respectively.
图 2.8 显示了比较器模型嵌入在反馈回路中。 是环路滤波器， 和 模型在比较器输入和输出处添加的噪声和失真。

Figure 2.8: Comparator model embedded in a feedback loop.
图 2.8：嵌入反馈环路的比较器模型。

The small-signal output of the comparator and power stage approximates a series of delta impulses, or a sampled signal. Since the loop filter is fed by a sampled signal and its output is again sampled by the comparator, we only care about the loop filter response at the sampling instances.
比较器和功率级的小信号输出在 0#附近近似为一系列 delta 脉冲，或者是一个采样信号。由于环路滤波器由采样信号供电，其输出又被比较器再次采样，因此我们只关心环路滤波器在采样时刻的响应。
Hence the continuous-time loop filter can be replaced by a discrete-time equivalent, as shown in Figure 2.9.
因此，连续时间环路滤波器可以被离散时间等效替代，如图 2.9 所示。

Figure 2.9: Discrete-time comparator model embedded in a feedback loop.
图 2.9：嵌入反馈回路的离散时间比较器模型。

The input reference signal propagates through the loop filter before reaching the comparator input. Therefore the input reference signal has to be filtered in continuous-time by before sampling [1]. Similarly, is added in continuoustime. The error source represents timing errors in the power stage and manifests as errors in the values of the Dirac impulses of . Hence the power stage error source is added directly to the discrete-time loop as . The signal is a discrete-time signal that represents the deviation of the modulator from the steady-state operating point.
输入参考信号 通过环路滤波器 后到达比较器输入。因此，输入参考信号 必须在连续时间下由 进行过滤，然后进行采样 [1]。同样， 在连续时间下添加。误差源 表示功率级中的定时误差，并表现为 的狄拉克脉冲值的误差。因此，功率级误差源 直接添加到离散时间环路中作为 。信号 是一个离散时间信号，表示调制器偏离稳态运行点的偏差。

As mentioned earlier, the continuous-time loop filter is fed by a sampled signal (a series of Dirac impulses) and its output is again sampled.
如前所述，连续时间循环滤波器由采样信号（一系列狄拉克脉冲）提供输入，其输出再次被采样。
This operation is similar to the impulse-invariant method of discretisation, which involves taking the z-transform of the sampled impulse-response of a system [17]. Consequently, the continuous-time loop filter can be converted to its discrete-time equivalent through the impulse invariant transform.
此操作类似于离散化中的冲激一致法，该方法涉及对系统采样冲激响应进行 z 变换 [17]。因此，连续时间回路滤波器 可以通过冲激一致变换转换为其等效的离散时间形式 。

Since the real system has to be causal, the comparator can only respond to the loop's response to a previous output sample. This means that the actual system always has at least a one sample delay.
由于实际系统必须具有因果性，比较器只能响应环路对前一个输出样本的响应。这意味着实际系统总是至少有一个样本的延迟。
This can be taken into account in the impulse-invariant transform by removing the impulse response sample at time zero [1]:
这可以在脉冲不变变换中考虑，通过在时间零处移除脉冲响应样本 [1]：

where is the direct impulse-invariant transform of . In Section 6.2 a slightly different approach to the impulse-invariant transform is suggested.
其中 是 的直接脉冲不变变换。在第 6.2 节中，建议了一种稍微不同的脉冲不变变换方法。

The effective comparator gain depends on the slope of the comparator input signal at zero crossings. The large-signal output of the real system is a PWM waveform. The PWM signal is filtered by the loop filter prior to reaching the comparator input and causes a periodic ripple signal to be added to the carrier. The slope of the comparator input signal at zero-crossings is the sum of the slopes of the carrier and ripple signal. For a triangle wave carrier with amplitude , the comparator gain is
有效比较器增益 取决于比较器输入信号在零过零点的斜率。实际系统的大型信号输出是一个 PWM 波形。PWM 信号在到达比较器输入之前由环路滤波器进行滤波，导致在载波上添加周期性波动信号 。比较器输入信号在零过零点的斜率是载波和波动信号斜率的总和。对于具有幅度 的三角波载波，比较器增益 是

where is the slope of the ripple signal just prior to a rising edge zero crossing of the comparator [1]. It should be noted that the ripple feedback signal reduces the effective comparator gain relative to open-loop operation.
在比较器[1]的上升沿零穿越之前， 是振荡信号 的斜率。应该注意的是，振荡反馈信号相对于开环操作降低了比较器的有效增益。

Closing a feedback loop around a PWM modulator introduces distortion mechanisms that are not present in the open-loop system. The PWM output signal contains components at multiples of the carrier frequency, as well as additional components centred around these.
关闭反馈回路到 PWM 调制器周围引入了在开环系统中不存在的失真机制。PWM 输出信号包含载体频率的倍数处的成分，以及围绕这些成分的额外成分。
When the output is fed back through the loop to the comparator input, some of these components will be aliased into the audio band due to the sampling nature of the comparator . Aliased components that are harmonically related to the input signal will manifest as harmonic distortion.
当输出通过回路反馈到比较器输入时，由于比较器 的采样性质，这些组件将被映射到音频带宽中。与输入信号谐波相关的映射组件将表现为谐波失真。

In [7] a so-called minimum-aliasing-error loop filter is discussed that reduces the effect of feedback ripple aliasing by cancelling parts of the aliasing error.
在[7]中，讨论了一种所谓的最小伪影误差环路滤波器，它通过消除伪影误差的部分来减少反馈振铃伪影的影响。
In [6] the non-linearity is reduced by dynamically modifying the symmetry of the carrier to counteract the phase shift in the effective sampling instances due to ripple feedback.
在[6]中，通过动态修改载体的对称性来抵消有效采样实例中由于纹波反馈引起的相位移，从而减少非线性。
In [8] and [18] a simple and very effective ripple compensation method is presented to reduce the effect of ripple aliasing in pulse-width modulators.
在[8]和[18]中，提出了一种简单且非常有效的振荡补偿方法，以减少脉冲宽度调制器中振荡混叠的影响。
A great benefit of the ripple compensation technique is that it gives the designer freedom in designing the transfer function and topology of the control loop. This method is implemented in a digitally-controlled PWM amplifier with state-of-the-art performance in [2].
振荡补偿技术的一大好处是它赋予了设计者在设计控制回路的传递函数和拓扑结构方面的自由。这种方法在数字控制 PWM 放大器中实现，并具有最先进的性能，详情见[2]。
This section describes the basic operation of the ripple compensation strategy discussed in .
本节描述了在 中讨论的振荡补偿策略的基本操作。

Figure 2.10 shows the simplest ripple compensation implementation for a NSSSPWM loop. The loop filter provides gain for error rejection. The feedback signal is modified
图 2.10 展示了 NSSSPWM 环路中最简单的振荡补偿实现。滤波器 提供增益以拒绝误差。反馈信号被修改。

Figure 2.10: Simple PWM feedback loop with ripple compensation [2].
图 2.10：简单的 PWM 反馈回路，带有纹波补偿 [2]。

by adding the sawtooth carrier to the PWM output . This has the effect of cancelling the unmodulated edge of the PWM waveform, thereby making the ripple signal reaching the comparator input largely independent of duty cycle and reducing the effect of the ripple feedback to only a DC offset.
通过将锯齿形载体 添加到 PWM 输出 。这起到了抵消 PWM 波形未调制边缘的作用，从而使到达比较器输入的纹波信号很大程度上独立于占空比，并减少了纹波反馈仅对直流偏置的影响。
From a frequency domain perspective, this means that only components related to the carrier are aliased into the audio band.
从频域角度来看，这意味着只有与载波相关的成分会被映射到音频带宽内。