Analog reservoir computing (ARC) systems have attracted attention owing to their efficiency in processing temporal information. However, the distinct functionalities of the system components pose challenges for hardware implementation. Herein, we report a fully integrated ARC system that leverages material versatility of the ferroelectric-to-mixed phase boundary (MPB) hafnium zirconium oxides integrated onto indium-gallium-zinc oxide thinfilm transistors (TFTs). MPB-based TFTs (MPBTFTs) with nonlinear short-term memory characteristics are utilized for physical reservoirs and artificial neuron, while nonvolatile ferroelectric TFTs mimic synaptic behavior for readout networks. Furthermore, double-gate configuration of MPBTFTs enhances reservoir state differentiation and state expansion for physical reservoir and processes both excitatory and inhibitory pulses for neuronal functionality with minimal hardware burden. The seamless integration of ARC components on a single wafer executes complex real-world time-series predictions with a low normalized root mean squared error of 0.28 . The material-device co-optimization proposed in this study paves the way for the development of area- and energy-efficient ARC systems. 模拟储层计算 (ARC) 系统因其处理时间信息的效率而引起了人们的关注。然而,系统组件的不同功能对硬件实现提出了挑战。在此,我们报告了一个完全集成的 ARC 系统,该系统利用集成到铟镓锌氧化物薄膜晶体管 (TFT) 上的铁电到混合相边界 (MPB) 铪锆氧化物的材料多功能性。具有非线性短期记忆特性的基于 MPB 的 TFT (MPBTFT) 用于物理储层和人工神经元,而非易失性铁电 TFT 模拟读出网络的突触行为。此外,MPBTFT 的双门配置增强了物理储层的储层状态分化和状态扩展,并以最小的硬件负担处理神经元功能的兴奋性和抑制性脉冲。ARC 组件在单个晶圆上的无缝集成执行了复杂的真实世界时间序列预测,归一化均方根误差低至 0.28。本研究提出的材料-器件协同优化为开发面积和能源效率高的 ARC 系统铺平了道路。
In the landscape of contemporary computing, deep neural networks (DNNs) have gained prominence by enabling breakthroughs across various applications from image classification to healthcare technologies ^(1-6){ }^{1-6}. Although DNNs and their feedforward configurations have shown remarkable success in executing static tasks such as pattern recognition ^(7-10){ }^{7-10}, they are unsuitable for processing dynamic data. In this context, recurrent neural networks (RNNs), specifically analog reservoir computing (ARC) systems, have emerged as pivotal solutions ^(11-14){ }^{11-14}. An ARC system employs a dynamic reservoir that projects the input data nonlinearly into a high-dimensional feature space (Supplementary Fig. 1). This mapping, facilitated by the intrinsic short- 在当代计算领域,深度神经网络 (DNN) 通过实现从图像分类到医疗保健技术 ^(1-6){ }^{1-6} 的各种应用的突破而获得突出地位。尽管 DNN 及其前馈配置在执行模式识别 ^(7-10){ }^{7-10} 等静态任务方面取得了显着成功,但它们并不适合处理动态数据。在这种情况下,递归神经网络 (RNN),特别是模拟储层计算 (ARC) 系统,已成为关键解决方案 ^(11-14){ }^{11-14} 。ARC 系统采用动态储层,将输入数据非线性地投影到高维特征空间中(补充图 1)。这种映射由内在的短
term memory capabilities of the reservoir, enables the transformation of complex inputs into linearly separable states within the system ^(14,15){ }^{14,15}. The linearly weighted summation of these states is then processed using a trainable readout network, making ARC an efficient and robust framework for temporal data processing and prediction tasks. 储层的术语记忆能力,能够在系统 ^(14,15){ }^{14,15} 内将复杂的输入转换为线性可分离的状态。然后使用可训练的读出网络处理这些状态的线性加权总和,使 ARC 成为时间数据处理和预测任务的高效且强大的框架。
However, conventional ARC systems based on complementary metal-oxide-semiconductor (CMOS) platforms suffer from a deficiency in inherent dynamic response characteristics ^(16){ }^{16}. This necessitates the use of complex algorithms along with large-scale integrated devices to handle nonlinear dynamic tasks, thus hindering the complete realization of the potential of ARC^(17)\mathrm{ARC}^{17}. To overcome this limitation, 然而,基于互补金属氧化物半导体 (CMOS) 平台的传统 ARC 系统存在固有动态响应特性 ^(16){ }^{16} 的缺陷。这需要使用复杂的算法以及大规模集成器件来处理非线性动态任务,从而阻碍了 ARC^(17)\mathrm{ARC}^{17} 的潜力的完全实现。为了克服这一限制,
the exploration of hardware-based ARC systems utilizing novel materials and device configurations has garnered research interest; specifically, materials and devices that exhibit distinct volatile and nonvolatile switching characteristics to implement the reservoir and readout networks, respectively. Various devices, including twoterminal memristors ^(5,18-27){ }^{5,18-27}, ferroelectric devices ^(28-32){ }^{28-32}, spintronic oscillators ^(33){ }^{33}, electrochemical transistors ^(34-36){ }^{34-36}, photonic module devices ^(37-39){ }^{37-39}, and quantum devices ^(40){ }^{40}, have been studied for the possible candidate. Despite the advantages of these hardware-based ARC systems, the full integration of the reservoir, readout network, and additional circuit components with artificial neuron functionality remains a challenge due to the utilization of different materials for each component (detailed in Supplementary Note 1). Zhong, Y. et al. presented an ARC system based on two-terminal memristors; however, the realization of the reservoir and readout network necessitated different materials -TiO_(x)-\mathrm{TiO}_{x} for the physical reservoir and TaO_(x)//HfAlO_(y)\mathrm{TaO}_{\mathrm{x}} / \mathrm{HfAlO}_{\mathrm{y}} for the artificial synapse in the readout network ^(18){ }^{18}. Consequently, the seamless integration of these components was unattainable, promting separate fabrication of each component connected through wiring afterward. Moreover, in most studies, the integration of neuron circuitry for the readout network in ARC has not been adequately explored. 利用新型材料和器件配置对基于硬件的 ARC 系统的探索引起了研究兴趣;具体来说,表现出不同易失性和非易失性开关特性的材料和器件分别实现储液罐和读出网络。已经研究了各种器件,包括双端子忆阻器 ^(5,18-27){ }^{5,18-27} 、铁电器件 ^(28-32){ }^{28-32} 、自旋电子振荡器 ^(33){ }^{33} 、电化学晶体管 ^(34-36){ }^{34-36} 、光子模块器件 ^(37-39){ }^{37-39} 和量子器件 ^(40){ }^{40} ,以寻找可能的候选者。尽管这些基于硬件的 ARC 系统具有优势,但由于每个组件使用不同的材料,因此将储液器、读出网络和附加电路组件与人工神经元功能完全集成仍然是一个挑战(详见补充说明 1)。Zhong, Y. 等人提出了一种基于双端子忆阻器的 ARC 系统;然而,储层和读出网络的实现需要为物理储层和 TaO_(x)//HfAlO_(y)\mathrm{TaO}_{\mathrm{x}} / \mathrm{HfAlO}_{\mathrm{y}} 读出网络 ^(18){ }^{18} 中的人工突触提供不同的材料 -TiO_(x)-\mathrm{TiO}_{x} 。因此,这些组件的无缝集成是无法实现的,之后通过布线连接的每个组件的单独制造。此外,在大多数研究中,ARC 中读出网络的神经元电路的集成尚未得到充分探索。
Hafnium oxide (HfO_(2))\left(\mathrm{HfO}_{2}\right)-based thin films present a promising solution to address these challenges by leveraging the material versatility of hafnia. HfO_(2)\mathrm{HfO}_{2} has traditionally served as a high- kappa\kappa dielectric in conventional CMOS technology since the mid-2000s ^(41){ }^{41}. Following the discovery of its ferroelectricity originating from the orthorhombic (o)phase in 2011, its applications have expanded to nonvolatile functionalities for memory and artificial synaptic devices ^(42-46){ }^{42-46}. Furthermore, through material engineering, anti-ferroelectricity, suitable for dynamic response in ARC, can also be realized. Recent advancements include the utilization of hafnium zirconium oxide (HZO) thin films near the mixed phase boundary (MPB) between the ferroelectric o-phase and tetragonal ( t )-phase ^(47,48){ }^{47,48}. Although there have been no prior attempts to exploit the HZO thin films near the MPB for ARC, its volatile memory characteristics and higher polarization magnitude at lower voltages compared to anti-ferroelectric films make it suitable for both the physical reservoir and artificial neuron (Fig. 1a). Therefore, by carefully engineering HfO_(2)\mathrm{HfO}_{2}-based films from ferroelectric to MPB, comprehensive integration of physical reservoir, artificial synapse, and neuron functionalities can be achieved (Supplementary Note 2a). In addition to material engineering, optimizing device configuration can further enhance the performance of ARC (Fig. 1a). While two-terminal devices are commonly employed, double-gate (DG) transistors with four terminals offer advantages in terms of enhanced controllability and reliability. Unlike two-terminal devices, which pose significant constraints in implementing neuronal functionality, DG transistors provide a broader range of design possibilities for artificial neurons. Furthermore, DG transistors facilitate a clearer differentiation between reservoir states, thereby overcoming the poor resolution and limited number of reservoir states ( 3 or 4 bits) ^(16,22,28,29,49-52){ }^{16,22,28,29,49-52}. Although various attempts have been made to mitigate these challenges in two-terminal devices, such as employing input encoding with various pulse intervals ^(22,50){ }^{22,50}, they require additional circuitry, inevitably increasing area and power consumption. Control of electrical characteristics utilizing additional electrodes in four-terminal transistors can improve the resolution between the states without the burden of additional circuit. 基于氧化 (HfO_(2))\left(\mathrm{HfO}_{2}\right) 铪的薄膜提供了一种很有前途的解决方案,通过利用铪的材料多功能性来应对这些挑战。自 2000 年代 ^(41){ }^{41} 中期以来 HfO_(2)\mathrm{HfO}_{2} ,传统上在传统 CMOS 技术中用作高 kappa\kappa 电介质。继 2011 年发现其起源于正交 (o) 相的铁电性后,其应用已扩展到存储器和人工突触器件 ^(42-46){ }^{42-46} 的非易失性功能。此外,通过材料工程,还可以实现适用于 ARC 动态响应的反铁电性。最近的进展包括在铁电 o 相和四方 (t) 相 ^(47,48){ }^{47,48} 之间的混合相边界 (MPB) 附近使用铪锆 (HZO) 薄膜。尽管之前没有尝试将 MPB 附近的 HZO 薄膜用于 ARC,但与反铁电薄膜相比,其易失性存储特性和较低电压下的更高极化幅度使其适用于物理储层和人工神经元(图 1a)。因此,通过精心设计 HfO_(2)\mathrm{HfO}_{2} 从铁电到 MPB 的基于薄膜,可以实现物理储层、人工突触和神经元功能的全面集成(补充注 2a)。除了材料工程外,优化器件配置还可以进一步提高 ARC 的性能(图 1a)。虽然通常采用双端子器件,但具有四个端子的双栅 (DG) 晶体管在增强可控性和可靠性方面具有优势。 与在实现神经元功能方面构成重大限制的双端器件不同,DG 晶体管为人工神经元提供了更广泛的设计可能性。此外,DG 晶体管有助于更清晰地区分储层状态,从而克服分辨率差和储层态数量有限(3 或 4 位) ^(16,22,28,29,49-52){ }^{16,22,28,29,49-52} 的问题。尽管已经进行了各种尝试来缓解双端设备中的这些挑战,例如采用具有各种脉冲间隔 ^(22,50){ }^{22,50} 的输入编码,但它们需要额外的电路,不可避免地会增加面积和功耗。利用四端晶体管中的附加电极控制电气特性可以提高状态之间的分辨率,而无需额外电路的负担。
In this study, we propose a material-device co-optimization method for the area- and energy-efficient ARC system utilizing HZObased thin-film transistors (TFTs). The seamless integration of physical reservoir, readout network, and leaky integrate-and-fire (LIF) neuron is achieved by meticulously engineering the material versatility of HZO (Fig. 1b). HZO with the o-phase is utilized for nonvolatile and multilevel conductances of the ferroelectric TFT (FeTFT)-based artificial synapse, 在这项研究中,我们提出了一种利用基于 HZO 的薄膜晶体管 (TFT) 的面积和能源效率高的 ARC 系统的材料-器件协同优化方法。物理储层、读出网络和泄漏集成-发射 (LIF) 神经元的无缝集成是通过精心设计 HZO 的材料多功能性来实现的(图 1b)。具有 o 相的 HZO 用于基于铁电 TFT (FeTFT) 的人工突触的非易失性和多能级电导,
while HZO near the MPB serves as both the physical reservoir and LIF neuron (Fig. 1c-e). All these materials are integrated into the TFTs with an indium-gallium-zinc oxide (IGZO) channel. The device configuration of DG MPB-based TFT (MPBTFT) improves the performance of the ARC system by leveraging the electrical characteristics of DG to clearly distinguish between the 16 reservoir states without overlapping, and successfully demonstrates 5 -bit reservoir states. For neuronal functionality, DG MPBTFT processes both excitatory and inhibitory pulses within a single device, unlike previously reported ferroelectric-based three-terminal LIF neurons ^(53-55){ }^{53-55}. Importantly, the adoption of similar fabrication processes for volatile and nonvolatile TFTs with HZO films enables their co-integration on a single wafer, a milestone previously unattainable. Various tasks, ranging from handwritten digit recognition tasks to waveform classification and complex time-series predictive tasks in the real world, were performed to evaluate the performance of the proposed ARC system. The integration of volatile and nonvolatile TFTs into an ARC system overcomes the limitations of previous hardware-based ARC systems and sets a new standard for energy efficiency, scalability, and versatility in ARC systems. 而 MPB 附近的 HZO 既是物理储液器又是 LIF 神经元(图 1c-e)。所有这些材料都通过铟-镓-锌氧化物 (IGZO) 通道集成到 TFT 中。DG 基于 MPB 的 TFT (MPBTFT) 的器件配置通过利用 DG 的电气特性清楚地区分 16 种储层状态而不重叠,从而提高了 ARC 系统的性能,并成功演示了 5 位储层态。对于神经元功能,DG MPBTFT 在单个设备中处理兴奋性和抑制性脉冲,这与以前报道的基于铁电的三端 LIF 神经元不同 ^(53-55){ }^{53-55} 。重要的是,采用类似的制造工艺来处理带有 HZO 薄膜的挥发性和非挥发性 TFT,使它们能够在单个晶圆上共集成,这是以前无法实现的里程碑。执行了各种任务,从手写数字识别任务到现实世界中的波形分类和复杂的时间序列预测任务,以评估所提出的 ARC 系统的性能。将易失性和非易失性 TFT 集成到 ARC 系统中克服了以前基于硬件的 ARC 系统的局限性,并为 ARC 系统的能效、可扩展性和多功能性设定了新标准。
Results 结果
Device Structures 设备结构
Two distinct types of HZO-based TFTs were fabricated to implement an ARC system: nonvolatile FeTFT for the synaptic device in the readout network and volatile MPBTFT for the physical reservoir and LIF neuron. While both TFTs utilize HZO thin films as ferroelectric materials, variations in the material composition of the HZO thin films impart the TFTs with either volatile or nonvolatile characteristics, diversifying their functionality within the system. Both TFTs incorporate an IGZO channel within a metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) structure, achieving enhanced electrical characteristics (Supplementary Note 3). In particular, an MPBTFT was designed as a DG device, enabling its operation to be modulated not only by the bottom-gate (BG) but also by the top-gate (TG). TG can be utilized to refine the reservoir states of MPBTFTs and execute inhibition operations in LIF neurons. The structural similarities between FeTFT and MPBTFT facilitate the integration of both types of TFTs on a single wafer using a self-align etching process. The fabrication process for both TFTs is detailed in the Methods section and Supplementary Fig. 2. 制造了两种不同类型的基于 HZO 的 TFT 来实现 ARC 系统:用于读出网络中突触装置的非易失性 FeTFT 和用于物理储层和 LIF 神经元的易失性 MPBTFT。虽然两种 TFT 都使用 HZO 薄膜作为铁电材料,但 HZO 薄膜材料成分的变化赋予 TFT 易失性或非易失性特性,使其在系统内的功能多样化。两种 TFT 在金属-铁电-金属-绝缘体半导体 (MFMIS) 结构中都集成了 IGZO 通道,实现了增强的电气特性(补充注 3)。特别是,MPBTFT 被设计为 DG 器件,使其操作不仅受底门 (BG) 的调制,还受顶门 (TG) 的调制。TG 可用于改进 MPBTFT 的储库状态并在 LIF 神经元中执行抑制操作。FeTFT 和 MPBTFT 之间的结构相似性有助于使用自对准蚀刻工艺将两种类型的 TFT 集成到单个晶圆上。两种 TFT 的制造工艺在方法部分和补充图 2 中详细介绍。
Nonvolatile synaptic FeTFT for readout network 用于读出网络的非易失性突触 FeTFT
Figure 2a shows a schematic illustration and cross-sectional view of a nonvolatile FeTFT with an MFMIS structure. The cross-sectional transmission electron microscopy (TEM) images of the fabricated FeTFTs are shown in Fig. 2b. The structure of the FeTFT with a Mo/ HZO//TiN//ZrO_(2)//IGZO\mathrm{HZO} / \mathrm{TiN} / \mathrm{ZrO}_{2} / \mathrm{IGZO} stack was examined using energy-dispersive spectroscopy (EDS) analysis (Supplementary Fig. 3). The crystallinity of the HZO (Hf:Zr = 2:1) thin films were investigated using grazing incidence X-ray diffraction (GIXRD) analysis (Supplementary Fig. 4a). Figure 2c shows the top optical images of the FeTFT array for the readout network within the ARC system. Each FeTFT functions as a synaptic device within the readout network by leveraging the inherent nonvolatile memory effects of ferroelectric materials. 图 2a 显示了具有 MFMIS 结构的非挥发性 FeTFT 的示意图和横截面图。制造的 FeTFT 的横截面透射电子显微镜 (TEM) 图像如图 2b 所示。使用能量色散光谱 (EDS) 分析检查具有 Mo/ HZO//TiN//ZrO_(2)//IGZO\mathrm{HZO} / \mathrm{TiN} / \mathrm{ZrO}_{2} / \mathrm{IGZO} 堆栈的 FeTFT 的结构(补充图 3)。使用掠入射 X 射线衍射 (GIXRD) 分析研究 HZO (Hf:Zr = 2:1) 薄膜的结晶度(补充图 4a)。图 2c 显示了 ARC 系统内读出网络的 FeTFT 阵列的顶部光学图像。每个 FeTFT 通过利用铁电材料固有的非易失性记忆效应,在读出网络中充当突触器件。
Capacitors with a metal-ferroelectric-metal (MFM) structure subjected to identical fabrication processes as the FeTFTs were utilized to verify the ferroelectric properties of the FeTFTs. The ferroelectric switching current is distinguished from non-ferroelectric switching currents, such as displacement and leakage currents, through positive-up-negative-down (PUND) measurements-wherein 100 kHz triangular pulses are applied. The switching current and polarization as a function of the applied voltage are depicted in Fig. 2d. The HZO film exhibits the magnitude of remanent polarization (2P_(r))\left(2 P_{\mathrm{r}}\right) of approximately 37.7 muC//cm^(2)37.7 \mu \mathrm{C} / \mathrm{cm}^{2} in the sweep range from -3.8 V to 3.8 V . Figure 2e illustrates the hysteretic transfer characteristics of the FeTFT. 具有金属-铁电-金属 (MFM) 结构的电容器采用与 FeTFT 相同的制造工艺,以验证 FeTFT 的铁电特性。铁电开关电流与非铁电开关电流(例如位移和漏电流)通过正-上-负-下 (PUND) 测量区分开来,其中施加 100 kHz 三角脉冲。开关电流和极化作为外加电压的函数如图 2d 所示。HZO 薄膜的剩余极化 (2P_(r))\left(2 P_{\mathrm{r}}\right) 幅度约为 37.7 muC//cm^(2)37.7 \mu \mathrm{C} / \mathrm{cm}^{2} -3.8 V 至 3.8 V 的扫描范围。图 2e 说明了 FeTFT 的滞后转移特性。
suitable candidates for physical reservoirs and LIF neurons within ARC systems, primarily owing to their inherent nonlinearity and short-term memory characteristics. FeTFTs are distinguished by their ability to represent multilevel synaptic weights with stability over time, making them ideal components for the readout network within ARC systems. By integrating these TFTs, ARC systems can harness the transient data processing capabilities of MPBTFTs with the long-term data retention properties of FeTFTs. 适合 ARC 系统内物理储层和 LIF 神经元的候选者,主要是因为它们固有的非线性和短期记忆特性。FeTFT 的特点是能够表示多级突触权重,并随着时间的推移保持稳定性,使其成为 ARC 系统内读出网络的理想组件。通过集成这些 TFT,ARC 系统可以利用 MPBTFT 的瞬态数据处理能力和 FeTFT 的长期数据保留特性。
The transfer characteristics demonstrate a counterclockwise hysteresis loop with a wide memory window (MW) of approximately 2.2 V at a constant drain current ( I_(D)I_{\mathrm{D}} ) of 10 nA . 传输特性表明,在 10 nA 的恒定漏极电流 ( I_(D)I_{\mathrm{D}} ) 下,具有约 2.2 V 的宽存储窗口 (MW) 的逆时针磁滞回线。
The nonvolatile FeTFTs can emulate the plasticity of biological synapses through the partial polarization switching of the HZO film ^(31,32,55,56){ }^{31,32,55,56}. The long-term potentiation (LTP) and long-term depression (LTD) characteristics of the FeTFT were investigated by applying program (PGM) and erase (ERS) pulses (Fig. 2f). The pulse widths were consistently maintained at 10 mus10 \mu \mathrm{~s}, and PGM pulse amplitudes increased from 3.5 V to 4.1 V in steps of 0.04 V , while ERS pulse amplitudes decreased from -4.35 V to -5.1 V in steps of -0.05 V . Multilevel synaptic weights were obtained through the FeTFT exhibiting a highly linear conductance response, characterized by coefficients beta_(p)=0.04\beta_{\mathrm{p}}=0.04 and beta_(d)=1.95^(6)\beta_{\mathrm{d}}=1.95^{6}. Figure 2 g illustrates the LTP and LTD characteristics of the FeTFT over 20 cycles. Low cycle-to-cycle variation is observed ( sigma//mu < 0.025,sigma\sigma / \mu<0.025, \sigma and mu\mu are the standard deviation and average value, respectively), indicating consistency and reliability in the operation of the FeTFT over multiple operational cycles. 非易失性 FeTFT 可以通过 HZO 膜 ^(31,32,55,56){ }^{31,32,55,56} 的部分极化切换来模拟生物突触的可塑性。通过应用程序 (PGM) 和擦除 (ERS) 脉冲研究了 FeTFT 的长时程增强 (LTP) 和长时程抑制 (LTD) 特性(图 2f)。脉冲宽度始终保持在 10 mus10 \mu \mathrm{~s} ,PGM 脉冲幅度以 0.04 V 的步长从 3.5 V 增加到 4.1 V,而 ERS 脉冲幅度以 -0.05 V 的步长从 -4.35 V 降低到 -5.1 V。通过 FeTFT 获得多级突触权重,表现出高度线性的电导响应,其特征是系数 beta_(p)=0.04\beta_{\mathrm{p}}=0.04 和 beta_(d)=1.95^(6)\beta_{\mathrm{d}}=1.95^{6} 。图 2 g 说明了 FeTFT 在 20 个周期内的 LTP 和 LTD 特性。观察到低周期间变化( sigma//mu < 0.025,sigma\sigma / \mu<0.025, \sigma 和 mu\mu 分别是标准偏差和平均值),表明 FeTFT 在多个操作周期内的运行一致性和可靠性。
The retention characteristics of the FeTFT with various memory states are depicted in Fig. 2h, showing its nonvolatile memory characteristics. The FeTFT preserves the stored information for 10^(3)s10^{3} \mathrm{~s} with a slight degradation, verifying the robustness and reliability of the device. The device-to-device variation, endurance characteristics, and selective PGM/ERS operations within the FeTFT array were investigated (Supplementary Figs. 5 and 6). The results confirm the suitability of the nonvolatile FeTFTs for synaptic devices. Note that by further optimizing the measurement conditions, a larger dynamic range can be obtained for enhanced system performance (Supplementary Fig. 7). 图 2h 描述了具有各种存储状态的 FeTFT 的保留特性,显示了其非易失性存储特性。FeTFT 保留了存储的信息 10^(3)s10^{3} \mathrm{~s} ,但会略微退化,从而验证了器件的稳健性和可靠性。研究了 FeTFT 阵列内的器件间变化、耐久性特性和选择性 PGM/ERS 操作(补充图 5 和 6)。结果证实了非易失性 FeTFT 对突触器件的适用性。请注意,通过进一步优化测量条件,可以获得更大的动态范围以增强系统性能(补充图 7)。
Volatile double-gate MPBTFT for physical reservoir 用于物理储层的挥发性双栅 MPBTFT
The distinguishing feature of the ARC system is the reservoir, which is a network of nonlinear dynamic nodes that transform input signals into a high-dimensional space, enabling the system to process temporal information. In an MPBTFT-based ARC system, these nodes are represented by volatile DG MPBTFTs, which are physical reservoirs ARC 系统的显着特征是储层,它是一个非线性动态节点网络,可将输入信号转换为高维空间,使系统能够处理时间信息。在基于 MPBTFT 的 ARC 系统中,这些节点由易失性 DG MPBTFT 表示,它们是物理储层
^(1){ }^{1} Department of Electronic Engineering, Hanyang University, Seoul 04763, Republic of Korea. ^(2){ }^{2} Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139, USA. ^(3){ }^{3} Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul 08826, Republic of Korea. ^(4){ }^{4} Department of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea. ^(5){ }^{5} Semiconductor Research and Development Center, Samsung Electronics, Hwaseong, Republic of Korea. ^(6){ }^{6} These authors contributed equally: Jangsaeng Kim, Eun Chan Park, Wonjun Shin. ⊠\boxtimes e-mail: sscheema@mit.edu; jkjeong1@hanyang.ac.kr; dw79kwon@hanyang.ac.kr ^(1){ }^{1} 汉阳大学电子工程系,韩国首尔 04763。麻省理工学院电子 ^(2){ }^{2} 研究实验室,美国剑桥 02139。首尔大学电气与计算机工程 ^(3){ }^{3} 系兼大学间半导体研究中心,韩国首尔 08826。成均馆大学半导体融合工程 ^(4){ }^{4} 系,韩国水原 16419。 ^(5){ }^{5} 三星电子半导体研发中心,华城,韩国。 ^(6){ }^{6} 这些作者的贡献相同:Jangsaeng Kim、Eun Chan Park、Wonjun Shin。 ⊠\boxtimes 电子邮件:sscheema@mit.edu;jkjeong1@hanyang.ac.kr;dw79kwon@hanyang.ac.kr