A. Block Diagram A. 框图

Fig. 1 shows the structure of the optoelectronic computing evaluation and deployment platform. This architecture is divided into two parts, i.e., the photonic chip with peripheral circuits module as well as the fixed point calculation operator module. The fixed point calculation operator module is further divided into Relu, LUT, pooling, Leaky Relu, BN and Shift & Add [11].
图 1 显示了光电计算评估和部署平台的结构。该架构分为两部分，即带外围电路的光子芯片模块和定点计算算子模块。定点计算操作模块进一步分为Relu、LUT、pooling、Leaky Relu、BN和Shift & Add [11]。

Fig. 1.  图 1.

The architecture of optoelectronic computing evaluation and deployment platform.
光电计算评估和部署平台的架构。

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Fig. 2.  图 2.

Analysis of non-ideal factors in optoelectronic computing evaluation and deployment platform.
光电计算评估与部署平台中的非理想因素分析。

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The working flow of the photonic chip with peripheral circuits module is as follows. The high-speed digital-to-analog converter (DAC) with driver modulates the input optical signal by the electro-optic modulator. The low-speed DAC generates the photonic chip calculation matrix by biasing the thermal phase shifter array. The output of the photonic chip is then amplified through the conversion of photodetector (PD) and transimpedance amplifier (TIA). Subsequently, it is quantized and encoded by the high-speed ADC for further processing in the digital domain. The photonic chip generates a 16-row and 16-column matrix for computation, enabling 256 multiply-accumulate operations (MACs). The peripheral electrical modules include a 16-channel DAC and a 16-channel ADC, both transmitting 8-bit information at a clock frequency of 500 MHz. Consequently, the data rate for a single channel is 4 Gb/s, resulting in a communication bandwidth of 16 channels reaching 128 Gb/s for bi-directional transceiver. The calculation formula of hardware performance is shown in (1).
带外围电路的光子芯片模块的工作流程如下。带驱动器的高速数模转换器 （DAC） 通过电光调制器调制输入光信号。低速 DAC 通过偏置热移相器阵列来生成光子芯片计算矩阵。然后，光子芯片的输出通过光电探测器 （PD） 和跨阻放大器 （TIA） 的转换进行放大。随后，它由高速 ADC 量化和编码，以便在数字域中进一步处理。光子芯片生成一个 16 行和 16 列的矩阵用于计算，支持 256 次乘法累加运算 （MAC）。外围电气模块包括一个 16 通道 DAC 和一个 16 通道 ADC，均以 500 MHz 的时钟频率传输 8 位信息。因此，单个通道的数据速率为 4 Gb/s，导致 16 个通道的通信带宽达到双向收发器的 128 Gb/s。硬件性能的计算公式如 （1） 所示。

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查看源 \begin{equation*}TOPS = \,Row\, \times \,Column\, \times 2 \times {F_{clk}}\tag{1}\end{equation*}

Row is the number of MACs matrix row, Column is the number of MAC matrix column, and F_clk is the clock frequency. This yields a hardware performance of 0.25 TOPS for a 16×16 optoelectronic computing chip.
Row 是 MAC 矩阵行的数量， Column 是 MAC 矩阵列的数量， F_clk 是时钟频率。这为 16×16 的光电计算芯片产生了 0.25 TOPS 的硬件性能。

B. Non-Ideal Factors B. 非理想因子

The peripheral electronic modules include ADC, DAC, and TIA. The photonic chip module includes electro-optic modulators, thermal phase shifter array, and PD. Fig. 2 depicts the block diagram with considerations for non-ideal factors. The platform introduces output referred noise, gain and offset error for the high-speed DAC, dark current noise for the PD, input referred current noise for the TIA. Input referred noise, gain and offset error are introduced for the high-speed ADC. Nonlinearity and insertion loss are introduced for the electro-optic modulator. The thermal phase shifter array considers insertion loss and the low-speed DAC considers output referred noise and quantization error.
外设电子模块包括 ADC、DAC 和 TIA。光子芯片模块包括电光调制器、热移相器阵列和 PD。图 2 描述了考虑非理想因素的框图。该平台为高速 DAC 引入了折合到输出端的噪声、增益和偏移误差，为 PD 引入了暗电流噪声，为 TIA 引入了折合到输入端的电流噪声。为高速 ADC 引入了折合到输入端的噪声、增益和偏移误差。为电光调制器引入了非线性和插入损耗。热移相器阵列考虑插入损耗，低速 DAC 考虑折合到输出的噪声和量化误差。

The output of a single-channel high-speed DAC can be expressed in (2).
单通道高速DAC的输出可以用（2）表示。

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查看源 \begin{equation*}{x_I} = IN \times {E_{G,DAC}} + {V_{O,DAC}} + {N_{h\_DAC}}\tag{2}\end{equation*}

Where IN is the ideal output of a single-channel high-speed DAC, E_{G, DAC} is the gain error, V_{O, DAC} is the offset voltage, and N_{h_ DAC} is the output referred noise.
其中，IN是单通道高速DAC的理想输出，E_G，DAC是增益误差，V_O，DAC是失调电压，N_{h_ DAC}是折合到输出端的噪声。

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查看源 \begin{equation*}X = \left[ {\begin{array}{c} {F\left( {{x_1}} \right)} \\ {F\left( {{x_2}} \right)} \\ \vdots \\ {F\left( {{x_{16}}} \right)} \end{array}} \right],\quad O = \left[ {\begin{array}{c} {{o_1}} \\ {{o_2}} \\ \vdots \\ {{o_{16}}} \end{array}} \right]\tag{3}\end{equation*}

In (3), a 16×1 matrix X can be obtained through the electro-optic modulators array. F is a function that introduces higher order harmonic terms and insertion loss for the output of high-speed DAC. The output O is obtained after multiplying X with the 16×16 matrix generated by the thermal phase shifter array. The derivation of the 16×16 matrix will be presented in Section Ⅲ. The signal that needs to be quantized by a single-channel DAC can be expressed in (4).
在（3）中，可以通过电光调制器阵列获得 16×1 矩阵 X。F 是为高速 DAC 的输出引入高阶谐波项和插入损耗的函数。输出 O 是将 X 与热移相器阵列生成的 16×16 矩阵相乘后得到的。16×16 矩阵的推导将在第 III 节中介绍。需要由单通道 DAC 量化的信号可以用 （4） 表示。

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查看源 \begin{equation*}\begin{array}{l} {y_1} = \left( {{o_1} \times {A_{PD}} + {N_{PD}} + {N_{TLA}}} \right) \times {A_{TLA}} \times {E_{G,ADC}} \\ + {V_{O,ADC}} + {N_{h\_ADC}} \end{array} \tag{4}\end{equation*}

Where N_PD is the dark current noise, A_PD is the optoelectronic responsivity, A_TIA is the transconductance gain, N_TIA is the input referred current noise, E_{G, ADC} is the gain error, V_{O, ADC} is the offset voltage, N_{h_ ADC} is the input referred noise.
其中 N_PD 是暗电流噪声，A_PD 是光电响应度，A_TIA 是跨导增益，N_TIA 是折合到输入端的电流噪声，E_G，ADC 是增益误差，_{V O，ADC} 是失调电压，N_{h_ ADC} 是折合到输入端的噪声。

The platform can be packaged to create a 16×16 optoelectronic computing operator chip, equipped with 16 optical/electrical signal inputs and 16 optical/electrical signal outputs. The output signal can be further processed in the optical or electrical domain to support flexible deployment of neural networks.
该平台可以封装成一个 16×16 光电子计算算子芯片，配备 16 个光/电信号输入和 16 个光/电信号输出。输出信号可以在光学或电气域中进一步处理，以支持神经网络的灵活部署。

Fig. 3.  图 3.

Structure of the MZI unit and thermal phase shifter array.
MZI 单元和热移相器阵列的结构。

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Fig. 4.  图 4.

The diagram of the proposed Simulink platform.
建议的 Simulink 平台的图表。

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A. MZI Thermal Phase Shifter Array
A. MZI 热移相器阵列

The basic cell structure [3] in the MZI network is illustrated in Fig. 3. From left to right, there are two phase shifters in this MZI unit to generate phase to control the splitting ratio of the MZI, and then the optical signal passes through a beam splitter. The two arms of the output have two phase shifters to generate phase to control the phase shift difference between the output arms, and finally it passes through a beam splitter again.
MZI 网络中的基本单元结构 [3] 如图 3 所示。从左到右，这个 MZI 单元中有两个移相器产生相位以控制 MZI 的分光比，然后光信号通过分束器。输出的两个臂有两个移相器来产生相位以控制输出臂之间的相移差，最后它再次通过分束器。

The transfer matrix of the MZI can be written as a standard rotation matrix with the expression in (5).
马赫-曾德尔调制器的传递矩阵可以写成标准旋转矩阵，表达式为 （5）。

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查看源 \begin{equation*}\begin{array}{r} {{M_1} = \left[ {\begin{array}{cc} {\cos \varphi }&{j\sin \varphi } \\ {j\sin \varphi }&{\cos \varphi } \end{array}} \right] \times \left[ {\begin{array}{cc} {{e^{j{\alpha _1}}}}&0 \\ 0&{{e^{j{\beta _1}}}} \end{array}} \right]} \\ {\quad \times \left[ {\begin{array}{ll} {\cos \varphi }&{j\sin \varphi } \\ {j\sin \varphi }&{\cos \varphi } \end{array}} \right] \times \left[ {\begin{array}{cc} {{e^{j{\alpha _0}}}}&0 \\ 0&{{e^{j{\beta _0}}}} \end{array}} \right]} \end{array}\tag{5}\end{equation*}

When φ = π /4, the beam splitter used has a beam split ratio of 50:50. Taking into account the influence of the insertion loss I_MZI of MZI unit, (5) can be rewritten as
当 φ = π /4 时，使用的分束器具有 50：50 的分束比。考虑到 MZI 单位的插入损耗 I_MZI 的影响，（5） 可以改写为

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查看源 \begin{equation*}\begin{array}{l} {M_1} = \left[ {\begin{array}{cc} {{e^{j\left( {{\alpha _0} + {\alpha _1}} \right)}} - {e^{j\left( {{\alpha _1} + {\beta _0}} \right)}}}&{j{e^{j\left( {{\alpha _0} + {\alpha _1}} \right)}} + j{e^{j\left( {{\alpha _1} + {\beta _0}} \right)}}} \\ {j{e^{j\left( {{\beta _0} + {\beta _1}} \right)}} + j{e^{j\left( {{\alpha _0} + {\beta _1}} \right)}}}&{{e^{j\left( {{\beta _0} + {\beta _1}} \right)}} - {e^{j\left( {{\alpha _0} + {\beta _1}} \right)}}} \end{array}} \right] \\ \times {I_{MZI}} \end{array} \tag{6}\end{equation*}

Fig. 3 shows a 16×16 thermal phase shifter array with three columns of crossing used to reorder the 16 signals in addition to the MZI units. For example, crossing C can be expressed as ⎡⎣⎢⎢⎢1000001001000001⎤⎦⎥⎥⎥. Thus, we get (7) and (8),
图 3 显示了一个 16×16 热移相器阵列，其中有三列交叉，用于对 16 个信号以及 MZI 单元进行重新排序。例如，交叉 C 可以表示为 ⎡⎣⎢⎢⎢1000001001000001⎤⎦⎥⎥⎥ 。因此，我们得到 （7） 和 （8），

Fig. 5.  图 5.

Die photo of the photonic chip.
光子芯片的芯片照片。

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Fig. 6.  图 6.

Chip micrograph of the 128-channel low-speed DAC.
128 通道低速 DAC 的芯片显微照片。

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查看源 \begin{align*}&{U_1} = \left[ {\begin{array}{cccc} {{M_1}}&{}&{}&{} \\ {}&{{M_2}}&{}&{} \\ {}&{}& \ddots &{} \\ {}&{}&{}&{{M_8}} \end{array}} \right] \tag{7}\\& R = {U_4} \times {C_3} \times {U_3} \times {C_2} \times {U_2} \times {C_1} \times {U_1}\tag{8}\end{align*}

B. Simulink-based Platform
B. 基于 Simulink 的平台

The electro-optic modulator and thermal phase shifter within the photonic chip are modeled at the behavioral level according to the principle, while the remaining modules are modeled using components in Simscape. The Simulink platform diagram is illustrated in Fig. 4.
光子芯片内的电光调制器和热移相器根据该原理在行为层面进行建模，而其余模块则使用 Simscape 中的组件进行建模。Simulink 平台图如图 4 所示。

The ADC adopts the Flash ADC in the Simulink library and introduces Gaussian noise as the input referred noise. The DAC utilizes the Binary Weighted DAC from the library and introduces the output referred noise. The PD needs to take the real part of the optical signal output from the photonic chip and convert it to an electrical signal. A low-pass filter is employed in Simulink to model the bandwidth of the PD. Additionally, a gain module is utilized to represent the optoelectronic responsivity, and dark current noise is introduced at the output. A low-pass filter is used in TIA to represent the bandwidth, a gain module is used to represent the transconductance gain, and input referred current noise is added.
ADC 采用 Simulink 库中的 Flash ADC，并引入高斯噪声作为折合到输入端的噪声。DAC 利用库中的二进制加权 DAC 并引入折合到输出的噪声。PD 需要将光子芯片输出的光信号的实部转换为电信号。Simulink 中使用低通滤波器对 PD 的带宽进行建模。此外，增益模块用于表示光电响应度，并在输出端引入暗电流噪声。TIA 中使用低通滤波器来表示带宽，使用增益模块来表示跨导增益，并添加折合到输入端的电流噪声。

A. Photonic Chip Test A. 光子芯片测试

TABLE I Photonic Chip Performance
表 I 光子芯片性能

TABLE II The Influence of Non-Ideal Factors
表 II 非理想因素的影响

The die photo of the photonic chip is shown in Fig. 5, including electro-optic modulator, thermal phase shifter and photodetector, etc., with an overall area of 5 mm × 7.5 mm. Voltage values suitable for optical computing are obtained by modifying the gradient descent variable of the Pytorch framework. The convolutional layers required for the neural network are obtained by biasing voltages on the thermal phase-shifting array and tested in practice. The FPGA (XCZU29DR-ffvf1760-1-i) generates the required voltage values, the tunable laser (CBDX-SC-SC-SC-SC-FA) generates the light source, and the calculation results are converted by the TIA (LMH32401) and quantified by the FPGA. The photonic chip achieves a Top5 accuracy of 86.4% on the ImageNet image dataset.
光子芯片的芯片照片如图 5 所示，包括电光调制器、热移相器和光电探测器等，总面积为 5 mm × 7.5 mm。通过修改 Pytorch 框架的梯度下降变量来获得适合光学计算的电压值。神经网络所需的卷积层是通过对热相移阵列上的电压进行偏置来获得的，并在实践中进行了测试。FPGA （XCZU29DR-ffvf1760-1-i） 生成所需的电压值，可调谐激光器 （CBDX-SC-SC-SC-SC-FA） 生成光源，计算结果由 TIA （LMH32401） 转换并由 FPGA 量化。光子芯片在 ImageNet 图像数据集上实现了 86.4% 的 Top5 准确率。

B. Low-speed DAC Test B. 低速 DAC 测试

Fig. 6 presents the silicon die photograph of the prototype. The ranges of 128-channel outputs are all from 0 to 13V. The signal-to-noise ratio (SNR) is more than 40dB, and the conversion speed of DAC is more than 1Msps. By configuring the relevant PINs, the output can be performed in three modes: low voltage, high voltage (4×amplification) and high voltage (6×amplification). The power consumption of the whole chip is less than 3W.
图 6 显示了原型的硅晶片照片。128 通道输出的范围都是从 0 到 13V。信噪比 （SNR） 超过 40dB，DAC 的转换速度超过 1Msps。通过配置相关的 PIN，可以在三种模式下进行输出：低电压、高电压 （4×amp化） 和高电压 （6×amplification）。整个芯片的功耗小于 3W。

C. Simulink Simulation C. Simulink 仿真

The platform simulation is carried out under Simulink. Except for the photonic chip and the low-speed DAC extracting from tape-out tests, the remaining electrical peripheral circuits refer to the commercial chips. The high-speed ADC is referred to AD9094, the high-speed DAC is referred to AD9776A, and the TIA is referred to HMC799.
平台仿真在 Simulink 下进行。除了光子芯片和从流片测试中提取的低速 DAC 外，其余的电气外围电路都是指商用芯片。高速 ADC 称为 AD9094，高速 DAC 称为 AD9776A，TIA 称为 HMC799。

Fig. 7.  图 7.

Impact of non-ideal factors in adverse situations.
非理想因素在不利情况下的影响。

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Fig. 8.  图 8.

Impact of non-ideal factors on image classification test.
非理想因素对图像分类测试的影响。

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After setting the relevant non-ideal parameters, the effective number of bits (ENOB) of a single channel is measured to be 6.8-bit under the Nyquist frequency. An error analysis of the photonic matrix yields a mean square error of 2.6068×10^-5 V² and a relative error of 2.18%. The image quality was tested by adding salt-and-pepper noise to the input image and comparing the various error analyses with the ideal 4×4 mean filter to observe the filtering effect under the influence of non-ideal factors. The peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) index obtained from the test are shown in Table II.
设置相关的非理想参数后，在奈奎斯特频率下测得单个通道的有效位数 （ENOB） 为 6.8 位。光子矩阵的误差分析得出均方误差为 2.6068×^10-5 V²，相对误差为 2.18%。通过在输入图像中加入盐和胡椒噪声，并将各种误差分析与理想的 4×4 均值滤波器进行比较，以观察非理想因子影响下的滤波效果，从而测试图像质量。从测试中获得的峰值信噪比 （PSNR） 和结构相似性 （SSIM） 指数如表 II 所示。

Through Table II it can be visualized that the optical matrix error has the greatest impact on the filtering effect, but a relatively high-quality image can still be obtained. Next, the errors are enlarged to analyze the filtering effect in adverse case, and the obtained images are illustrated in Fig. 7.
通过表 II 可以直观地看到，光学矩阵误差对滤波效果的影响最大，但仍然可以获得相对高质量的图像。接下来，放大误差以分析不利情况下的滤波效果，所得图像如图 7 所示。

Fig. 8 depicts the impact of various non-ideal factors on the image classification results with the Modified National Institute of Standards and Technology (MNIST) database. Error1 is the noise of high-speed ADC, high-speed DAC, PD and TIA, error2 is the gain and offset error, error3 is the nonlinearity of the electro-optic modulator, error4 is the resolution of the low-speed DAC, and error5 is the noise of the low-speed DAC. It can be seen that with the continuous accumulation of non-ideal factors, the accuracy rate also decreases to varying degrees. Then each non-ideal factor is analyzed separately. The resolution and noise of the low-speed DAC have the greatest impact on the test results. The SNR of the low-speed DAC must be at least 52 dB to achieve an 80% image classification accuracy according to the test.
图 8 描述了使用修改后的美国国家标准与技术研究院 （MNIST） 数据库，各种非理想因素对图像分类结果的影响。误差 1 是高速 ADC、高速 DAC、PD 和 TIA 的噪声，误差 2 是增益和失调误差，误差 3 是电光调制器的非线性度，误差 4 是低速 DAC 的分辨率，误差 5 是低速 DAC 的噪声。由此可见，随着非理想因子的不断积累，准确率也不同程度地下降。然后分别分析每个非理想因子。低速 DAC 的分辨率和噪声对测试结果的影响最大。根据测试，低速 DAC 的 SNR 必须至少为 52 dB，才能达到 80% 的图像分类精度。