Unique Bias Stress Instability of Heterogeneous ${Ga}_{2} O_{3}$ -on-SiC MOSFET
异构 ${Ga}_{2} O_{3}$ on-SiC MOSFET 独特的偏置应力不稳定性

Chenyu Liu $^{\oplus}$ , Yibo Wang $^{\oplus}$ , Wenhui ${Xu}^{\oplus}$ , Member, IEEE, Xiaole Jia, Shuqi Huang,
刘 $^{\oplus}$ 晨宇，一 $^{\oplus}$ 博王，文辉 ${Xu}^{\oplus}$ ， IEEE成员，贾晓乐，黄淑琪，Yuewen Li, Bochang Li $^{\oplus}$ , Zhengdong Luo, Cizhe Fang, Yan Liu $^{\oplus}$ , Tiangui You, Xin Ou $^{\oplus}$ , Senior Member, IEEE, Yue Hao $^{\oplus}$ , Senior Member, IEEE, and Genquan Han $^{®}$ , Member, IEEE
李月文、李 $^{\oplus}$ 博昌、罗正东、方慈哲、刘燕 $^{\oplus}$ 、游天桂、欧欣 $^{\oplus}$ （Xin Ou）， IEEE高级会员，玥浩（Yue Hao $^{\oplus}$ ）， IEEE高级会员，韩根泉（Genquan Han $^{®}$ ）， IEEE 会员

Abstract 抽象

In this letter, we report on a unique positive bias stress (PBS) instability observed in the heterogeneous ${Ga}_{2} O_{3}$ -on-SiC (GaOSiC) metal-oxide-semiconductor fieldeffect transistor (MOSFET). The ${Ga}_{2} O_{3}$ layer in the GaOSiC MOSFET, which was fabricated using the ion implantation process, still contains hydrogen $(H)$ , leading to significantly different threshold voltage ( $V_{T H}$ ) shifts and on-resistance ( $R_{ON}$ ) variations compared to transistors on ${Ga}_{2} O_{3}$ bulk under PBS. During the initial several tens of seconds of PBS, the GaOSiC MOSFET exhibits a normal positive $V_{TH}$ shift, resulting from the capture of some electrons in the channel by border traps in the gate dielectric and interface traps. However, as the PBS time increases, the $V_{T H}$ of the GaOSiC transistor starts to shift in the negative direction. This can be attributed to the generation of shallow donors under PBS, with the presence of H , resulting in an increased carrier density ( $n_{e}$ ) in the ${Ga}_{2} O_{3}$ channel. The increased $n_{e}$ also leads to an improvement in drain current and a reduction in $R_{ON}$ of the GaOSiC MOSFET during long-term PBS. Our work provides new insights into the PBS instability of heterogeneous GaOSiC MOSFETs, particularly for high-power applications.
在这封信中，我们报告了在异构 ${Ga}_{2} O_{3}$ SiC 上（GaOSiC）金属氧化物半导体场效应晶体管（MOSFET）中观察到的独特正偏置应力（PBS）不稳定性。使用离子注入工艺制造的 GaOSiC MOSFET 中的 ${Ga}_{2} O_{3}$ 层仍然含有氢 $(H)$ ，导致与 PBS 下 ${Ga}_{2} O_{3}$ 体体晶体管相比，阈值电压（ $V_{T H}$ ）偏移和导通电阻（ $R_{ON}$ ）变化明显不同。在 PBS 的最初几十秒内，GaOSiC MOSFET 表现出正常的正 $V_{TH}$ 偏移，这是由于栅极电介质和界面陷阱中的边界陷阱捕获了通道中的一些电子。然而，随着 PBS 时间的增加，GaOSiC 晶体管 $V_{T H}$ 的 GaOSiC 晶体管开始向负方向移动。这可以归因于在 PBS 下产生浅供体，存在 H ，导致 ${Ga}_{2} O_{3}$ 通道中的载流子密度（ $n_{e}$ ）增加。在长期 PBS 期间，漏 $n_{e}$ 极电流的增加还导致漏极电流的改善和 GaOSiC MOSFET $R_{ON}$ 的减少。我们的工作为异构 GaOSiC MOSFET 的 PBS 不稳定性提供了新的见解，特别是对于高功率应用。

Index Terms-Gallium Oxide,

{Ga}_{2} O_{3}

, Heterogeneous,

{Ga}_{2} O_{3}

-on-SiC, GaOSiC, MOSFET, Positive Bias Stress.
索引项 - 氧化镓、

{Ga}_{2} O_{3}

、异质、

{Ga}_{2} O_{3}

-on-SiC、GaOSiC、MOSFET、正偏置应力。

I. INTRODUCTION I. 引言

GALLIUM oxide

({Ga}_{2} O_{3})

is currently attracting significant interest for its potential applications in the next generation of power devices, thanks to its high critical electric field and easily available large-scale substrate [1], [3]. With the
氧化

({Ga}_{2} O_{3})

镓由于其高临界电场和易于获得的大规模衬底，目前因其在下一代功率器件中的潜在应用而引起了人们的极大兴趣 [1]，[3]。使用

advancement of device architecture and process techniques, such as epitaxial growth, selective doping, source drain engineering, high-

κ

, and fin-channel, it is possible to boost the performance for

{Ga}_{2} O_{3}

metal-oxide semiconductor field-effect transistors (MOSFETs). However,

{Ga}_{2} O_{3}

has a thermal conductivity

κ

that is less than

1 / 10

of SiC [4], [5], which limits its applications in high-power electronics. In such cases, efficient heat dissipation is crucial for device performance and reliability. To address this low

κ

bottleneck problem in

{Ga}_{2} O_{3}

devices, a novel ion-cutting process has been developed to enable the wafer-scale heterogeneous

{Ga}_{2} O_{3}

-on-SiC (GaOSiC) substrate [6], [7].
器件架构和工艺技术的进步，如外延生长、选择性掺杂、源极漏极工程、高通道

κ

和鳍通道，可以提高

{Ga}_{2} O_{3}

金属氧化物半导体场效应晶体管（MOSFET）的性能。然而，

{Ga}_{2} O_{3}

它的导热系数

κ

小于

1 / 10

SiC [4]、[5]，这限制了它在高功率电子产品中的应用。在这种情况下，高效散热对于设备性能和可靠性至关重要。为了解决器件中的

{Ga}_{2} O_{3}

低

κ

瓶颈问题，人们开发了一种新颖的离子切割工艺，以实现晶圆级非均相

{Ga}_{2} O_{3}

SiC （GaOSiC）衬底 [6]，[7]。

To make

{Ga}_{2} O_{3}

MOSFETs practically applicable, it is crucial to address reliability issues, especially positive bias stress (PBS) instability, which can cause significant performance degradation over time, particularly under high-temperature and high-stress conditions. Threshold voltage shift

(Δ V_{TH})

induced by PBS is a common problem faced by wide bandgap transistors. Although, there have been few studies on PBS instability for bulk

{Ga}_{2} O_{3}

MOSFETs so far [8], [9], [10], [11]. It has been reported that the electrons trapped by border traps in gate dielectric can lead to a positive shift in the threshold voltage

(V_{TH})

. This issue is similar to the PBS instability problem faced by SiC MOSFETs [12], [13] and can be mitigated by optimizing the gate oxide thickness and improving its quality [14], [15], [16].
为了使

{Ga}_{2} O_{3}

MOSFET 实际适用，解决可靠性问题至关重要，尤其是正偏置应力（PBS）不稳定性，随着时间的推移，这可能会导致性能显着下降，尤其是在高温和高应力条件下。PBS 引起的阈值电压偏移

(Δ V_{TH})

是宽带隙晶体管面临的常见问题。虽然，到目前为止，关于体

{Ga}_{2} O_{3}

MOSFET 的 PBS 不稳定性的研究很少 [8]、[9]、[10]、[11]。据报道，栅极电介质中边界陷阱捕获的电子会导致阈值电压

(V_{TH})

发生正向偏移。这个问题类似于 SiC MOSFET 面临的 PBS 不稳定问题 [12]、[13]，可以通过优化栅极氧化层厚度和提高其质量来缓解 [14]、[15]、[16]。

Addressing PBS instability in heterogeneous GaOSiC transistors fabricated through the hydrogen

(H)

ion-cutting process is a complex issue. This is because H is inevitably incorporated into the

{Ga}_{2} O_{3}

channel during the ion-implantation process, and the interstitial H ion

(H_{i}^{+})

and H trapped at a Ga vacancy can act as donors [17], [18], [19]. Under the PBS effect, the configuration transition of

H_{i}^{+}

and H complexed with native defects can change, resulting in variations in carrier concentration in the

{Ga}_{2} O_{3}

channel and causing

Δ V_{TH}

. However, there is a lack of research on PBS instability in heterogeneous

{Ga}_{2} O_{3}

transistors.
解决通过氢

(H)

离子切割工艺制造的异构 GaOSiC 晶体管中的 PBS 不稳定性是一个复杂的问题。这是因为在离子注入过程中，H 不可避免地被整合到

{Ga}_{2} O_{3}

通道中，而被困在 Ga 空位的间隙 H 离子

(H_{i}^{+})

和 H 可以作为供体 [17]、[18]、[19]。在 PBS 效应下，与天然缺陷复合的

H_{i}^{+}

和 H 的构型跃迁会发生变化，导致

{Ga}_{2} O_{3}

通道中载流子浓度的变化，并导致

Δ V_{TH}

。然而，目前缺乏对异构

{Ga}_{2} O_{3}

晶体管中 PBS 不稳定性的研究。

In this work, we report our findings on the study of PBS instability for heterogeneous

{Ga}_{2} O_{3}

-on-SiC ( GaOSiC ) MOSFETs. We present the abnormal shift in

V_{TH}

and variation in on-resistance (

R_{ON}

) under PBS, and we also discuss the underlying mechanism causing this instability.
在这项工作中，我们报告了我们对异构

{Ga}_{2} O_{3}

on-SiC （GaOSiC ） MOSFET 的 PBS 不稳定性研究结果。我们介绍了 PBS 下导通电阻（

R_{ON}

）的异常变化

V_{TH}

和变化，我们还讨论了导致这种不稳定性的潜在机制。

II. EXPERIMENTAL DETAIL II. 实验细节

Fig. 1(a) illustrates the schematic of the

β - {Ga}_{2} O_{3}

channel MOSFET studied in this work. The device was fabricated on a GaOSiC substrate using ion-cutting and surface-activated
图 1（a）说明了本研究中研究的

β - {Ga}_{2} O_{3}

沟道 MOSFET 的原理图。该器件是在 GaOSiC 衬底上使用离子切割和表面活化制造的

Fig. 1. (a) Schematic of the GaOSiC MOSFET studied in this work. (b) Measure-stress-measure waveforms used for the PBS instability study.
图 1.（a）本研究中研究的 GaOSiC MOSFET 的原理图。（b）用于 PBS 不稳定性研究的测量-应力-测量波形。
bonding techniques to create a heterogeneous integrated

{Ga}_{2} O_{3}

wafer [6]. The starting GaOSiC wafer had a thickness of 180-200 nm and a carrier dopant concentration

(n_{e})

5 \times 10^{17} - 1.0 \times 10^{18} {cm}^{- 3}

in the top

{Ga}_{2} O_{3}

layer. The device mesa was defined using inductively coupled plasma etching, and the

S / D

regions were doped with

{Si}^{+}

implantation. The channel region was thinned down using

{BCl}_{3} / {Cl}_{2}

fixed gases. The thermal annealing was carried out for dopant activation.

Ti / Au S / D

metals were formed by a lift-off process followed by a thermal annealing at

470^{\circ} C

. A

50 - nm {Al}_{2} O_{3}

gate dielectric was deposited by thermal atomic layer deposition at

300^{\circ} C

, and the

Ni / Au

gate electrode was formed by the electron beam.
创建异构集成

{Ga}_{2} O_{3}

晶圆的键合技术 [6]。起始 GaOSiC 晶片的厚度为 180-200 nm，顶层

{Ga}_{2} O_{3}

的载流子掺杂剂浓度

(n_{e})

5 \times 10^{17} - 1.0 \times 10^{18} {cm}^{- 3}

为。使用电感耦合等离子体刻蚀定义器件台面，并通过

{Si}^{+}

注入掺杂区域

S / D

。使用

{BCl}_{3} / {Cl}_{2}

固定气体减薄通道区域。进行热退火以活化掺杂剂。

Ti / Au S / D

金属是通过剥离过程形成的，然后在进行热退火。

470^{\circ} C

通过热原子层沉积

300^{\circ} C

沉积栅

50 - nm {Al}_{2} O_{3}

极电介质，

Ni / Au

栅极电极由电子束形成。

The measurement methodology is illustrated in Fig. 1(b). First, the initial electrical characteristics were measured using a Keithley 4200A-SCS Parameter Analyzer. After applying positive gate bias stress (

V_{G, stress}

), the drain current (

I_{D}

) versus gate voltage

(V_{G})

curves,

I_{D}

versus drain voltage

(V_{D})

curves, and gate capacitance

(C_{G})

versus

V_{G}

curves of the device under test was measured within several seconds. The basic theory and method for

C_{G}

measurement can be found in the literature [20], [21]. The source and drain contacts were grounded during the stress phase. For a fixed

V_{G, stress}

value, a measure-stress-measure period was continuously performed, with stress duration increasing from 5 s to 50000 s . The 1 , 3 , and

5 V V_{G,stress}

conditions were applied to one device in sequence, with a 20 -hour recovery period between two

V_{G,stress}

conditions.
测量方法如图 1（b）所示。首先，使用 Keithley 4200A-SCS 参数分析仪测量初始电气特性。在施加正栅极偏置应力（

V_{G, stress}

）后，在几秒钟内测量了被测器件的漏极电流（

I_{D}

）与栅极电压

(V_{G})

曲线、

I_{D}

漏极电压

(V_{D})

曲线和栅极电容

(C_{G})

与

V_{G}

曲线的关系。

C_{G}

测量的基本理论和方法可以在文献中找到 [20]、[21]。源极和漏极触点在应力阶段接地。对于固定

V_{G, stress}

值，连续执行测量-应力-测量周期，应力持续时间从 5 秒增加到 50000 秒。将 1 、 3 和

5 V V_{G,stress}

条件按顺序应用于一台设备，两个

V_{G,stress}

条件之间有 20 小时的恢复期。

III. Results and Discussion
III. 结果与讨论

Figs. 2 show the bidirectional sweeping of the measured

I_{D}

versus

V_{G}

curves for a GaOSiC MOSFET under PBS at

V_{G,stress}

1 V, 3 V

, and 5 V . Fig. 3(a) shows the

V_{TH}

instability extracted from the

I_{D} - V_{G}

curves in Fig. 2.

V_{TH}

is defined as the

V_{G}

at an

I_{D}

0.1 mA / mm

. An abnormal shift in the

I_{D} - V_{G}

curve is observed:

V_{TH}

initially shifts in the positive direction and then shifts in the negative direction with increasing PBS time. Typically, under PBS conditions, a positive

Δ V_{TH}

is observed due to some electrons in the channel being captured in border traps in the

{Al}_{2} O_{3}

dielectric and interface traps [8], [9], [10], [11], [12], [13], [22], [23], [24], [25], [26]. As shown in Figs. 4(a) and (b), at a

t_{PBS}

of 50 s , some of interface and border states below Fermi level

(E_{F})

trap the electrons, causing interface energy bands bend upward. However, the abnormal negative

Δ V_{TH}

under PBS conditions has never been observed in

{Ga}_{2} O_{3}

Unique Bias Stress Instability of Heterogeneous Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3}-on-SiC MOSFET 异构 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} on-SiC MOSFET 独特的偏置应力不稳定性

Abstract 抽象

I. INTRODUCTION I. 引言

II. EXPERIMENTAL DETAIL II. 实验细节

III. Results and DiscussionIII. 结果与讨论

Unique Bias Stress Instability of Heterogeneous ${Ga}_{2} O_{3}$ -on-SiC MOSFET
异构 ${Ga}_{2} O_{3}$ on-SiC MOSFET 独特的偏置应力不稳定性

III. Results and Discussion
III. 结果与讨论