Unique Bias Stress Instability of Heterogeneous ${Ga}_{2} O_{3}$ -on-SiC MOSFET
异构 ${Ga}_{2} O_{3}$ on-SiC MOSFET 独特的偏置应力不稳定性

Chenyu Liu $^{\oplus}$ , Yibo Wang $^{\oplus}$ , Wenhui ${Xu}^{\oplus}$ , Member, IEEE, Xiaole Jia, Shuqi Huang,
刘 $^{\oplus}$ 晨宇，一 $^{\oplus}$ 博王，文辉 ${Xu}^{\oplus}$ ， IEEE成员，贾晓乐，黄淑琪，Yuewen Li, Bochang Li $^{\oplus}$ , Zhengdong Luo, Cizhe Fang, Yan Liu $^{\oplus}$ , Tiangui You, Xin Ou $^{\oplus}$ , Senior Member, IEEE, Yue Hao $^{\oplus}$ , Senior Member, IEEE, and Genquan Han $^{®}$ , Member, IEEE
李月文、李 $^{\oplus}$ 博昌、罗正东、方慈哲、刘燕 $^{\oplus}$ 、游天桂、欧欣 $^{\oplus}$ （Xin Ou）， IEEE高级会员，玥浩（Yue Hao $^{\oplus}$ ）， IEEE高级会员，韩根泉（Genquan Han $^{®}$ ）， IEEE 会员

Abstract 抽象

In this letter, we report on a unique positive bias stress (PBS) instability observed in the heterogeneous ${Ga}_{2} O_{3}$ -on-SiC (GaOSiC) metal-oxide-semiconductor fieldeffect transistor (MOSFET). The ${Ga}_{2} O_{3}$ layer in the GaOSiC MOSFET, which was fabricated using the ion implantation process, still contains hydrogen $(H)$ , leading to significantly different threshold voltage ( $V_{T H}$ ) shifts and on-resistance ( $R_{ON}$ ) variations compared to transistors on ${Ga}_{2} O_{3}$ bulk under PBS. During the initial several tens of seconds of PBS, the GaOSiC MOSFET exhibits a normal positive $V_{TH}$ shift, resulting from the capture of some electrons in the channel by border traps in the gate dielectric and interface traps. However, as the PBS time increases, the $V_{T H}$ of the GaOSiC transistor starts to shift in the negative direction. This can be attributed to the generation of shallow donors under PBS, with the presence of H , resulting in an increased carrier density ( $n_{e}$ ) in the ${Ga}_{2} O_{3}$ channel. The increased $n_{e}$ also leads to an improvement in drain current and a reduction in $R_{ON}$ of the GaOSiC MOSFET during long-term PBS. Our work provides new insights into the PBS instability of heterogeneous GaOSiC MOSFETs, particularly for high-power applications.
在这封信中，我们报告了在异构 ${Ga}_{2} O_{3}$ SiC 上（GaOSiC）金属氧化物半导体场效应晶体管（MOSFET）中观察到的独特正偏置应力（PBS）不稳定性。使用离子注入工艺制造的 GaOSiC MOSFET 中的 ${Ga}_{2} O_{3}$ 层仍然含有氢 $(H)$ ，导致与 PBS 下 ${Ga}_{2} O_{3}$ 体体晶体管相比，阈值电压（ $V_{T H}$ ）偏移和导通电阻（ $R_{ON}$ ）变化明显不同。在 PBS 的最初几十秒内，GaOSiC MOSFET 表现出正常的正 $V_{TH}$ 偏移，这是由于栅极电介质和界面陷阱中的边界陷阱捕获了通道中的一些电子。然而，随着 PBS 时间的增加，GaOSiC 晶体管 $V_{T H}$ 的 GaOSiC 晶体管开始向负方向移动。这可以归因于在 PBS 下产生浅供体，存在 H ，导致 ${Ga}_{2} O_{3}$ 通道中的载流子密度（ $n_{e}$ ）增加。在长期 PBS 期间，漏 $n_{e}$ 极电流的增加还导致漏极电流的改善和 GaOSiC MOSFET $R_{ON}$ 的减少。我们的工作为异构 GaOSiC MOSFET 的 PBS 不稳定性提供了新的见解，特别是对于高功率应用。

Index Terms-Gallium Oxide,

{Ga}_{2} O_{3}

, Heterogeneous,

{Ga}_{2} O_{3}

-on-SiC, GaOSiC, MOSFET, Positive Bias Stress.
索引项 - 氧化镓、

{Ga}_{2} O_{3}

、异质、

{Ga}_{2} O_{3}

-on-SiC、GaOSiC、MOSFET、正偏置应力。

I. INTRODUCTION I. 引言

GALLIUM oxide

({Ga}_{2} O_{3})

is currently attracting significant interest for its potential applications in the next generation of power devices, thanks to its high critical electric field and easily available large-scale substrate [1], [3]. With the
氧化

({Ga}_{2} O_{3})

镓由于其高临界电场和易于获得的大规模衬底，目前因其在下一代功率器件中的潜在应用而引起了人们的极大兴趣 [1]，[3]。使用

advancement of device architecture and process techniques, such as epitaxial growth, selective doping, source drain engineering, high-

κ

, and fin-channel, it is possible to boost the performance for

{Ga}_{2} O_{3}

metal-oxide semiconductor field-effect transistors (MOSFETs). However,

{Ga}_{2} O_{3}

has a thermal conductivity

κ

that is less than

1 / 10

of SiC [4], [5], which limits its applications in high-power electronics. In such cases, efficient heat dissipation is crucial for device performance and reliability. To address this low

κ

bottleneck problem in

{Ga}_{2} O_{3}

devices, a novel ion-cutting process has been developed to enable the wafer-scale heterogeneous

{Ga}_{2} O_{3}

-on-SiC (GaOSiC) substrate [6], [7].
器件架构和工艺技术的进步，如外延生长、选择性掺杂、源极漏极工程、高通道

κ

和鳍通道，可以提高

{Ga}_{2} O_{3}

金属氧化物半导体场效应晶体管（MOSFET）的性能。然而，

{Ga}_{2} O_{3}

它的导热系数

κ

小于

1 / 10

SiC [4]、[5]，这限制了它在高功率电子产品中的应用。在这种情况下，高效散热对于设备性能和可靠性至关重要。为了解决器件中的

{Ga}_{2} O_{3}

低

κ

瓶颈问题，人们开发了一种新颖的离子切割工艺，以实现晶圆级非均相

{Ga}_{2} O_{3}

SiC （GaOSiC）衬底 [6]，[7]。

To make

{Ga}_{2} O_{3}

MOSFETs practically applicable, it is crucial to address reliability issues, especially positive bias stress (PBS) instability, which can cause significant performance degradation over time, particularly under high-temperature and high-stress conditions. Threshold voltage shift

(Δ V_{TH})

induced by PBS is a common problem faced by wide bandgap transistors. Although, there have been few studies on PBS instability for bulk

{Ga}_{2} O_{3}

MOSFETs so far [8], [9], [10], [11]. It has been reported that the electrons trapped by border traps in gate dielectric can lead to a positive shift in the threshold voltage

(V_{TH})

. This issue is similar to the PBS instability problem faced by SiC MOSFETs [12], [13] and can be mitigated by optimizing the gate oxide thickness and improving its quality [14], [15], [16].
为了使

{Ga}_{2} O_{3}

MOSFET 实际适用，解决可靠性问题至关重要，尤其是正偏置应力（PBS）不稳定性，随着时间的推移，这可能会导致性能显着下降，尤其是在高温和高应力条件下。PBS 引起的阈值电压偏移

(Δ V_{TH})

是宽带隙晶体管面临的常见问题。虽然，到目前为止，关于体

{Ga}_{2} O_{3}

MOSFET 的 PBS 不稳定性的研究很少 [8]、[9]、[10]、[11]。据报道，栅极电介质中边界陷阱捕获的电子会导致阈值电压

(V_{TH})

发生正向偏移。这个问题类似于 SiC MOSFET 面临的 PBS 不稳定问题 [12]、[13]，可以通过优化栅极氧化层厚度和提高其质量来缓解 [14]、[15]、[16]。

Addressing PBS instability in heterogeneous GaOSiC transistors fabricated through the hydrogen

(H)

ion-cutting process is a complex issue. This is because H is inevitably incorporated into the

{Ga}_{2} O_{3}

channel during the ion-implantation process, and the interstitial H ion

(H_{i}^{+})

and H trapped at a Ga vacancy can act as donors [17], [18], [19]. Under the PBS effect, the configuration transition of

H_{i}^{+}

and H complexed with native defects can change, resulting in variations in carrier concentration in the

{Ga}_{2} O_{3}

channel and causing

Δ V_{TH}

. However, there is a lack of research on PBS instability in heterogeneous

{Ga}_{2} O_{3}

transistors.
解决通过氢

(H)

离子切割工艺制造的异构 GaOSiC 晶体管中的 PBS 不稳定性是一个复杂的问题。这是因为在离子注入过程中，H 不可避免地被整合到

{Ga}_{2} O_{3}

通道中，而被困在 Ga 空位的间隙 H 离子

(H_{i}^{+})

和 H 可以作为供体 [17]、[18]、[19]。在 PBS 效应下，与天然缺陷复合的

H_{i}^{+}

和 H 的构型跃迁会发生变化，导致

{Ga}_{2} O_{3}

通道中载流子浓度的变化，并导致

Δ V_{TH}

。然而，目前缺乏对异构

{Ga}_{2} O_{3}

晶体管中 PBS 不稳定性的研究。

In this work, we report our findings on the study of PBS instability for heterogeneous

{Ga}_{2} O_{3}

-on-SiC ( GaOSiC ) MOSFETs. We present the abnormal shift in

V_{TH}

and variation in on-resistance (

R_{ON}

) under PBS, and we also discuss the underlying mechanism causing this instability.
在这项工作中，我们报告了我们对异构

{Ga}_{2} O_{3}

on-SiC （GaOSiC ） MOSFET 的 PBS 不稳定性研究结果。我们介绍了 PBS 下导通电阻（

R_{ON}

）的异常变化

V_{TH}

和变化，我们还讨论了导致这种不稳定性的潜在机制。

II. EXPERIMENTAL DETAIL II. 实验细节

Fig. 1(a) illustrates the schematic of the

β - {Ga}_{2} O_{3}

channel MOSFET studied in this work. The device was fabricated on a GaOSiC substrate using ion-cutting and surface-activated
图 1（a）说明了本研究中研究的

β - {Ga}_{2} O_{3}

沟道 MOSFET 的原理图。该器件是在 GaOSiC 衬底上使用离子切割和表面活化制造的

Fig. 1. (a) Schematic of the GaOSiC MOSFET studied in this work. (b) Measure-stress-measure waveforms used for the PBS instability study.
图 1.（a）本研究中研究的 GaOSiC MOSFET 的原理图。（b）用于 PBS 不稳定性研究的测量-应力-测量波形。
bonding techniques to create a heterogeneous integrated

{Ga}_{2} O_{3}

wafer [6]. The starting GaOSiC wafer had a thickness of 180-200 nm and a carrier dopant concentration

(n_{e})

5 \times 10^{17} - 1.0 \times 10^{18} {cm}^{- 3}

in the top

{Ga}_{2} O_{3}

layer. The device mesa was defined using inductively coupled plasma etching, and the

S / D

regions were doped with

{Si}^{+}

implantation. The channel region was thinned down using

{BCl}_{3} / {Cl}_{2}

fixed gases. The thermal annealing was carried out for dopant activation.

Ti / Au S / D

metals were formed by a lift-off process followed by a thermal annealing at

470^{\circ} C

. A

50 - nm {Al}_{2} O_{3}

gate dielectric was deposited by thermal atomic layer deposition at

300^{\circ} C

, and the

Ni / Au

gate electrode was formed by the electron beam.
创建异构集成

{Ga}_{2} O_{3}

晶圆的键合技术 [6]。起始 GaOSiC 晶片的厚度为 180-200 nm，顶层

{Ga}_{2} O_{3}

的载流子掺杂剂浓度

(n_{e})

5 \times 10^{17} - 1.0 \times 10^{18} {cm}^{- 3}

为。使用电感耦合等离子体刻蚀定义器件台面，并通过

{Si}^{+}

注入掺杂区域

S / D

。使用

{BCl}_{3} / {Cl}_{2}

固定气体减薄通道区域。进行热退火以活化掺杂剂。

Ti / Au S / D

金属是通过剥离过程形成的，然后在进行热退火。

470^{\circ} C

通过热原子层沉积

300^{\circ} C

沉积栅

50 - nm {Al}_{2} O_{3}

极电介质，

Ni / Au

栅极电极由电子束形成。

The measurement methodology is illustrated in Fig. 1(b). First, the initial electrical characteristics were measured using a Keithley 4200A-SCS Parameter Analyzer. After applying positive gate bias stress (

V_{G, stress}

), the drain current (

I_{D}

) versus gate voltage

(V_{G})

curves,

I_{D}

versus drain voltage

(V_{D})

curves, and gate capacitance

(C_{G})

versus

V_{G}

curves of the device under test was measured within several seconds. The basic theory and method for

C_{G}

measurement can be found in the literature [20], [21]. The source and drain contacts were grounded during the stress phase. For a fixed

V_{G, stress}

value, a measure-stress-measure period was continuously performed, with stress duration increasing from 5 s to 50000 s . The 1 , 3 , and

5 V V_{G,stress}

conditions were applied to one device in sequence, with a 20 -hour recovery period between two

V_{G,stress}

conditions.
测量方法如图 1（b）所示。首先，使用 Keithley 4200A-SCS 参数分析仪测量初始电气特性。在施加正栅极偏置应力（

V_{G, stress}

）后，在几秒钟内测量了被测器件的漏极电流（

I_{D}

）与栅极电压

(V_{G})

曲线、

I_{D}

漏极电压

(V_{D})

曲线和栅极电容

(C_{G})

与

V_{G}

曲线的关系。

C_{G}

测量的基本理论和方法可以在文献中找到 [20]、[21]。源极和漏极触点在应力阶段接地。对于固定

V_{G, stress}

值，连续执行测量-应力-测量周期，应力持续时间从 5 秒增加到 50000 秒。将 1 、 3 和

5 V V_{G,stress}

条件按顺序应用于一台设备，两个

V_{G,stress}

条件之间有 20 小时的恢复期。

III. Results and Discussion
III. 结果与讨论

Figs. 2 show the bidirectional sweeping of the measured

I_{D}

versus

V_{G}

curves for a GaOSiC MOSFET under PBS at

V_{G,stress}

1 V, 3 V

, and 5 V . Fig. 3(a) shows the

V_{TH}

instability extracted from the

I_{D} - V_{G}

curves in Fig. 2.

V_{TH}

is defined as the

V_{G}

at an

I_{D}

0.1 mA / mm

. An abnormal shift in the

I_{D} - V_{G}

curve is observed:

V_{TH}

initially shifts in the positive direction and then shifts in the negative direction with increasing PBS time. Typically, under PBS conditions, a positive

Δ V_{TH}

is observed due to some electrons in the channel being captured in border traps in the

{Al}_{2} O_{3}

dielectric and interface traps [8], [9], [10], [11], [12], [13], [22], [23], [24], [25], [26]. As shown in Figs. 4(a) and (b), at a

t_{PBS}

of 50 s , some of interface and border states below Fermi level

(E_{F})

trap the electrons, causing interface energy bands bend upward. However, the abnormal negative

Δ V_{TH}

under PBS conditions has never been observed in

{Ga}_{2} O_{3}

bulk MOSFETs, as shown in the inset of Fig. 3(a). It is speculated that the negative

Δ V_{TH}

may be due to the increase in

n_{e}

in the channel region. This is attributed to the newly generated shallow donors in

{Ga}_{2} O_{3}

under PBS, as shown in Fig. 4©, which will be discussed in more detail later. Fig. 3(b) depicts the

Δ V_{TH}

for a

{Ga}_{2} O_{3}

device under PBS at elevated temperatures.

Δ V_{TH}

图 2 显示了 PBS 下 GaOSiC MOSFET 的测量

I_{D}

与

V_{G}

曲线的双向扫描，电压

V_{G,stress}

为

1 V, 3 V

，为，电压为 5 V。图 3（a）显示了从图 2 中的

I_{D} - V_{G}

曲线中提取的

V_{TH}

不稳定性。

V_{TH}

定义为

V_{G}

的的。

I_{D}

0.1 mA / mm

观察到

I_{D} - V_{G}

曲线的异常偏移：

V_{TH}

最初向正方向偏移，然后随着 PBS 时间的增加向负方向偏移。通常，在 PBS 条件下，由于通道中的一些电子被电介质和界面陷阱 [8]、[9]、[10]、[11]、[12]、[13]、[22]、[23]、[24]、[25]、[26] 的边界陷阱

{Al}_{2} O_{3}

捕获，因此观察到阳性

Δ V_{TH}

。如图 4（a）和（b）所示，在 a

t_{PBS}

为 50 s 时，一些低于费米能级

(E_{F})

的界面和边界态捕获了电子，导致界面能带向上弯曲。然而，在PBS条件下，从未在体状MOSFET中

{Ga}_{2} O_{3}

观察到异常负

Δ V_{TH}

离子，如图3（a）的插图所示。据推测，负面

Δ V_{TH}

可能是由于通道区域的增加

n_{e}

。这归因于 PBS 下

{Ga}_{2} O_{3}

新生成的浅供体，如图 4© 所示，稍后将更详细地讨论。图 3（b）描述了

Δ V_{TH}

在高温下使用 PBS 的

{Ga}_{2} O_{3}

装置。

Δ V_{TH}

Fig. 2. Bidirectional

I_{D} - V_{G}

for a GaOSiC MOSFET underwent PBS at different

V_{G, stress}

.
图 2.GaOSiC MOSFET 的双向

I_{D} - V_{G}

PBS 在不同的

V_{G, stress}

Fig. 3. (a)

V_{T H}

versus PBS time for a GaOSiC MOSFET device in Fig. 1.Inset compares the

_{1} V_{TH}

of GaOSiC MOSFET

(V_{G}

stress

= 5 V)

and bulk

{Ga}_{2} O_{3}

transistors under PBS. Devices in [9] and [10] had the

{Al}_{2} O_{3}

gate dielectric thicknesses of 25 nm and 30 nm , respectively, and were under the

V_{G,stress}

of 5 V and 4 V , respectively. (b)

1 V_{TH}

for a GaOSiC device under PBS at the elevated temperatures.
图 3.

V_{T H}

图 1 中 GaOSiC MOSFET 器件的 PBS 时间。插图比较

_{1} V_{TH}

了 PBS 下 GaOSiC MOSFET

(V_{G}

应力

= 5 V)

和体

{Ga}_{2} O_{3}

晶体管的应力。[9] 和 [10] 中的器件的

{Al}_{2} O_{3}

栅极介电厚度分别为 25 nm 和 30 nm，分别低于

V_{G,stress}

5 V 和 4 V。（b）

1 V_{TH}

对于高温下 PBS 下的 GaOSiC 器件。

Fig. 4. Schematics of the energy band diagrams of metal/

/ {Al}_{2} O_{3} / {Ga}_{2} O_{3}

under PBS at different

t_{PBS.}

(b) Electrons captured in border traps in the

{Al}_{2} O_{3}

dielectric and interface traps. © Increased

n_{e}

in the channel region due to the newly generated shallow donors in

{Ga}_{2} O_{3}

.
图 4.金属/

/ {Al}_{2} O_{3} / {Ga}_{2} O_{3}

在 PBS 下在不同

t_{PBS.}

（b）

{Al}_{2} O_{3}

电介质和界面陷阱的边界陷阱中捕获的电子的能带示意图。© 由于中新生成的浅给体，在通道区域中增加

n_{e}

{Ga}_{2} O_{3}

。

Fig. 5. Hysteresis evolution for GaOSiC transistor under PBS.
图 5.PBS 下 GaOSiC 晶体管的磁滞演变。
exhibits the same trend in changes at different temperatures. Initially, when the PBS time is zero,

V_{TH}

of the device is expected to shift towards the negative direction with increasing temperature due to thermally activated donor-induced carriers in the channel.
在不同温度下表现出相同的变化趋势。最初，当 PBS 时间为零时，

V_{TH}

由于通道中的热激活供体诱导载流子，预计设备会随着温度的升高而向负方向移动。

Fig. 5 illustrates the variation of hysteresis in the GaOSiC MOSFET under PBS. In this context, hysteresis is defined as the difference in

V_{TH}

between the forward and reverse sweeping of the

I_{D} - V_{G}

curves. The hysteresis is mainly caused by the trapping or detrapping of electrons by the interface states and defects in

{Ga}_{2} O_{3}

during the bidirectional sweeping. For a lower

V_{G, stress}

of 1 V , the hysteresis of the device on December 18,2024 at 06:29:05 UTC from IEEE Xplore. Restrictions apply.
图 5 说明了 PBS 下 GaOSiC MOSFET 的磁滞变化。在这种情况下，滞后定义为

I_{D} - V_{G}

曲线的正向和反向扫描

V_{TH}

之间的差异。磁滞主要是由于双向扫描

{Ga}_{2} O_{3}

过程中界面状态和缺陷对电子的俘获或去俘获引起的。对于 1 V 的较低

V_{G, stress}

值，该器件在 2024 年 12 月 18 日 06：29：05 UTC 的迟滞，来自 IEEE Xplore。限制条件适用。

Fig. 6. (a) Measured

C_{G} - V_{G}

and

1 / C_{G}^{2}

for GaOSiC transistor at different

t_{PBS}

. (b) Extracted

n_{e}

versus

W_{dep}

for the device.
图 6.（a）测量

C_{G} - V_{G}

和

1 / C_{G}^{2}

GaOSiC 晶体管在不同

t_{PBS}

。（b）提取与设备的提取

n_{e}

。

W_{dep}

remains stable with

t_{PBS}

for up to 500 seconds. However, with continuous stress, it starts to increase. Under a 5000-second PBS, the hysteresis of the device increases rapidly. For larger

V_{G,stress}

of 3 and 5 V , the hysteresis is much smaller, and the phenomenon of increased hysteresis with long

t_{PBS}

is significantly reduced compared to the

1 V V_{G, stress}

. It is speculated that the detrapping process of electrons by defects in

{Ga}_{2} O_{3}

produces the hysteresis, and a higher

V_{G,stress}

is not favorable for the occurrence of this process.
保持稳定

t_{PBS}

长达 500 秒。然而，随着持续的压力，它开始增加。在 5000 秒的 PBS 下，设备的滞后迅速增加。对于 3 V 和 5 V 的较大

V_{G,stress}

值，磁滞要小得多，并且与相比，滞后随时间

t_{PBS}

增加的现象显著减少

1 V V_{G, stress}

。据推测，电子被缺陷解陷的过程

{Ga}_{2} O_{3}

会产生磁滞，而更高的

V_{G,stress}

磁滞不利于这一过程的发生。

To gain a deeper understanding of the unique bias stress instability with long PBS time, the

n_{e}

in the

{Ga}_{2} O_{3}

channel was characterized using

C_{G}

curves for GaOSiC transistors under different PBS times. Fig. 6(a) illustrates the measured

C_{G}

and

1 / C_{G}^{2}

as a function of

V_{G}

for the GaOSiC MOSFETs under

V_{G,stress}

of 1 V . It is noted that, at the fixed

V_{G,stress}

of 1 V , the depletion capacitance increases with the

t_{PBS}

, particularly for a

t_{PBS}

up to 50000 s . By using the differential capacitance-voltage profile technique, the

n_{e}

versus depletion width (

W_{dep}

) in the

{Ga}_{2} O_{3}

channel is calculated by [21]:
为了更深入地了解长 PBS 时间下独特的偏置应力不稳定性，使用

C_{G}

不同 PBS 时间下 GaOSiC 晶体管的曲线对

{Ga}_{2} O_{3}

通道

n_{e}

中的偏差进行了表征。图 6（a）说明了 GaOSiC MOSFET 在 1 V 下的测量

C_{G}

结果和

1 / C_{G}^{2}

函数

V_{G}

。

V_{G,stress}

值得注意的是，在固定

V_{G,stress}

为 1 V 时，耗尽电容随而

t_{PBS}

增加，特别是长达

t_{PBS}

50000 s 。通过使用差分电容-电压曲线技术，通道中的

n_{e}

与耗尽宽度（

W_{dep}

）的关系由 [21]

{Ga}_{2} O_{3}

计算：

\begin{aligned} n_{e} (W_{dep}) & = - \frac{C_{G}^{3}}{q K_{s} ε_{0} A^{2} d C_{G} / d V_{G}} \\ = \frac{2}{q K_{s} ε_{0} A^{2} d (1 / C_{G}^{2}) / d V_{G}} \end{aligned}

and 和

W_{dep} = \frac{K_{s} ε_{0} A}{C_{G}}

where

n_{e} (W_{dep})

is the carrier density,

W_{dep}

is the depth from surface of metal and oxide,

K_{S}

is relative permittivity of the channel, and

A

is the area of contact.
其中

n_{e} (W_{dep})

是载流子密度，

W_{dep}

是金属和氧化物表面的深度，

K_{S}

是通道的相对介电常数，

A

是接触面积。

As shown in Fig. 6(b), the device exhibits an enhanced

n_{e}

when subjected to PBS. The increased

n_{e}

with bias stress is attributed to the fact that the implanted hydrogen (H) gives rise to shallow donors and leads to carrier recovery. Previous reports have shown that Ga vacancies

(V_{Ga})

{Ga}_{2} O_{3}

are deep acceptors, which can be passivated by H to form

V_{G - H}

shallow donors [17], [18]. Another possibility is that more charged interstitial

H (H_{i}^{+})

shallow donors are formed under PBS [18], [19]. The transition from

V_{Ga}

V_{G - H}

complex and the formation of

(H_{i}^{+})

under long-time bias stress contribute to the improved

n_{e}

but also introduce shallow-level impurities in the

{Ga}_{2} O_{3}

channel. The increase in

n_{e}

leads to the shift

V_{TH}

in negative direction, and results in the reduced

W_{dep}

{Ga}_{2} O_{3}

and the increased depletion capacitance. Both

n_{e}

and

W_{dep}

exhibit a consistent variation, while

V_{TH}

initially shows a positive shift followed by a negative shift. This behavior can be attributed to electron trapping dominating the positive

Δ V_{TH}

during the initial stage of PBS. As

t_{PBS}

increases further, the negative

Δ V_{TH}

is determined by the increased

n_{e}

.
如图 6（b）所示，该装置在受到 PBS 时表现出增强

n_{e}

。增加

n_{e}

的偏置应力归因于注入的氢（H）产生浅供体并导致载流子恢复。以前的报道表明，Ga 空位

(V_{Ga})

{Ga}_{2} O_{3}

是深受体，可以被 H 钝化形成

V_{G - H}

浅供体 [17]，[18]。另一种可能性是在PBS下形成更多的带电间

H (H_{i}^{+})

质浅供体[18]，[19]。从

V_{Ga}

V_{G - H}

到复合体的转变以及

(H_{i}^{+})

在长期偏置应力下形成有助于改善

n_{e}

，但也在

{Ga}_{2} O_{3}

通道中引入了浅层杂质。增加

n_{e}

导致负向偏移

V_{TH}

，并导致耗尽电容的减小

W_{dep}

{Ga}_{2} O_{3}

和增加。两者

n_{e}

W_{dep}

都表现出一致的变化，而

V_{TH}

最初显示正偏移，然后是负偏移。这种行为可归因于在 PBS 的初始阶段电子捕获主导阳性

Δ V_{TH}

。随着

t_{PBS}

的进一步增加，负

Δ V_{TH}

数由增加

n_{e}

的决定。

Fig. 7.

I_{D} - V_{G}

characteristics at

V_{G}

of 9 V under different bias stress condition of (a)

V_{G,stress} = 1 V

, (b)

V_{G,stress} = 3 V

and ©

V_{G,stress} =

5 V . (d)

R_{ON}

extracted from

I_{D} - V_{D}

curves as a function of

t_{PBS}

. (e)

I_{ON}

extracted from

/ I_{D} - V_{D}

curves at

V_{D}

of 10 V as a function of

t_{PBS}

.
图 7.

I_{D} - V_{G}

在（a）

V_{G,stress} = 1 V

、（b）

V_{G,stress} = 3 V

和 ©

V_{G,stress} =

5 V 不同偏置应力条件下 9 V 时的

V_{G}

特性。（d）

R_{ON}

从

I_{D} - V_{D}

曲线中提取为

t_{PBS}

的函数。（e）

I_{ON}

从

/ I_{D} - V_{D}

10 V 的

V_{D}

曲线中提取，作为的函数。

t_{PBS}

The

R_{ON}

and

I_{D}

variation under PBS with different

V_{G, stress}

R_{ON}

and

I_{D}

(at

V_{D} = 10 V

) instability versus the

t_{PBS}

at different

V_{G, stress}

. It is observed that

R_{ON}

slightly increases and

I_{D}

decreases from the initial to 5000s’ PBS, which is attributed to the generation of interface states and charged impurities in the

{Ga}_{2} O_{3}

channel. As the PBS time increases to 50000s, the device achieves improved

R_{ON}

and

I_{D}

performance, which is due to the increase in

n_{e}

in the channel region.

R_{ON}

I_{D}

表征了不同

V_{G, stress}

R_{ON}

和

I_{D}

（at

V_{D} = 10 V

）的不稳定性与

t_{PBS}

at 的不同

V_{G, stress}

。据观察，

R_{ON}

从初始到 5000 秒的 PBS 略有增加和

I_{D}

减少，这归因于

{Ga}_{2} O_{3}

通道中界面态和带电杂质的产生。随着 PBS 时间增加到 50000 秒，该设备实现了改进

R_{ON}

和性能

I_{D}

，这是由于通道区域的增加

n_{e}

。

From Figs. 3(a) and 7(d), it is observed that the negative shift of the

V_{TH}

and the reduction of the

R_{ON}

are less significant at higher

V_{G, stress}

compared to the previous lower

V_{G, stress}

. Moreover, when starting at a higher

V_{G, stress}

during testing, the initial

V_{TH} (R_{ON})

exhibits a right shift (an increase in magnitude) compared to the final

V_{TH} (R_{ON})

at a PBS time of 50000 s at a lower

V_{G, stress}

. This is because the configurational relaxations of

V_{Ga}

by H and

H_{i}^{+}

that contribute to the enhanced

n_{e}

are recovered, but only partially, during the 20 hours of recovery between different

V_{G,stress}

conditions. It is noted that the unique inflection point of

R_{ON}

and

I_{D}

of the device occurs at 5000 s compared to

V_{TH}

, i.e., 50 s . It is speculated that the formed impurities act as scattering centers leading to the degradation of channel mobility, which compensates the boosting effect of increased

n_{e}

on the drive current of the device.
从图 3（a）和 7（d）中可以观察到，与前一个较低的

V_{G, stress}

相比，在较高时

V_{G, stress}

the

V_{TH}

的负偏移和 the

R_{ON}

的减少不那么显著。此外，在测试过程中从较高的

V_{G, stress}

值开始时，与最终

V_{TH} (R_{ON})

值在 50000 s

V_{G, stress}

的 PBS 时间较低时相比，初始

V_{TH} (R_{ON})

值表现出右移（幅度增加）。这是因为在不同

V_{G,stress}

条件之间的 20 小时恢复期间，H 的构型松弛和有助于增强的

n_{e}

松弛

V_{Ga}

H_{i}^{+}

被恢复，但只是部分恢复。值得注意的是，该器件的

R_{ON}

和

I_{D}

的独特拐点发生在 5000 s 处，而

V_{TH}

则为 50 s。据推测，形成的杂质充当散射中心，导致沟道迁移率下降，从而补偿了增加

n_{e}

对器件驱动电流的增强效应。

IV. Conclusion 四、结论

In summary, we have investigated a unique PBS instability observed in GaOSiC MOSFETs. Our findings reveal that under long-term PBS, the presence of H in the

{Ga}_{2} O_{3}

layer can cause a transition from

V_{Ga}

deep acceptor to

V_{G - H}

shallow donor, as well as the formation of

H_{i}^{+}

donors. These factors contribute to an increase in the

n_{e}

in the

{Ga}_{2} O_{3}

channel, which leads to negative

V_{TH}

shifts and reduced

R_{ON}

in the device. This behavior has not been observed in

{Ga}_{2} O_{3}

bulk transistors. Our study sheds light on the mechanisms underlying PBS instability in heterogeneous GaOSiC MOSFETs and has important implications for the design and reliability of

{Ga}_{2} O_{3}

power devices.
总之，我们研究了在 GaOSiC MOSFET 中观察到的独特 PBS 不稳定性。我们的研究结果表明，在长期 PBS 下，

{Ga}_{2} O_{3}

层中存在 H 可导致从

V_{Ga}

深受体转变为

V_{G - H}

浅供体，以及供体的

H_{i}^{+}

形成。这些因素导致通道

n_{e}

增加，从而导致设备中的负

V_{TH}

偏移和减少

R_{ON}

。

{Ga}_{2} O_{3}

在体晶体管中

{Ga}_{2} O_{3}

未观察到这种行为。我们的研究阐明了异质 GaOSiC MOSFET 中 PBS 不稳定的机制，并对功率器件的设计

{Ga}_{2} O_{3}

和可靠性具有重要意义。

Manuscript received 18 May 2023; accepted 20 June 2023. Date of publication 23 June 2023; date of current version 26 July 2023. This work was supported by the National Natural Science Foundation of China under Grant 62293522, Grant 62204255, Grant 62234007, and Grant 62025402. The review of this letter was arranged by Editor Z. Ma. (Corresponding authors: Yibo Wang; Genquan Han.)
手稿于 2023 年 5 月 18 日收到;2023 年 6 月 20 日接受。发布日期 2023 年 6 月 23 日;当前版本的日期 2023 年 7 月 26 日。这项工作得到了中国国家自然科学基金 Grant 62293522、 Grant 62204255、 Grant 62234007 和 Grant 62025402 的支持。这封信的评论是由编辑Z. 马安排的。（通讯作者：Yibo Wang;韩根泉。

Chenyu Liu, Xiaole Jia, Shuqi Huang, Yan Liu, and Yue Hao are with the School of Microelectronics, Xidian University, Xi’an 710071, China.
Chenyu Liu、Xiaole Jia、Shuqi Huang、Yan Liu 和 Yue Hao 就职于中国习安710071西安电子科技大学微电子学院。

Yibo Wang is with the Suzhou Institute of Nano-Tech and NanoBionics, Chinese Academy of Sciences, Suzhou 215123, China (e-mail: wangyibo2576@gmail.com).
Yibo Wang 就职于中国科学院苏州纳米技术和纳米仿生研究所，中国苏州215123（电子邮件：wangyibo2576@gmail.com）。
Wenhui Xu, Tiangui You, and Xin Ou are with the State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China.
Wenhui Xu、Tiangui You 和 Xin Ou 就职于中国科学院上海微系统与信息技术研究所，信息学功能材料国家重点实验室，上海 200050。
Yuewen Li is with the Hangzhou Institute of Technology, Xidian University, Hangzhou 311200, China.
李月文就职于西安电子科技大学杭州理工学院，中国杭州 311200。
Bochang Li, Zhengdong Luo, Cizhe Fang, and Genquan Han are with the School of Microelectronics, Xidian University, Xi’an 710071, China, and also with the Hangzhou Institute of Technology, Xidian University, Hangzhou 311200, China (e-mail: gqhan@xidian.edu.cn).
Bochang Li、Zhengdong Luo、Cizhe Fang 和 Genquan Han 就职于西安电子科技大学微电子学院（中国710071习安 311200）（电子邮件：gqhan@xidian.edu.cn）。
Color versions of one or more figures in this letter are available at https://doi.org/10.1109/LED.2023.3288820.
这封信中一个或多个图形的彩色版本可在 https://doi.org/10.1109/LED.2023.3288820 获得。
Digital Object Identifier 10.1109/LED.2023.3288820
数字对象标识符 10.1109/LED.2023.3288820

Unique Bias Stress Instability of Heterogeneous Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3}-on-SiC MOSFET 异构 Ga 2 O 3 Ga 2 O 3 Ga_(2)O_(3)\mathrm{Ga}_{2} \mathrm{O}_{3} on-SiC MOSFET 独特的偏置应力不稳定性

Abstract 抽象

I. INTRODUCTION I. 引言

II. EXPERIMENTAL DETAIL II. 实验细节

III. Results and DiscussionIII. 结果与讨论

IV. Conclusion 四、结论

Unique Bias Stress Instability of Heterogeneous ${Ga}_{2} O_{3}$ -on-SiC MOSFET
异构 ${Ga}_{2} O_{3}$ on-SiC MOSFET 独特的偏置应力不稳定性

III. Results and Discussion
III. 结果与讨论