Understanding Bias Stress-Induced Instabilities in ALD-Deposited ZnO FeFETs Featuring $HZO - {Al}_{2} O_{3}$ - HZO Ferroelectric Stack
了解具有 $HZO - {Al}_{2} O_{3}$ - HZO 鐵電堆的 ALD 沉積氧化鋅鐵氧體電晶體中偏置應力誘發的不穩定性

Chen Sun $^{⊙}$ , Qiwen Kong $^{∙}$ , Graduate Student Member, IEEE, Gan Liu $^{\oplus}$ , Graduate Student Member, IEEE, Dong Zhang $^{\oplus}$ , Graduate Student Member, IEEE, Leming Jiao $^{\oplus}$ , Graduate Student Member, IEEE, Xiaolin Wang $^{∙}$ , Graduate Student Member, IEEE, Jishen Zhang, Haiwen Xu $^{∙}$ , Yang Feng, Rui Shao, Yue Chen, and Xiao Gong $^{∙}$
Chen Sun $^{⊙}$ , Qiwen Kong $^{∙}$ , Graduate Student Member, IEEE, Gan Liu $^{\oplus}$ , Graduate Student Member, IEEE, Dong Zhang $^{\oplus}$ , Graduate Student Member, IEEE、焦立明 $^{\oplus}$ , IEEE 研究生會員, 王曉林 $^{∙}$ , IEEE 研究生會員, 張吉申, 徐海文 $^{∙}$ , 馮楊, 邵瑞, 陳玥, 龔曉 $^{∙}$ .

Abstract 摘要

In this work, we investigate the threshold voltage ( $V_{T H}$ ) and memory window (MW) dynamics under positive and negative bias stress (PBS/NBS) in atomic layer deposition (ALD)-grown zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs). The gate stack is engineered by inserting an ${Al}_{2} O_{3}$ layer between Zr -doped ${HfO}_{2}$ (HZO) layers to form an $HZO - {Al}_{2} O_{3} - HZO$ configuration. This enhances the MW of ZnO FeFETs to 1.75 V compared to devices without the ${Al}_{2} O_{3}$ insertion. From bias stress characterizations, notable results are obtained, especially under NBS conditions. It is revealed that the generation of disorder state (DS) $O^{2 -}$ defects plays a key role when devices are stressed by negative bias, leading to an abnormal positive shift in $V_{TH}$ . Importantly, the degradation in MW caused by polarization pinning during NBS is mitigated by applying an even more negative bias. This can be explained by enhanced polarization erasing due to NBS. Our investigations provide a deep understanding of bias stress-induced instabilities in ALD-deposited ZnO FeFETs.
在這項工作中，我們研究了原子層沉積 (ALD) 生長的氧化鋅 (ZnO) 鐵電場效電晶體 (FeFET) 在正負偏壓 (PBS/NBS) 下的閾值電壓 ( $V_{T H}$ ) 和記憶視窗 (MW) 動態。閘極堆疊是透過在摻有 Zr 的 ${HfO}_{2}$ (HZO) 層之間插入 ${Al}_{2} O_{3}$ 層來形成 $HZO - {Al}_{2} O_{3} - HZO$ 配置。與沒有插入 ${Al}_{2} O_{3}$ 的元件相比，這將 ZnO FeFET 的 MW 增強到 1.75 V。偏置應力特性分析獲得了顯著的結果，尤其是在 NBS 條件下。結果顯示，當元件受到負偏壓時，無序狀態 (DS) $O^{2 -}$ 缺陷的產生扮演了關鍵的角色，導致 $V_{TH}$ 出現異常的正向偏移。重要的是，在 NBS 期間，由於極化釘造成的 MW 降級，會透過施加更負的偏壓而減緩。這可以用 NBS 所導致的極化擦除增強來解釋。我們的研究提供了對 ALD 沉積 ZnO FeFET 中偏壓應力誘發不穩定性的深入瞭解。

Index Terms-Ferroelectric field-effect transistors (FeFETs),

HZO - {Al}_{2} O_{3} - HZO

, negative bias stress (NBS), positive bias stress (PBS), zinc oxide (ZnO).
索引主題-鐵電場效電晶體 (FeFET)、

HZO - {Al}_{2} O_{3} - HZO

、負偏壓 (NBS)、正偏壓 (PBS)、氧化鋅 (ZnO)。

I. Introduction I.簡介

IN THE pursuit of enhancing device performance beyond poly-Si channels for 3D integration, oxide semiconductors (OS) deposited by atomic layer deposition (ALD) have emerged as one of the most promising channel materials due to the high uniformity, decent electron mobility, and low process temperature [1], [2], [3], [4]. OS channels are also viable for implementation in non-volatile ferroelectric field-effect transistors (FeFETs) [5], [6], [7], with doped

{HfO}_{2}

, particularly

{HfZrO}_{2}

(HZO), as the ferroelectric dielectric [8], [9], [10]. OS FeFETs offer compatibility with CMOS technology, high
為了提升 3D 整合多晶矽通道以外的元件效能，以原子層沉積 (ALD) 方式沉積的氧化物半導體 (OS) 因具有高均勻性、良好的電子遷移率以及低製程溫度等優點而成為最有前途的通道材料之一 [1]、[2]、[3]、[4]。OS 通道也可應用於非揮發性鐵電場效電晶體 (FeFET) [5]、[6]、[7]，以摻雜

{HfO}_{2}

，特別是

{HfZrO}_{2}

(HZO) 作為鐵電介質 [8]、[9]、[10]。OS FeFET 具有與 CMOS 技術相容、高

scalability, and play a significant role in shaping switching speed and power consumption [11], [12], [13].
可擴充性，並在塑造切換速度和功耗方面扮演重要角色 [11]、[12]、[13]。

Nevertheless, for OS FeFETs, the threshold voltage (

V_{TH}

) and memory window (MW) instabilities under positive and negative bias stress (PBS/NBS) gradually become challenges, especially when applied in 3D NAND, where the pass gate bias (

V_{PASS}

) induces PBS and the negative turn-off voltage (

V_{OFF}

) leads to NBS [Fig. 1(a)] [14], [15]. So far, strategies to improve the MW and cycling performance of OS FeFETs have been reported [16], [17], [18], [19]. However, the bias stressinduced

V_{TH}

and MW instabilities, as well as the underlying mechanisms in OS FeFETs, have not been comprehensively investigated.
儘管如此，對於 OS FeFET 而言，正負偏壓 (PBS/NBS) 下的閾值電壓 (

V_{TH}

) 和記憶體視窗 (MW) 不穩定性逐漸成為挑戰，尤其是當應用在 3D NAND 時，通過閘極偏壓 (

V_{PASS}

) 會誘發 PBS，而負關閉電壓 (

V_{OFF}

) 則會導致 NBS [圖 1(a)] [14], [15]。到目前為止，改善 OS FeFET 的 MW 和循環性能的策略已被報導 [16]、[17]、[18]、[19]。然而，偏壓應力誘發的

V_{TH}

和 MW 不穩定性，以及 OS FeFET 中的潛在機理，尚未得到全面的研究。
In this study, OS FeFETs with an ALD-deposited zinc oxide

(ZnO)

channel and an

HZO - {Al}_{2} O_{3} - HZO

ferroelectric stack are reported, achieving an enhanced MW of 1.75 V attributed to the insertion of

{Al}_{2} O_{3}

. Based on the MW-optimized ZnO FeFETs, bias stress characterizations are conducted. During PBS, it is observed that typical electron trapping effect dominates device behavior, resulting in a positive

V_{TH}

shift. This effect, combined with polarization pinning due to oxygen vacancies at the ferroelectric and channel interface, also leads to MW reduction. During NBS, the degradation in MW is caused by polarization pinning at the gate and ferroelectric interface. However, applying a more negative bias alleviates the MW degradation due to enhanced polarization erasing after NBS. Moreover, it is revealed that the abnormal positive

V_{TH}

shift under NBS can be explained by the generation of disorder state (DS)

O^{2 -}

defects.
本研究報告了具有 ALD 沉積氧化鋅

(ZnO)

通道和

HZO - {Al}_{2} O_{3} - HZO

鐵電堆疊的 OS FeFET，由於插入了

{Al}_{2} O_{3}

而實現了 1.75 V 的增強 MW。在 MW 最佳化 ZnO FeFET 的基礎上，進行了偏置應力特性分析。在 PBS 期間，觀察到典型的電子捕集效應主導裝置行為，導致

V_{TH}

正向偏移。此效應與鐵電體和通道介面上的氧空位所造成的極化釘(polarization pinning)結合，也會導致 MW 下降。在 NBS 期間，閘極和鐵電介面的極化釘滯會導致 MW 下降。然而，在 NBS 之後，由於極化擦除的增強，施加更多的負偏壓會減緩 MW 的劣化。此外，研究還發現在 NBS 下的異常正

V_{TH}

移動可以用無序狀態 (DS)

O^{2 -}

缺陷的產生來解釋。

II. MW Enhancement in ALD ZnO FeFETs
II.ALD 氧化鋅 FeFET 的 MW 增強

Fig. 1(b) illustrates the schematic of the ALD-deposited ZnO FeFET with a bottom-gate metal-ferroelectricsemiconductor (MFS) structure, and the ferroelectric layer is a stack of

HZO - {Al}_{2} O_{3} - HZO

. The process flow is shown in Fig. 1©. Here,

10 nm HZO (F_{A}), 15 nm HZO (F_{B})

, and the stack of

7 nm HZO / 2 nm Al I_{2} / 7 nm HZO (F_{C})

were deposited using ALD at

300^{\circ} C

in different samples for comparison. The ferroelectricity was stabilized by depositing W sacrificial capping layer, rapid thermal annealing (RTA) at

400^{\circ} C

for 60 s , and W removal. ZnO channel with a thickness of 7.5 nm was deposited by ALD at

150^{\circ} C

using

C_{4} H_{10} Zn

(DEZ) and

H_{2} O

as the precursors. Fig. 1(d)
圖1(b)為ALD-deposited ZnO FeFET的示意圖，其為底澆口金屬-鐵電半導體(MFS)結構，鐵電層為

HZO - {Al}_{2} O_{3} - HZO

的堆疊層。製程流程如圖 1© 所示。在此，

10 nm HZO (F_{A}), 15 nm HZO (F_{B})

，以及

7 nm HZO / 2 nm Al I_{2} / 7 nm HZO (F_{C})

的堆疊是使用 ALD 在

300^{\circ} C

處沉積在不同的樣品中，以作比較。透過沉積 W 犧牲封蓋層、在

400^{\circ} C

下快速熱退火 (RTA) 60 秒，並移除 W 來穩定鐵電性。以

C_{4} H_{10} Zn

(DEZ) 和

H_{2} O

為前體，透過 ALD 在

150^{\circ} C

沉積厚度為 7.5 nm 的 ZnO 通道。圖 1(d)

Fig. 1. (a) Typical

I_{D S} - V_{G S}

curves of OS FeFETs. Applying

V_{P A S S}

and

V_{OFF}

leads to PBS and NBS, respectively. (b) Schematic illustration of a ZnO FeFET. © Key process flow. (d) TEM image of the ZnO FeFET featuring the

HZO - {Al}_{2} O_{3} - HZO

ferroelectric stack.
圖 1. (a) OS FeFET 的典型

I_{D S} - V_{G S}

曲線。應用

V_{P A S S}

和

V_{OFF}

會分別導致 PBS 和 NBS。(b) ZnO FeFET 的示意圖。© 關鍵製程流程。(d) 以

HZO - {Al}_{2} O_{3} - HZO

鐵電堆為特色的 ZnO FeFET 的 TEM 影像。

(b)

2 P_{r}

(μ C / {cm}^{2})

+ V_{c}

(V)

- V_{c}

(V)

F_{A}

37.4

0.87

-1.48

F_{B}

11.7

1.31

-2.02

F_{C}

33.1

3.08

-3.87

Fig. 2. (a) Polarization loops of capacitors with 10 nm HZO, 15 nm HZO , and

HZO - {Al}_{2} O_{3} - HZO (7 nm / 2 nm / 7 nm)

. (b) Extracted

2 P_{r}

and

V_{c}

. ©

I_{DS} - V_{GS}

curves for FeFETs with various ferroelectrics. (d) Extracted MW. FeFET with the

HZO - {Al}_{2} O_{3} - HZO

stack shows an enhanced MW of 1.75 V .
圖 2. (a) 10 nm HZO、15 nm HZO 及

HZO - {Al}_{2} O_{3} - HZO (7 nm / 2 nm / 7 nm)

電容的極化迴路。 (b) 擷取的

2 P_{r}

及

V_{c}

. ©

I_{DS} - V_{GS}

具有各種鐵電性的 FeFET 曲線。(d) 擷取的 MW.具有

HZO - {Al}_{2} O_{3} - HZO

疊層的 FeFET 顯示出 1.75 V 的增強 MW .
presents the transmission electron microscopy (TEM) image of a ZnO FeFET with the

HZO - {Al}_{2} O_{3} - HZO

stack, revealing that the inserted

{Al}_{2} O_{3}

affects the crystallization of the two HZO layers and results in different grain orientations.
展示了具有

HZO - {Al}_{2} O_{3} - HZO

堆疊的 ZnO FeFET 的透射電子顯微鏡 (TEM) 圖像，揭示出插入的

{Al}_{2} O_{3}

會影響兩個 HZO 層的結晶，並導致不同的晶粒取向。

Capacitors with a

W /

ferroelectric

/ ZnO / Ni

structure and various ferroelectrics

(F_{A}, F_{B}

, and

F_{C})

were fabricated to extract remanent polarization

(P_{r})

and coercive voltage

(V_{c})

, especially

- V_{c}

, which are crucial for optimizing the MW of OS FeFETs. The polarization loops are depicted in Fig. 2(a), while Fig. 2(b) gives the

2 P_{r}

and

V_{c}

. The

HZO - {Al}_{2} O_{3} - HZO

stack achieves a larger

V_{c}

than the others and a high

2 P_{r}

33.1 μ C / {cm}^{2}

.
製作了具有

W /

鐵電

/ ZnO / Ni

結構和各種鐵電

(F_{A}, F_{B}

，以及

F_{C})

的電容，以提取剩餘極化

(P_{r})

和矯正電壓

(V_{c})

，尤其是

- V_{c}

，這對於優化 OS FeFET 的 MW 至關重要。圖 2(a) 描述了極化環路，而圖 2(b) 則給出了

2 P_{r}

和

V_{c}

。

HZO - {Al}_{2} O_{3} - HZO

堆疊達到比其他堆疊更大的

V_{c}

以及

33.1 μ C / {cm}^{2}

的高

2 P_{r}

。

The transfer characteristics (

I_{DS} - V_{GS}

) for FeFETs

(L_{CH} =

5 μ m

) with these ferroelectrics are illustrated in Fig. 2©. Fig. 2(d) shows the extracted MW. The ZnO FeFET with 10 nm HZO has a small MW due to the limitation of

- V_{c}

. As

V_{GS}

sweeps in reverse and approaches

- V_{c}

, the device switches to the erased state and turns off, restricting the programmed

V_{TH}

and MW [6], [20]. Then, increasing the HZO thickness to 15 nm increases

V_{c}

, but the drawback is the low

2 P_{r}

, and an even smaller MW is obtained. Notably, the ZnO FeFET with the

HZO - {Al}_{2} O_{3} - HZO

stack exhibits the largest MW of 1.75 V attributed to the decent

2 P_{r}

and

V_{c}

. Here, the electron tunneling through the inserted

{Al}_{2} O_{3}

is also believed to be a reason for the large MW, and further optimization of the HZO and

{Al}_{2} O_{3}

thicknesses can be conducted to achieve better performance [21].
使用這些鐵電體的 FeFET

(L_{CH} =

5 μ m

) 的傳輸特性 (

I_{DS} - V_{GS}

) 如圖 2© 所示。圖 2(d) 顯示了提取的 MW。由於

- V_{c}

的限制，具有 10 nm HZO 的 ZnO FeFET 的 MW 較小。當

V_{GS}

反向掃描並接近

- V_{c}

時，元件切換到擦除狀態並關閉，限制了燒錄的

V_{TH}

和 MW [6]、[20]。然後，將 HZO 厚度增加到 15 nm 會增加

V_{c}

，但缺點是

2 P_{r}

很低，而且會得到更小的 MW。值得注意的是，具有

HZO - {Al}_{2} O_{3} - HZO

疊層的 ZnO FeFET 顯示出 1.75 V 的最大 MW，這歸功於像樣的

2 P_{r}

和

V_{c}

。在此，電子透過插入的

{Al}_{2} O_{3}

的隧道作用也被認為是產生大 MW 的原因之一，可進一步優化 HZO 和

{Al}_{2} O_{3}

的厚度，以獲得更好的性能 [21]。

Fig. 3. (a) Endurance of ZnO FeFETs. (b) Measurement setup for PBS/NBS. ©

I_{DS} - V_{GS}

curves under PBS

(V_{STRESS} = 2 V)

for the device with an

L_{C H}

of 500 nm . (d)-(e) Extracted

V_{T H}

shift in programmed and erased states for ZnO FeFETs under different

V_{Stress. (f)} MW

change over stress time.
圖 3. (a) ZnO FeFET 的耐久性。(b) PBS/NBS 的量測設定。(d)-(e) ZnO FeFET 在不同

V_{Stress. (f)} MW

應力時間變化下，擷取的

V_{T H}

燒錄及擦除狀態的位移。

III. Evaluations of $V_{Th}$ and MW Under Bias Stress
III.偏壓下 $V_{Th}$ 與 MW 的評估

Fig. 3(a) shows the endurance of ZnO FeFETs, achieving high endurance of over

10^{8}

cycles. To stabilize the devices and ensure reliable results, PBS/NBS evaluations were conducted after 10 cycles. Fig. 3(b) shows the measurement setup, where

I_{DS} - V_{GS}

curves are obtained by DC sweeps ( -5.5 V to 5.5 V ) for

V_{TH}

and MW extraction. In addition to studying PBS/NBS for devices in erased state during stress (DC sweep ends in reverse), results for programmed state (DC sweep ends with a forward sweep) will also be discussed. Although DC sweeps would induce a recovery effect, this effect is applied uniformly across all devices and does not affect the validity of the overall trend.
圖 3(a) 顯示 ZnO FeFET 的耐久性，達到超過

10^{8}

循環的高耐久性。為了穩定元件並確保可靠的結果，在 10 次循環後進行 PBS/NBS 評估。圖 3(b) 顯示量測設定，其中

I_{DS} - V_{GS}

曲線是透過直流掃描 ( -5.5 V 至 5.5 V ) 獲得

V_{TH}

和 MW 抽取。除了研究器件在應力期間處於擦除狀態 (直流掃描以反向結束) 時的 PBS/NBS 外，還會討論編程狀態 (直流掃描以正向掃描結束) 的結果。雖然直流掃描會誘發恢復效應，但此效應均勻地應用於所有裝置，並不會影響整體趨勢的有效性。

The

V_{TH}

is defined using the constant current method at a current level of

W_{CH} / L_{CH} \times 10^{- 7} A

, where

W_{CH}

is the channel width. The MW is the difference between the

V_{TH}

values of the erased and programmed states. Fig. 3© depicts the measured

I_{DS} - V_{GS}

curves under PBS with a stress voltage (

V_{STRESS}

) of 2 V after various stress times for a ZnO FeFET with a

W_{CH}

5 μ m

and an

L_{CH}

of 500 nm . In the programmed

I_{DS} - V_{GS}

curves, the positive shift in the on-state region is more noticeable than in the subthreshold region. This could be due to contact effects and the reduced effectiveness of polarization switching in assisting the device to turn off as the

V_{TH}

moves away from

- V_{c}

V_{TH}

是使用定電流方法在

W_{CH} / L_{CH} \times 10^{- 7} A

的電流等級下定義的，其中

W_{CH}

是通道寬度。MW 是擦除狀態和燒錄狀態的

V_{TH}

值之差。圖 3© 描述在不同應力時間後，應力電壓 (

V_{STRESS}

) 為 2 V 的 PBS 下，對於

W_{CH}

為

5 μ m

且

L_{CH}

為 500 nm 的 ZnO FeFET 所測得的

I_{DS} - V_{GS}

曲線。在燒錄的

I_{DS} - V_{GS}

曲線中，導通區域的正向偏移比次閥值區域更為明顯。這可能是由於接觸效應，以及當

V_{TH}

遠離

- V_{c}

時，極化切換在協助裝置關閉方面的效能降低所致。

The extracted

V_{TH}

shifts

(Δ V_{TH})

in the programmed state (low

V_{TH}

) and erased state (high

V_{TH}

) are provided in Fig. 3(d) and Fig. 3(e), respectively. The

V_{StRESS}

values of 1 V and 3 V are also included, simulating the cases of

V_{PASS} = 1, 2, 3 V

. Fig. 3(f) shows the corresponding MW change (

Δ MW

). These device behaviors under PBS can be explained by the well-known electron trapping effect.
圖 3(d) 和圖 3(e) 分別提供了在燒錄狀態 (低

V_{TH}

) 和擦除狀態 (高

V_{TH}

) 下提取的

V_{TH}

移位

(Δ V_{TH})

。還包括

V_{StRESS}

值為 1 V 和 3 V，模擬

V_{PASS} = 1, 2, 3 V

的情況。圖 3(f) 顯示相對應的 MW 變化 (

Δ MW

)。這些在 PBS 下的元件行為可以用眾所周知的電子俘虜效應來解釋。
Typically, PBS traps electrons at the ferroelectric and channel interface or within the ferroelectric, reducing carrier concentration in the channel and shifting

V_{TH}

positively. Meanwhile, oxygen vacancies are generated in the ferroelectric and move to the ferroelectric and channel interface, where they
通常，PBS 會在鐵電和通道介面或鐵電體內捕集電子，降低通道中的載子濃度，並使

V_{TH}

正向移動。與此同時，氧空位會在鐵電體中產生，並移動到鐵電體和通道介面，並在那裡

Fig. 4. (a)

I_{D S} - V_{G S}

curves under NBS (

V_{STRESS} = - 3 V

). (b)-© Extracted

V_{TH}

shift in programmed state and erased state for devices under NBS with different

V_{STRESS}

, showing a positive shift. (d) Corresponding MW change over stress time. At more negative bias, the degradation of MW is less.
圖 4. (a) NBS 下的

I_{D S} - V_{G S}

曲線 (

V_{STRESS} = - 3 V

)。(b)-© 在 NBS 下不同

V_{STRESS}

的裝置，擷取的

V_{TH}

在燒錄狀態和刪除狀態的移位，顯示出正的移位。(d) 應力時間內相對應的 MW 變化。在較負的偏壓下，MW 的退化程度較小。

Fig. 5. (a) Energy band diagrams at

V_{G S} = 0 V

and NBS. Generated DS

O^{2 -}

defects during NBS dominate the positive

V_{TH}

shift. (b) Polarization pinning at gate and ferroelectric (Fe) interface leads to MW reduction. © NBS increases the switching probability of the dipoles under the center channel.
圖 5. (a)

V_{G S} = 0 V

與 NBS 時的能帶圖。在 NBS 期間產生的 DS

O^{2 -}

缺陷支配了

V_{TH}

的正向偏移。(b) 閘極和鐵電 (Fe) 介面的極化箝位會導致 MW 下降。NBS 會增加中心通道下偶極子的切換概率。

Fig. 6. (a) MW change after

10^{3}

s and NBS, showing clear repeatability. (b) Retention of devices before stress, after PBS, and after NBS.
圖 6. (a)

10^{3}

秒和 NBS 之後的 MW 變化，顯示明顯的重複性。(b) 應力前、PBS 後及 NBS 後裝置的保留。
pin the ferroelectric domains in a particular orientation [22], [23]. The pinning effect inhibits polarization switching under external electric fields. This is another reason for MW reduction in addition to the electron trapping. Such

V_{TH}

and MW instabilities are more severe at higher

V_{STRESS}

. Similar results are observed when devices are in programmed state during PBS, but the

V_{TH}

and MW changes are more pronounced than in the erased state at the same

V_{STRESS}

due to the higher overdrive stress voltage (

V_{OV} = V_{STRESS} - V_{TH}

).
將鐵電域固定在特定的方向上 [22]、[23]。釘住效應會抑制外部電場下的極化轉換。除了電子俘縱之外，這是造成 MW 減少的另一個原因。這種

V_{TH}

和 MW 不穩定性在

V_{STRESS}

較高時更為嚴重。當裝置在 PBS 期間處於燒錄狀態時，也會觀察到類似的結果，但在相同的

V_{STRESS}

下，由於過度驅動應力電壓 (

V_{OV} = V_{STRESS} - V_{TH}

) 較高，所以

V_{TH}

和 MW 的變化比在擦除狀態時更明顯。

Fig. 4(a) shows the

I_{DS} - V_{GS}

curves of the device under NBS with a

V_{STRESS}

of -3 V . Interestingly, unlike the negative

V_{TH}

shift reported by previous studies [24], [25], which is mainly due to oxygen vacancy ionization, the ZnO FeFETs exhibit an abnormal positive

V_{TH}

Δ V_{TH}

in the programmed state and erased state, respectively. The corresponding

Δ MW

is depicted in Fig. 4(d). For the positive shifted

V_{TH}

, one possible reason is the hole trapping effect. However, the ZnO channel in this work is an n-type OS, and holes can hardly drift to the ferroelectric and channel interface due to the low hole mobility.
圖 4(a) 顯示裝置在 NBS 下的

I_{DS} - V_{GS}

曲線，其中

V_{STRESS}

為 -3 V。有趣的是，有別於先前研究[24]、[25]所報告的主要由於氧空位電離所造成的負向

V_{TH}

漂移，氧化鋅 FeFET 在 NBS 條件下呈現異常的正向

V_{TH}

Δ V_{TH}

。圖 4(d) 描述了相對應的

Δ MW

。對於正偏移的

V_{TH}

，一個可能的原因是空穴陷阱效應。然而，本工作中的 ZnO 溝道是 n 型 OS，由於空穴遷移率低，空穴幾乎無法漂移到鐵電和溝道介面。

Hence, this positive

V_{TH}

shift under NBS is more likely due to the generation of disorder state (DS)

O^{2 -}

defects [26], [27].
因此，在 NBS 下，這種

V_{TH}

正向偏移更可能是由於產生無序狀態 (DS)

O^{2 -}

缺陷 [26]、[27]。

As illustrated in Fig. 5(a), more DS

O^{2 -}

defects, located in the lower-half band of the ZnO channel, are generated during NBS. The DS O

^{2 -}

defects act as acceptor-like traps and can capture electrons, thus causing the

V_{TH}

to shift positively. Oxygen vacancy ionization, which typically requires negative bias illumination stress (NBIS), plays a minor role here. Furthermore, the decrease in MW can also be understood by polarization pinning. In this case, oxygen vacancies are located at the gate and ferroelectric interface after NBS [Fig. 5(b)].
如圖 5(a) 所示，在 NBS 期間會產生更多位於 ZnO 通道下半頻帶的 DS

O^{2 -}

缺陷。DS O

^{2 -}

缺陷扮演類似受體陷阱的角色，可以捕捉電子，因此會導致

V_{TH}

正向移動。通常需要負偏置照明應力 (NBIS) 的氧空位電離在此扮演次要角色。此外，MW 的降低也可以用極化引腳 (polarization pinning) 來理解。在這種情況下，氧空位位於 NBS 後的閘極與鐵電界面 [圖 5(b)]。
Notably, a more negative stress voltage alleviates the MW degradation, which is opposite to the PBS case. To understand this phenomenon, it is necessary to mention the weak erasing issue in OS FeFETs. During erasing, due to the lack of high-mobility holes and the depletion of channel, polarization is more difficult to switch compared to programming. This can even result in the dipoles below the center of the channel failing to switch during erasing, causing the measured MW to be smaller than the actual MW of the device. One solution is to scale down the

L_{CH}

to reduce the areas with weaker electric field distribution in the center of the channel [19].
值得注意的是，較負的應力電壓會減緩 MW 劣化，這與 PBS 的情況相反。要了解這個現象，就必須提到 OS FeFET 的弱擦除問題。在擦除過程中，由於缺乏高遷移率的空穴以及通道的耗竭，極化相較於燒錄更難切換。這甚至會導致通道中心以下的偶極子在擦除期間無法切換，造成量測的 MW 小於元件的實際 MW。解決方法之一是縮小

L_{CH}

，以減少通道中心電場分佈較弱的區域 [19]。

Although the stress voltage in NBS does not reach the erasing voltage, the long-time bias stress increases the switching probability of the dipoles under the center channel, leading to the hard-to-switch dipoles to switch and thereby compensating the MW reduction caused by the polarization pinning effect [Fig. 5©]. That is the reason for the alleviation of MW degradation under a more negative stress. Fig. 6(a) presents the MW change after 1000 s under NBS for more measured devices, exhibiting clear repeatability.
雖然在 NBS 中的應力電壓並未達到擦除電壓，但長時間的偏壓應力增加了中心通道下偶極子的切換機率，使得難以切換的偶極子得以切換，進而補償了極化釘住效應所造成的 MW 下降[圖 5©]。這也是在較負的應力下減緩 MW 衰減的原因。圖 6(a)顯示更多量測裝置在 NBS 下 1000 秒後的 MW 變化，顯示出明顯的重複性。

Additionally, the alleviation of MW change and the positive

V_{TH}

shift are also obtained when devices are in the programmed state during NBS. Compared to the results shown in Fig. 4(b) to Fig. 4(d), the

V_{TH}

shift is smaller, and the MW degradation is greater at the same

V_{STRESS}

. In addition to the difference in

V_{OV}

, the increased MW degradation is partly due to the following reverse DC sweep ( 5.5 V to -5.5 V ) after stress, which slightly offsets the benefits gained from NBS.
此外，當裝置在 NBS 期間處於燒錄狀態時，也會得到 MW 變化的緩和以及

V_{TH}

正向偏移。相較於圖 4(b) 至圖 4(d) 所示的結果，在相同的

V_{STRESS}

下，

V_{TH}

的偏移較小，而 MW 的衰減較大。除了

V_{OV}

的差異之外，MW 退化增加的部分原因是應力之後的反向直流掃描 (5.5 V 至 -5.5 V)，這稍微抵銷了從 NBS 獲得的好處。
Fig. 6(b) shows the retention results of ZnO FeFETs before stress, after PBS (

V_{STRESS} = 2 V

), and after NBS

(V_{STRESS} =

-3 V ). Despite the

V_{TH}

shifts caused by stress, the retention results have a relatively similar trend, possibly due to the combined effects of polarization loss and stress recovery.
圖 6(b) 顯示 ZnO FeFET 在應力前、PBS 後 (

V_{STRESS} = 2 V

) 以及 NBS 後

(V_{STRESS} =

-3 V ) 的保持結果。儘管應力會造成

V_{TH}

的偏移，但保持結果的趨勢相對類似，這可能是由於極化損失和應力恢復的共同影響。

Here, we focus on revealing the degradation mechanism in ZnO FeFET under bias stress. Further studies on passivation and interface engineering should be conducted to improve the

V_{TH}

and MW stabilities. Additionally, it should be noted that the electron tunneling through the

{Al}_{2} O_{3}

in the ferroelectric stack is ignored in the analysis because the stress voltage is low, and the tunneling effect is reversible in the following high-voltage DC sweep after bias stress.
在此，我們著重於揭示 ZnO FeFET 在偏壓應力下的退化機制。為了改善

V_{TH}

和 MW 的穩定性，應進一步研究鈍化和介面工程。此外，需要注意的是，由於應力電壓較低，且在偏壓應力之後的高壓直流掃描中，隧道效應是可逆的，因此在分析中忽略了電子通過鐵電堆疊中

{Al}_{2} O_{3}

的隧道效應。

IV. CONCLUSION IV.結論

The bias stress-induced instabilities in MW-optimized ZnO FeFETs featuring the

HZO - {Al}_{2} O_{3} - HZO

ferroelectric stack are explored. A positive

V_{TH}

shift is observed in both PBS and NBS cases, attributed to the electron trapping and the generation of DS O

^{2 -}

defects, respectively. Electron trapping, coupled with the polarization pinning effect, results in a reduction in MW under PBS. Importantly, during NBS, we found that MW reduction due to the polarization pinning can be mitigated by applying a more negative bias.
本研究探討了具有

HZO - {Al}_{2} O_{3} - HZO

鐵電堆的 MW 優化 ZnO FeFET 中偏置應力誘發的不穩定性。在 PBS 和 NBS 的情況下，都觀察到

V_{TH}

的正向偏移，分別歸因於電子捕集和 DS O

^{2 -}

缺陷的產生。電子捕集加上極化釘住效應，導致 PBS 下的 MW 減少。重要的是，在 NBS 期間，我們發現由於極化釘鎖效應導致的 MW 減少可以透過施加較負的偏壓來減緩。

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Received 6 September 2024; accepted 15 September 2024. Date of publication 18 September 2024; date of current version 24 October 2024. This work was supported in part by the National Research Foundation (NRF) Singapore, under its Quantum Engineering Programme 1.0 Projects (QEP-P3), Ministry of Education (MOE) (Singapore) Tier 2 Academic Research Grant MOE-T2EP50221-0008; and in part by the MOE Tier 1 under Grant A-8001168-00-00. The review of this letter was arranged by Editor G. Han. (Corresponding author: Xiao Gong.)
收到日期：2024 年 9 月 6 日；接受日期：2024 年 9 月 15 日。發表日期：2024 年 9 月 18 日；目前版本日期：2024 年 10 月 24 日。本研究部分由新加坡國家研究基金會 (NRF) 量子工程計畫 1.0 項目 (QEP-P3)、教育部 (MOE) (新加坡) 第 2 階層學術研究補助金 MOE-T2EP50221-0008 所資助；部分由教育部第 1 階層補助金 A-8001168-00-00 所資助。這封信的審閱工作由編輯 G. Han 安排。(通訊作者：龔曉)
The authors are with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (e-mail: elegong@nus.edu.sg).
作者為新加坡國立大學電機與電腦工程系，新加坡 117576 (電子郵件：elegong@nus.edu.sg)。
Color versions of one or more figures in this letter are available at https://doi.org/10.1109/LED.2024.3462933.
本信中一個或多個圖表的彩色版本可在 https://doi.org/10.1109/LED.2024.3462933 上獲得。
Digital Object Identifier 10.1109/LED.2024.3462933
數位物件識別碼 10.1109/LED.2024.3462933

Abstract 摘要

I. Introduction I.簡介

II. MW Enhancement in ALD ZnO FeFETsII.ALD 氧化鋅 FeFET 的 MW 增強

III. Evaluations of V Th V Th V_(Th)\mathrm{V}_{\mathrm{Th}} and MW Under Bias StressIII.偏壓下 V Th V Th V_(Th)\mathrm{V}_{\mathrm{Th}} 與 MW 的評估

IV. CONCLUSION IV.結論

References 參考資料

II. MW Enhancement in ALD ZnO FeFETs
II.ALD 氧化鋅 FeFET 的 MW 增強

III. Evaluations of $V_{Th}$ and MW Under Bias Stress
III.偏壓下 $V_{Th}$ 與 MW 的評估