by 由

Man Lok Joshua Chung

A thesis submitted in conformity with the requirements
根据要求提交的论文

for the degree of Master of Applied Science
申请应用科学硕士学位

Graduate Department of Electrical and Computer Engineering
电气与计算机工程研究生部

University of Toronto 多伦多大学

(C) Copyright by Man Lok Joshua Chung 2016
(C) 版权所有：Man Lok Joshua Chung 2016

2016

I would like to express my deep and sincere gratitude to my research supervisor, Professor Wai Tung Ng for pointing me to the exciting topic of Class D audio amplifiers, and for his guidance and support through the courses of this research.
在此，我要向我的研究导师 Wai Tung Ng 教授表示深深而诚挚的谢意，感谢他将我引向 D 类音频放大器这一令人兴奋的课题，感谢他在本研究过程中给予的指导和支持。
I have enjoyed working in the Smart Power Integration & Semiconductor Devices Research Group under this leadership. His knowledge and vision in power electronics and audio amplifiers has been invaluable for my career development.
在他的领导下，我在智能功率集成与半导体器件研究组工作得非常愉快。他在电力电子和音频放大器方面的知识和远见对我的职业发展非常宝贵。

I would also like to thank my fellow graduate students and researchers for many discussions and insights over the courses for this research. Robert McKenzie and Rophina Li
我还要感谢我的研究生同学和研究人员，他们在本研究课程中进行了多次讨论，并提出了许多真知灼见。罗伯特-麦肯齐（Robert McKenzie）和李若菲娜（Rophina Li

worked closely with me on the topic of Class D audio amplifiers. Additional thanks to goes to Weijia Zhang, Tae Young Goh, Jingxuan Chen, Jingshu Yu, Mengqi Wang and Andrew Shorten who provided with valuable feedbacks.
在 D 类音频放大器的课题上与我密切合作。此外，还要感谢张维佳、Tae Young Goh、陈景轩、于静姝、王梦琪和 Andrew Shorten，他们为我提供了宝贵的反馈意见。

I would like to express my sincere gratitude towards GaN Systems Inc. for providing the device samples for this research. Iain Scott and Hughes Lafontaine have provided many answers to the questions about the GaN device samples.
我衷心感谢氮化镓系统公司（GaN Systems Inc.Iain Scott 和 Hughes Lafontaine 为我解答了许多有关氮化镓器件样品的问题。

Finally, I would like to thank my family, my parents Sandra and Edwin as well as my brother Jonathan would support and encouragement through all my endeavors.
最后，我要感谢我的家人，我的父母桑德拉和埃德温以及我的兄弟乔纳森在我的所有努力中给予我的支持和鼓励。

Acknowledgments ..... iii
致谢 ..... iii
List of Tables ..... vi
表格清单 ..... vi
List of Figures ..... vii
图表目录 ..... vii
List of Glossary ..... xii
词汇表 .....xii
1 Introduction ..... 1 1 简介 .....1
1.1 Class D Amplifiers ..... 3
1.1 D 类放大器 .....3
1.2 Thesis Organization ..... 4
1.2 论文组织 .....4
2 Background ..... 5 2 背景 .....5
2.1 Operations of Class D Amplifier ..... 5
2.1 D 类放大器的运行 .....5
2.1.1 Half Bridge Configuration ..... 6
2.1.1 半桥配置 ..... 6
2.1.2 Concept of Dead-Time ..... 7
2.1.2 死亡时间的概念 ..... 7
2.1.3 Full-Bridge Configuration ..... 8
2.1.3 全桥配置 .....8
2.2 Modulation Schemes ..... 9
2.2 调制方案 .....9
2.2.1 Pulse Width Modulation ..... 9
2.2.1 脉冲宽度调制 .....9
2.2.2 Pulse Density Modulation ..... 10
2.2.2 脉冲密度调制 .....10
2.2.3 Comparison between Pulse Density and Pulse Width Modulation ..... 14
2.2.3 脉冲密度与脉宽调制的比较 .....14
2.3 GaN Material Properties ..... 17
2.3 氮化镓材料特性 .....17
2.3.1 Device Structure and Operation ..... 18
2.3.1 设备结构和运行 .....18
2.4 Source of Power Loss ..... 20
2.4 电力损耗来源 .....20
2.4.1 Conduction Loss ..... 20
2.4.1 传导损耗 .....20
2.4.2 Switching Loss ..... 20
2.4.2 开关损耗 .....20
2.4.3 Gate Drive Loss ..... 22
2.4.3 栅极驱动损耗 .....22
2.4.4 Reverse Conduction Loss ..... 22
2.4.4 反向传导损耗 .....22
2.4.5 Reverse Recovery Loss ..... 25
2.4.5 反向恢复损失 .....25
2.5 Source of Distortion in Class D Amplifier ..... 26
2.5 D 类放大器的失真源 .....26
2.6 Sources of Electromagnetic Interference (EMI) ..... 28
2.6 电磁干扰（EMI）源 .....28
2.6.1 Switch Mode Configuration ..... 28
2.6.1 交换机模式配置 .....28
2.6.2 Ringing due to Parasitic ..... 28
2.6.2 寄生虫引起的振铃 .....28
2.7 Summary ..... 31 2.7 总结 .....31
3 Digital Modulator and Output Stage Design ..... 32
3 数字调制器和输出级设计 .....32
3.1 Digital Modulator Design ..... 32
3.1 数字调制器设计 .....32
3.1.1 Modulator Architecture ..... 32
3.1.1 调制器架构 .....32
3.1.2 Up-Sampler & Interpolator ..... 32
3.1.2 上采样器和插值器 .....32
3.1.3 Delta sigma Modulator ..... 34
3.1.3 ΔΣ 调制器 .....34
3.1.4 Dead-Time Controller ..... 36
3.1.4 死区控制器 .....36
3.2 Print Circuit Board (PCBs) Design ..... 37
3.2 印刷电路板（PCB）设计 .....37
3.2.1 Current Loops ..... 37
3.2.1 电流环路 .....37
3.2.2 PCB Grounding ..... 39
3.2.2 PCB 接地 .....39
3.3 Discrete Component Selection ..... 40
3.3 分立元件选择 .....40
3.3.1 GaN and Silicon Device ..... 40
3.3.1 氮化镓和硅器件 .....40
3.3.2 Gate Driver ..... 42
3.3.2 栅极驱动器 .....42
3.3.3 Gate Resistance ..... 43
3.3.3 栅极电阻 .....43
3.3.4 Low Pass Filter ..... 46
3.3.4 低通滤波器 .....46
3.4 Summary ..... 47 3.4 总结 .....47
4 Experimental Results ..... 48
4 实验结果 .....48
4.1 Experimental Implementation ..... 48
4.1 实验实施 .....48
4.2 Test Setup ..... 48
4.2 测试设置 .....48
4.3 Experimental Results ..... 49
4.3 实验结果 .....49
4.3.1 Synchronous Buck Converter Experimental Results ..... 49
4.3.1 同步降压转换器实验结果 .....49
4.3.2 Class D Audio Amplifier Experimental Results ..... 51
4.3.2 D 类音频放大器实验结果 .....51
4.4 Performance Variation due to Thermal Issues ..... 73
4.4 热问题导致的性能差异 .....73
4.6 Summary ..... 80 4.6 总结 .....80
5 Conclusions ..... 81 5 结论 .....81
6 References ..... 83 6 参考文献 .....83
APPENDIX A - PCB Layout ..... 86
附录 A - PCB 布局 .....86
APPENDIX B - Data Sheets of Transistors ..... 90
附录 B - 晶体管数据表 .....90

Table 2.1. Material Properties of Silicon and Wide Band Gap Materials [18, 19]....................... 17
表 2.1.硅和宽带隙材料的材料特性 [18, 19].......................17

Table 3.1. Comparison between GaN and Silicon Transistors. .................................................... 40
表 3.1.氮化镓晶体管与硅晶体管的比较。....................................................40

Table 3.2. Comparison of the GaN and Silicon Gate Driver........................................................ 42
表 3.2.氮化镓和硅栅极驱动器的比较........................................................42

Table 4.1. Buck Configuration Measurements ............................................................................. 50
表 4.1.降压配置测量 .............................................................................50

Table 4.2. GaN and Silicon Output Stage without Air-Cooling................................................... 78
表 4.2.无空气冷却的氮化镓和硅输出级...................................................78

Table 4.3. GaN and Silicon Output Stage with Air-Cooling. ....................................................... 79
表 4.3.采用空气冷却的氮化镓和硅输出级。.......................................................79

Figure 1.1. Audio amplifier configurations: a) Linear Class AB and b) Switch Mode Class D amplifier. ..... 3
图 1.1.音频放大器配置：a) 线性 AB 类和 b) 开关模式 D 类放大器。.....3
Figure 2.1. Essential circuit blocks in a class D audio amplifier. ..... 5
图 2.1.D 类音频放大器的基本电路模块。.....5
Figure 2.2. Half-bridge configuration ..... 6
图 2.2.半桥配置 .....6
Figure 2.3. Waveforms of a buck converter. ..... 7
图 2.3.降压转换器的波形。.....7
Figure 2.4. and are the dead-times inserted between the gating signals ..... 8
图 2.4. 和 是插入门控信号之间的死区时间 .....8
Figure 2.5. Full-bridge configuration ..... 8
图 2.5.全桥配置 .....8
Figure 2.6. Basic architecture of a PWM modulator. ..... 9
图 2.6.PWM 调制器的基本结构。.....9
Figure 2.7. Example of a PWM modulator output waveforms ..... 9
图 2.7.PWM 调制器输出波形示例 .....9
Figure 2.8. Example architecture of a digital PWM modulator ..... 10
图 2.8.数字 PWM 调制器结构示例 .....10
Figure 2.9. Basic architecture of a PDM modulator. ..... 11
图 2.9.PDM 调制器的基本结构。.....11
Figure 2.10. PDM output waveforms with and without with hysteresis. ..... 11
图 2.10.带滞后和不带滞后的 PDM 输出波形。.....11
Figure 2.11. DSM noise transfer functions: Red is a order modulator and blue is a order
图 2.11.DSM 噪声传递函数：红色为 阶调制器，蓝色为 阶调制器
modulator. ..... 11 调制器。.....11
Figure 2.12. Basic architecture of a PDM modulator with hysteresis. ..... 12
图 2.12.带滞后的 PDM 调制器的基本结构。.....12
Figure 2.13. Example architecture of a digital PDM modulator. ..... 12
图 2.13.数字 PDM 调制器结构示例。.....12
Figure 2.14. PDM single-tone spectrum with different hysteresis coefficient. ..... 13
图 2.14.具有不同滞后系数的 PDM 单音频谱。.....13
Figure 2.15. PDM output pulse width histogram with different hysteresis coefficient ..... 13
图 2.15.不同滞后系数下 PDM 输出脉宽直方图 .....13
Figure 2.16. Histogram of pulse width of the PWM modulator with different input sine wave. ..... 14
图 2.16.不同输入正弦波时 PWM 调制器脉冲宽度的直方图。.....14
Figure 2.17. Histogram of pulse width of the PDM modulator with different input sine wave. ..... 15
图 2.17.PDM 调制器在不同输入正弦波条件下的脉冲宽度直方图。.....15
Figure 2.18. The supply current spectrum: Red is PDM and blue is PWM ..... 15
图 2.18.电源电流频谱：红色为 PDM，蓝色为 PWM .....15
Figure 2.19. PWM output single tone spectrums with an output stage. ..... 16
图 2.19.带输出级的 PWM 输出单音频谱。.....16
Figure 2.20. PDM output single tone spectrums with an output stage ..... 16
图 2.20.带有输出级的 PDM 输出单音频谱 .....16
Figure 2.21. versus breakdown voltage for silicon, SiC , and ..... 18
图 2.21.硅、SiC 和 的 与击穿电压的关系 .....18
Figure 2.22. A typical GaN HEMT structure [22]. ..... 19
图 2.22.典型的 GaN HEMT 结构 [22]。.....19
Figure 2.23. A typical silicon MOSFET structure ..... 19
图 2.23.典型的硅 MOSFET 结构 .....19
Figure 2.24. Switching loss during the turn-on of a power device ..... 21
图 2.24.功率器件接通期间的开关损耗 .....21
Figure 2.25. Switching loss during the turn-off a power device. ..... 21
图 2.25.功率器件关断时的开关损耗。.....21
Figure 2.26. Reverse conduction in a half-bridge configuration with GaN devices ..... 23
图 2.26.使用氮化镓器件的半桥配置中的反向传导 .....23
Figure 2.27. Waveforms for reverse conduction in a half-bridge configuration ..... 23
图 2.27.半桥配置中的反向传导波形 .....23
Figure 2.28. Reverse conduction in a full-bridge configuration with GaN device. ..... 24
图 2.28.采用氮化镓器件的全桥配置中的反向传导。.....24
Figure 2.29. Waveforms for reverse conduction in a full-bridge configuration. ..... 24
图 2.29.全桥配置中的反向传导波形。.....24
Figure 2.30 Diode recovery waveform during turn off transistors [23]. ..... 25
图 2.30 关闭晶体管时二极管的恢复波形 [23]。.....25
Figure 2.31 Comparison between ideal and actual switching waveform ..... 26
图 2.31 理想开关波形与实际开关波形对比 .....26
Figure 2.32. The effect of change in on THD+N [25] ..... 27
图 2.32. 的变化对 THD+N 的影响 [25] .....27
Figure 2.33. The effects of dead-time on THD+N [25] ..... 27
图 2.33.死区时间对 THD+N 的影响 [25] .....27
Figure 2.34. One-sided spectrum of a square wave [28] ..... 28
图 2.34.方波的单边频谱 [28] .....28
Figure 2.35. Parasitic inductances in a half-bridge configuration. ..... 29
图 2.35.半桥配置中的寄生电感。.....29
Figure 2.36. Parasitic in the gate circuit. ..... 29
图 2.36.栅极电路中的寄生.....29
Figure 2.37. Square wave with ringing ..... 30
图 2.37.带振铃的方波 .....30
Figure 2.38. Spectra of a square wave with ringing at [28]. ..... 30
图 2.38.在 处出现振铃的方波频谱 [28]。.....30
Figure 3.1. Block diagram showing the main digital PDM modulator building blocks ..... 32
图 3.1.显示主要数字 PDM 调制器构件的框图 .....32
Figure 3.2. CIC interpolation filter [31] ..... 33
图 3.2.CIC 插值滤波器 [31] .....33
Figure 3.3. CIC filter magnitude output. ..... 33
图 3.3.CIC 滤波器幅度输出。.....33
Figure 3.4. CIC filter output (a) Input (b) First CIC (C) Second CIC. ..... 34
图 3.4.CIC 滤波器输出 (a) 输入 (b) 第一个 CIC (C) 第二个 CIC。.....34
Figure 3.5. order DSM architecture with hysteresis ..... 34
图 3.5.带滞后的 阶 DSM 架构 .....34
Figure 3.6. FFT of the input and output of a DSM. ..... 35
图 3.6.DSM 输入和输出的 FFT。.....35
Figure 3.7. Dead-time controller for each transistor. ..... 36
图 3.7.每个晶体管的死区时间控制器.....36
Figure 3.8. Current loops of the GaN output stage. ..... 38
图 3.8.氮化镓输出级的电流回路。.....38
Figure 3.9. Current loops of the silicon output stage ..... 38
图 3.9.硅输出级的电流回路 .....38
Figure 3.10. Star connection on the PCB ..... 39
图 3.10.PCB 上的星形连接 .....39
Figure 3.11. Comparison of FOM for TrenchFET and NexFET technologies [33] ..... 41
图 3.11.TrenchFET 和 NexFET 技术的 FOM 比较 [33] .....41
Figure 3.12. Qg vs Ron graph [34] ..... 41
图 3.12.Qg vs Ron 图 [34] .....41
Figure 3.13. Example boot strap circuit. ..... 43
图 3.13.引导带电路示例。.....43
Figure 3.14. The GaN half-bridge output stage schematic. ..... 44
图 3.14.氮化镓半桥输出级原理图。.....44
Figure 3.15. The silicon half-bridge output stage schematic ..... 44
图 3.15.硅半桥输出级原理图 .....44
Figure 3.16. Gate nodes of the silicon output stage with different gate resistance ..... 45
图 3.16.具有不同栅极电阻的硅输出级栅极节点 .....45
Figure 3.17. Passive RLC low pass filter. ..... 46
图 3.17.无源 RLC 低通滤波器。.....46
Figure 3.18. Low pass filter transfer function ..... 46
图 3.18.低通滤波器传递函数 .....46
Figure 4.1. Photographs of the output stages ..... 48
图 4.1.输出级照片 .....48
Figure 4.2. The setup for audio performance characterization. ..... 49
图 4.2.音频性能鉴定装置。.....49
Figure 4.3. Gate nodes of both output stages. ..... 50
图 4.3.两个输出级的栅极节点。.....50

Figure 4.4. Switching nodes of both output stages. ...................................................................... 50
图 4.4.两个输出级的开关节点。......................................................................50

Figure 4.5. First operating condition of the full-bridge configuration when output voltage is positive to ..................................................................................... 51
图 4.5.当输出电压为 ..................................................................................... 时，全桥配置的第一工作状态51

Figure 4.6. Second operating condition of the full-bridge configuration when output voltage is negative to . .................................................................................... 51
图 4.6.当输出电压为负至 时，全桥配置的第二种工作状态。....................................................................................51

Figure 4.7. Switching node of the GaN output stage with . .......................................... 53
图 4.7.带有 的氮化镓输出级的开关节点。..........................................53

Figure 4.8. Switching node of the GaN output stage with . .......................................... 53
图 4.8.带有 的氮化镓输出级的开关节点。..........................................53

Figure 4.9. Switching node of the silicon output stage with ........................................ 53
图 4.9.带有 ........................................ 的硅输出级开关节点53

Figure 4.10. Switching node of the silicon output stage with ...................................... 54
图 4.10.带有 ...................................... 的硅输出级开关节点54

Figure 4.11. Gate nodes of both output stages at . .................................................... 54
图 4.11. 时两个输出级的栅极节点。....................................................54

Figure 4.12. Single-tone spectrum of the GaN output stage with and a -6 dBFS 100 Hz sine wave 56
图 4.12.采用 和 -6 dBFS 100 Hz 正弦波的氮化镓输出级的单音频谱 56

Figure 4.13. Single-tone spectrum of the GaN output stage with and a -6 dBFS 1 kHz sine wave 56
图 4.13.采用 和 -6 dBFS 1 kHz 正弦波的氮化镓输出级的单音频谱 56

Figure 4.14. Single-tone spectrum of the GaN output stage with and a -6 dBFS 10 kHz sine wave 56
图 4.14.采用 和 -6 dBFS 10 kHz 正弦波的氮化镓输出级的单音频谱 56

Figure 4.15. Single-tone spectrum of the silicon output stage with and a -6 dBFS 100 Hz sine wave. 57
图 4.15.硅输出级 和 -6 dBFS 100 Hz 正弦波的单音频谱。57

Figure 4.16. Single-tone spectrum of the silicon output stage with and a -6 dBFS 1 kHz sine wave. 57
图 4.16.带有 和 -6 dBFS 1 kHz 正弦波的硅输出级单音频谱。57

Figure 4.17. Single-tone spectrum of the silicon output stage with and a -6 dBFS 10 kHz sine wave. 57
图 4.17.带有 和 -6 dBFS 10 kHz 正弦波的硅输出级单音频谱。57

Figure 4.18. Efficiency versus output power of the GaN output stage at different with and a 1 kHz sine wave at different power levels
图 4.18.在不同 、 和 1 kHz 正弦波的不同功率水平下，氮化镓输出级的效率与输出功率的关系

59

Figure.4.19. Efficiency versus output power of the silicon output stage at different with and a 1 kHz sine wave at different power levels.
图 4.19.硅输出级在不同 和 条件下的效率与输出功率的关系，以及不同功率水平下的 1 kHz 正弦波。

Figure 4.20. Efficiency versus output power of both GaN and silicon output stages with different with and a 1 kHz sine wave at different power levels. 60
图 4.20.不同 和 的氮化镓和硅输出级的效率与输出功率的关系，以及不同功率水平下的 1 kHz 正弦波。60

Figure 4.21. Efficiency versus output power of the GaN output stage at different dead-times with , a 1 kHz sine wave at different power levels and with an
图 4.21.氮化镓输出级在不同死区时间 、不同功率水平的 1 kHz 正弦波和 条件下的效率与输出功率的关系

Figure 4.22. Efficiency versus output power of the silicon output stage at different dead-times with , a 1 kHz sine wave at different power levels and with an 61
图 4.22.硅输出级在不同死区时间 、不同功率水平的 1 kHz 正弦波和 61 条件下的效率与输出功率的关系

Figure 4.23. THD +N versus output power of the GaN output stage at different with with a 1 kHz sine wave at different power levels 63
图 4.23.氮化镓输出级在不同 和 条件下的 THD +N 与输出功率的关系，1 kHz 正弦波在不同功率水平 63

Figure 4.24. THD +N versus output power of the silicon output stage at different with with a 1 kHz sine wave at different power levels 63
图 4.24.硅输出级在不同 和 条件下的 THD +N 与输出功率的关系，1 kHz 正弦波在不同功率水平 63

Figure 4.25. THD +N versus output power of both GaN and silicon output stage at different with with a 1 kHz sine wave at different power levels. 64
图 4.25.在不同 和 条件下，氮化镓和硅输出级的 THD +N 与输出功率的关系，1 kHz 正弦波在不同功率水平。64

Figure 4.26. THD+N versus output power of the GaN output stage at different dead times with , a 1 kHz sine wave at different power levels and with an 64
图 4.26.在 不同死区时间、不同功率水平的 1 kHz 正弦波和 64 条件下，氮化镓输出级的 THD+N 与输出功率的关系。

Figure 4.27. THD +N versus output power of the silicon output stage at different dead times with , a 1 kHz sine wave at different power levels and with an
图 4.27.硅输出级在 不同死区时间、不同功率水平的 1 kHz 正弦波和 时的 THD +N 与输出功率的关系。

65

Figure 4.28. Frequency response of both GaN and silicon output stage with and a -6 dBFS sine wave at different frequencies and with different . 66
图 4.28.采用 和 -6 dBFS 正弦波的氮化镓和硅输出级在不同频率和不同 下的频率响应。66

Figure 4.29. Maximum power of both GaN and silicon with and at different with a constant THD+N = ........................................................................... 67
图 4.29.在 THD+N = ........................................................................... 不变的情况下，在不同 条件下，GaN 和硅在 和 时的最大功率67

Figure 4.30. THD+N versus frequency of both GaN and silicon at an constant output power of 5 W with and at different ............................................... 68
图 4.30.在 5 W 恒定输出功率下，GaN 和硅的 THD+N 与频率的关系， 和 在不同的 ...............................................。68

Figure 4.31. THD +N versus frequency of both GaN and silicon at an constant output power of 10 W with and at different 69
图 4.31.当输出功率恒定为 10 W， 和 位于不同的 69 时，氮化镓和硅的 THD +N 随频率变化的情况

Figure 4.32. Dual tone test with of the GaN output stage with and with -1 dBFS
图 4.32.氮化镓输出级的 和 双音测试（-1 dBFS

Figure 4.33. Dual tone test with of the silicon output stage with and with -1 dBFS .
图 4.33.硅输出级的 和 双音测试（-1 dBFS）。

Figure 4.34. CEMI of the GaN output stage with and and a -6 dBFS 1 kHz) sine wave
图 4.34.采用 和 以及 -6 dBFS 1 kHz 正弦波的氮化镓输出级的 CEMI

Figure 4.35. CEMI of the silicon output stage with and and a -6 dBFS 1) kHz sine wave 72
图 4.35.带有 和 的硅输出级的 CEMI 以及 -6 dBFS 1) kHz 正弦波 72

Figure 4.36 CEMI of the output stage with no input and VSupply V........................................ 72
图 4.36 输出级的 CEMI（无输入，VSupply V........................................72
Figure 4.37. Temperature characteristic for the GaN power devices [38]. ..... 74
图 4.37.氮化镓功率器件的温度特性 [38]。.....74
Figure 4.38. Changes in dead-time after a threshold voltage increase. Actual dead-times are
图 4.38.阈值电压上升后的死区时间变化。实际死区时间为 。
and ..... 74 和 .....74
Figure 4.39. Temperature characteristic for silicon power devices [39]. ..... 75
图 4.39.硅功率器件的温度特性 [39]。.....75
Figure 4.40. Changes in dead-time after a threshold voltage decrease. Actual dead-times are
图 4.40.阈值电压降低后的死区时间变化。实际死区时间为 。
and . ..... 75 和 。.....75
Figure 4.41. GaN output stage taken with a digital camera. ..... 76
图 4.41.用数码相机拍摄的 GaN 输出级。.....76
Figure 4.42. GaN output stage taken with an IR Camera with a 1 kHz sine wave. ..... 76
图 4.42.用红外热像仪拍摄的氮化镓输出级 1 kHz 正弦波。.....76
Figure 4.43. Silicon output stage taken with digital camera. ..... 76
图 4.43.用数码相机拍摄的硅输出级。.....76
Figure 4.44. Silicon output stage taken with an IR Camera with a 1 kHz sine wave ..... 77
图 4.44.用红外摄像机拍摄的硅输出级，1 kHz 正弦波 .....77
Figure 4.45. GaN output stage taken with an IR Camera, with music playing ..... 77
图 4.45.使用红外摄像机拍摄的氮化镓输出级，播放音乐 .....77
Figure 4.46. Silicon output stage taken with an IR Camera, with music playing. ..... 77
图 4.46.使用红外摄像机拍摄的硅输出级，同时播放音乐。.....77
Figure A. 1 Top layer of the GaN output stage. ..... 86
图 A. 1 氮化镓输出级的顶层。.....86
Figure A.2. Bottom layer of the GaN output stage ..... 87
图 A.2.氮化镓输出级底层 .....87
Figure A.3. Top layer of the silicon output stage ..... 88
图 A.3.硅输出级顶层 .....88
Figure A.4. Bottom layer of the silicon output stage ..... 89
图 A.4.硅输出级底层 .....89

Gallium Nitride (GaN) is a promising wide-band gap material suitable for switching power converters. It has higher electron mobility and electron saturation velocity when compared to silicon.
氮化镓（GaN）是一种很有前途的宽带隙材料，适用于开关功率转换器。与硅相比，氮化镓具有更高的电子迁移率和电子饱和速度。
These properties have led to GaN power devices having a lower figure of merit (FOM), which is defined as gate charge on-resistance [1]. The FOM is important in applications such as switching power converters, where the devices' conduction loss and switching loss affect the performance of the converters. These advantages have led to an increase in research activities to further improve GaN power devices [2].
这些特性使得氮化镓功率器件具有较低的优点系数（FOM），其定义为栅极电荷 导通电阻 [1]。FOM 在开关功率转换器等应用中非常重要，因为器件的传导损耗和开关损耗会影响转换器的性能。这些优势促使进一步改进氮化镓功率器件的研究活动不断增加[2]。

With the introduction of commercial GaN power devices, the market for these devices has been increasing dramatically. It is forecasted that the GaN power devices market will reach billion by 2022 [3]. The entire semiconductor market for power converters ranging from 20 to 1200 V is billion annually and the power integrated circuit (PICs) market for devices account for an additional 10 billion in annual sales [4]. This market is growing with increasing demand from several emerging technologies that require these devices.
随着商用氮化镓功率器件的推出，这些器件的市场也在急剧增长。据预测，到 2022 年，氮化镓功率器件的市场规模将达到 十亿[3]。20 至 1200 V 功率转换器的整个半导体市场每年的销售额为 亿美元，功率集成电路 (PIC) 市场的年销售额也达到 100 亿美元 [4]。随着一些新兴技术对这些器件的需求不断增长，这一市场也在不断扩大。
These include light emitting diode (LED) lighting, inverters for photovoltaic (PV) applications, and motor drives in electrical vehicles (EV). For power converters such as PICs the power density, which is defined as amount of power per area, is important for consumers.
这些应用包括发光二极管（LED）照明、光伏（PV）应用中的逆变器以及电动汽车（EV）中的电机驱动器。对于 PIC 等功率转换器而言，功率密度（即单位面积的功率）对消费者来说非常重要。
A GaN power device with a low FOM allows the power converters to operate at a higher efficiency and switching frequencies ( ) than silicon power device. This results in a smaller overall circuit as the size of the output low pass filter decreases. With higher efficiency, minimal thermal management are required to cool down the devices.
与硅功率器件相比，具有低 FOM 的氮化镓功率器件可使功率转换器以更高的效率和开关频率（ ）工作。由于输出低通滤波器的尺寸减小，因此整体电路更小。有了更高的效率，冷却器件所需的热管理也降至最低。

The material properties of GaN has led researchers to build power converters from 10's of W to several kW , with switching frequency ranging from a few 100 's of kHz to power converters have been used in various applications such as power supplies, envelope tracking and PV converters. A 300 W boost converter operating at 1 MHz was shown to have an efficiency of in 2008 [5] and in 2013 a 1.6 kW boost converter operating at 1 MHz was shown to have efficiency [6]. The material properties of GaN allows the power converters to operate at higher switching speeds, therefore researcher have pushed the of the converters. They have demonstrated a 10 W buck converter with varying from 10 to 40 MHz . The peak efficiency at 10 MHz is and above at 40 MHz , with the duty cycles > [7]. Another researcher demonstrated a 65 W boost converter with a peak efficiency of and of 50 MHz in 2011
氮化镓的材料特性促使研究人员制造出功率从 10 几瓦到几千瓦不等的功率转换器，开关频率从几百千赫到 不等，功率转换器已被用于电源、包络跟踪和光伏转换器等各种应用中。2008 年，一个工作频率为 1 MHz 的 300 W 升压转换器的效率达到 [5]；2013 年，一个工作频率为 1 MHz 的 1.6 kW 升压转换器的效率达到 [6]。氮化镓的材料特性允许功率转换器以更高的开关速度运行，因此研究人员推动了转换器的 。他们展示了一个 10 W 的降压转换器， 在 10 到 40 MHz 之间变化。10 MHz 时的峰值效率为 ，40 MHz 时超过 ，占空比 > [7]。另一位研究人员在 2011 年展示了一款 65 W 的升压转换器，其峰值效率为 ， 为 50 MHz。

[8]. The GaN devices are also shown to be more efficient when compared to silicon devices, a study has shown an increase in efficiency from 94.7 % to 95.9 % in a PV converter [9]. Another study has shown a buck converter with a increase in efficiency at an of 10 MHz [10]. The research carried out on various configurations shows general improvement in efficiency at all . However, the application of GaN devices in Class D audio power amplifiers have not been widely studied.
[8].一项研究显示，在光伏转换器中，氮化镓器件的效率从 94.7% 提高到 95.9%[9]。另一项研究显示，在 10 MHz 的 频率下，降压转换器的效率提高了 [10]。对各种配置进行的研究表明，在所有 条件下，效率都有普遍提高。然而，GaN 器件在 D 类音频功率放大器中的应用尚未得到广泛研究。

Companies which manufacture GaN power devices such as EPC and Infineon has built GaN Class D audio amplifiers achieving at 5 W and a max efficiency of at 150 W with an load [11]. Although GaN based audio amplifiers has been studied, no comparison on the overall performance between a GaN and silicon based Class D audio power amplifiers were conducted.
宜普公司和英飞凌公司等生产氮化镓功率器件的公司已制造出氮化镓 D 类音频放大器，在 5 W 时达到 ，在 150 W 时达到 ，负载为 [11]。虽然对基于氮化镓的音频放大器进行了研究，但并未对氮化镓和硅基 D 类音频功率放大器的整体性能进行比较。
In this thesis, a comparison between an open-loop Class D audio power amplifier with GaN and silicon based output stage will be investigated.
本论文将对采用氮化镓输出级和硅输出级的开环 D 类音频功率放大器进行比较研究。

The latest generation of audio amplifiers employs the switched mode Class D topology to achieve significant power efficiency improvements over conventional linear audio amplifiers, such as Class and AB . Linear amplifiers have a DC bias current which makes up for a large portion of their power consumption. As a result, typical power efficiency is limited to around . In contrast, the Class D amplifier utilizes a switched mode configuration to achieve a power efficiency, which can theoretically reach . However, Class D amplifiers require an additional modulation stage in order to encode the input audio signal. These two topologies are illustrated in Figure 1.1. Class D amplifiers has higher efficiency; therefore, the heat dissipation is reduced.
最新一代音频放大器采用了开关模式 D 类拓扑结构，与传统的线性音频放大器（如 类和 AB 类）相比，功率效率有了显著提高。线性放大器的大部分功耗来自直流偏置电流。因此，典型的功率效率仅限于 左右。相比之下，D 类放大器利用开关模式配置来实现功率效率，理论上可以达到 。不过，D 类放大器需要额外的调制级才能对输入音频信号进行编码。这两种拓扑结构如图 1.1 所示。D 类放大器具有更高的效率，因此可以减少散热。
As a result, the Class D amplifier has a lower cost and minimal thermal managements are usually sufficient.
因此，D 类放大器的成本较低，通常只需最低限度的热管理即可。
On the other hand, compared to linear amplifiers, the Class D amplifiers are sensitive to modulator non-linearity, power device non-idealities and power supply noise, which makes achieving low distortion difficult.
另一方面，与线性放大器相比，D 类放大器对调制器非线性、功率器件非理想性和电源噪声非常敏感，因此很难实现低失真。
With the recent development in GaN technology, this thesis will focus on minimizing the non-idealities of the power devices with the use of GaN power devices.
随着氮化镓技术的最新发展，本论文将重点讨论如何利用氮化镓功率器件最大限度地减少功率器件的非理想性。

(a)

(b)

Figure 1.1. Audio amplifier configurations: a) Linear Class AB and b) Switch Mode Class D amplifier.
图 1.1.音频放大器配置：a) 线性 AB 类和 b) 开关模式 D 类放大器。

Chapter 2 covers the background of the Class D audio power amplifier and is organized into four parts.
第 2 章介绍了 D 类音频功率放大器的背景，分为四个部分。
The first part deals with the operation of the Class D audio amplifier, followed by the theoretical concepts of the Pulse Width Modulation (PWM) and Pulse Density Modulation (PDM) architectures and lastly the advantages and disadvantages of each modulation scheme.
第一部分介绍 D 类音频放大器的工作原理，然后是脉冲宽度调制 (PWM) 和脉冲密度调制 (PDM) 结构的理论概念，最后是每种调制方案的优缺点。
This is followed by a description of the GaN material properties. Finally, the sources of power loss, distortion and electromagnetic interference (EMI) from the Class D amplifier are discussed. Chapter 3 discusses the design of the modulator and output stage.
随后介绍了氮化镓材料的特性。最后，讨论了 D 类放大器的功率损耗、失真和电磁干扰（EMI）来源。第 3 章讨论了调制器和输出级的设计。
Beginning with the design of the digital modulation stage, followed by the design considerations for the Printed Circuit Boards (PCB) and the details of the selections of discrete components.
首先是数字调制阶段的设计，然后是印刷电路板（PCB）的设计考虑因素和选择分立元件的细节。
Chapter 4 presents the experimental results and discussion of the Class D audio amplifier. The thesis concludes with Chapter 5, where the research is summarized and the opportunities for future work are discussed.
第 4 章介绍了 D 类音频放大器的实验结果和讨论。论文最后的第 5 章总结了研究工作，并讨论了未来工作的机会。

This chapter discusses the basic components of a Class D amplifier, beginning with the basic operations. This is then followed by the theoretical concepts and the modulation schemes.
本章从基本操作开始，讨论 D 类放大器的基本组件。然后是理论概念和调制方案。
Pulse Width Modulation (PWM) and Pulse Density Modulation (PDM) are the two modulation schemes to be discussed. The GaN materials properties is discussed next.
脉宽调制（PWM）和脉冲密度调制（PDM）是将要讨论的两种调制方案。接下来将讨论氮化镓材料的特性。
Finally, the chapter ends with an overview of the power loss, distortion and electromagnetic interference associated with the Class D amplifier.
最后，本章概述了与 D 类放大器有关的功率损耗、失真和电磁干扰。

The Class D amplifier consists of a modulator, a switching output stage, and a low pass filter as illustrated in Figure 2.1. The input audio signal is encoded with a PWM or PDM modulator into a high frequency gating signal.
D 类放大器由一个调制器、一个开关输出级和一个低通滤波器组成，如图 2.1 所示。输入音频信号由 PWM 或 PDM 调制器编码成高频门控信号。
This signal is then used to drive the output stage devices. The output stage can be in a half-bridge or full-bridge configuration; however, a full-bridge configuration is more common. The output stage amplifies the input gating signal determined by the level of supply voltage.
该信号随后用于驱动输出级设备。输出级可以采用半桥或全桥配置，但全桥配置更为常见。输出级放大由电源电压电平决定的输入门控信号。
It is then demodulated by a low pass filter, in order to remove the high frequency components, to recovery of the original signal. Finally, the demodulated signal then is used to drive the speaker.
然后通过低通滤波器进行解调，以去除高频成分，恢复原始信号。最后，解调后的信号用于驱动扬声器。

Figure 2.1. Essential circuit blocks in a class D audio amplifier.
图 2.1.D 类音频放大器的基本电路模块。

A full-bridge configuration consists of two half-bridges. The half-bridge configuration is illustrated in Figure 2.2. In order to understand the full-bridge configuration, understanding the operations of a half-bridge is essential.
全桥配置由两个半桥组成。半桥配置如图 2.2 所示。要了解全桥配置，必须先了解半桥的工作原理。
However, the half-bridge is not commonly used for Class D amplifiers. The full-bridge configuration can resolve issues that exist in the half-bridge configuration, such as an inherent DC component [12].
不过，半桥并不常用于 D 类放大器。全桥配置可以解决半桥配置中存在的问题，如固有的直流分量 [12]。

Figure 2.2. Half-bridge configuration.
图 2.2.半桥配置

The half-bridge configuration can operate as a synchronous buck converter or a Class D amplifier. However, in order to operate the Class D amplifier with a half-bridge configuration, a capacitor in series with the output speaker is require to remove the inherent DC component.
半桥配置可作为同步降压转换器或 D 类放大器运行。不过，要使用半桥配置运行 D 类放大器，需要在输出扬声器上串联一个电容器，以消除固有的直流分量。
In a buck converter, a constant regulated output voltage is desired, however in a Class D audio amplifier, a constantly changing output voltage reflective to the input signal is desired.
在降压转换器中，需要恒定的稳压输出电压，而在 D 类音频放大器中，则需要不断变化的输出电压来反映输入信号。

In a synchronous buck converter, the switches are gated in a complementary fashion, this ensures that M1 and M2 are never on at the same time; otherwise it will short circuit from power to ground.
在同步降压转换器中，开关是以互补方式选通的，这就确保了 M1 和 M2 永远不会同时导通，否则就会造成电源到地的短路。
To ensure M1 and M2 are never on at the same time, additional dead-time is added between the two gate signals. When is on and is off, supplies the output load, and charges the inductor and capacitor. When M2 is on, M1 is off, the energy stored in from the inductor, and the capacitor is used to supply the load. The corresponding waveforms illustrated in Figure 2.3.
为确保 M1 和 M2 绝不同时导通，在两个栅极信号之间增加了额外的死区时间。当 开启， 关闭时， 为输出负载供电，并为电感器和电容器充电。当 M2 接通、M1 关断时，电感器和电容器储存的能量将用于为负载供电。相应的波形如图 2.3 所示。

Figure 2.3. Waveforms of a buck converter.
图 2.3.降压转换器的波形。

Given a fixed frequency at the period defines by , with duty cycle as the percentage of time that is turned on and as the percentage that is turned on. The average output voltage will be defined as [13]:
给定一个固定频率，其周期由 定义，占空比 为 接通的时间百分比， 为 接通的时间百分比。平均输出电压定义为 [13]：

To ensure that M1 and M2 are never on at the same time, dead-time is added to the gating signal as a practical and safety measure. Figure 2.4, illustrates the complementary gating signals with the presence of dead-time.
为了确保 M1 和 M2 永远不会同时开启，作为一项实用和安全的措施，在门控信号中加入了死区时间。图 2.4 展示了存在死区时间的互补选通信号。
In order to prevent the situation where both M1 and M2 being on simultaneously, due to finite switching speed of the transistors, a dead-time is inserted between the gating signals such that one transistors will be allowed to turn off before the other one is turned on.
由于晶体管的开关速度有限，为了防止出现 M1 和 M2 同时导通的情况，在门控信号之间插入了一个死区时间，使一个晶体管可以在另一个晶体管导通之前关闭。
Dead-time is implemented with the same method in a full-bridge configuration.
死区时间在全桥配置中以同样的方法实现。

Figure 2.4. and are the dead-times inserted between the gating signals.
图 2.4. 和 是插入门控信号之间的死区时间。

The full-bridge configuration (refer to Figure 2.5) operates in a similar fashion. M1 and M2 are gated in a complementary fashion same as that in a half-bridge configuration. For a simple two level modulation scheme, the gating signals for and are the same, and those for and M3 are the same. The full-bridge configuration allows the load to have a differential output of , doubling that of the half-bridge configuration. A full-bridge configuration also removes the inherent DC component as well as with an inherent power supply rejection, which are not present in a half-bridge configuration.
全桥配置（参见图 2.5）的工作方式类似。M1 和 M2 的门控方式与半桥配置中的互补方式相同。对于简单的两电平调制方案， 和 的门控信号相同， 和 M3 的门控信号也相同。全桥配置允许负载具有 的差分输出，是半桥配置的两倍。全桥配置还消除了固有的直流分量，并具有固有的电源抑制功能，而半桥配置则不具备这些功能。
The full-bridge configuration can also function with a 3 level modulation scheme [12], whereas the half-bridge configuration is limited to 2 .
全桥配置还可采用 3 级调制方案 [12]，而半桥配置则仅限于 2 级。

Figure 2.5. Full-bridge configuration.
图 2.5.全桥配置。

The modulation schemes are techniques that encode an input waveform into an output gating signal. The two level modulation scheme is used in this thesis.
调制方案是将输入波形编码成输出门控信号的技术。本论文采用的是两级调制方案。
This section discusses and compares two modulation schemes used in Class D amplifiers, the Pulse Width Modulation (PWM) and Pulse Density Modulation (PDM).
本节讨论并比较 D 类放大器中使用的两种调制方案，即脉冲宽度调制 (PWM) 和脉冲密度调制 (PDM)。

The architecture of a PWM is illustrated in Figure 2.6. The PWM modulation produces a waveform with a duty cycle that reflects the average voltage level of the input signal by comparing the input with a ramp as shown in Figure 2.7. The output switches once per ramp cycle, typically at 384 kHz , can create significant electromagnetic inference (EMI) harmonics at the ramp frequency.
PWM 的结构如图 2.6 所示。如图 2.7 所示，PWM 调制产生的波形占空比反映了输入信号的平均电压水平。输出在每个斜坡周期切换一次，频率通常为 384 kHz，会在斜坡频率上产生显著的电磁干扰 (EMI) 谐波。
As the modulation index increases the pulses can become narrow. At this point the output stage cannot replicate the pulses due to the transistors non-idealities such as finite switching speeds.
随着调制指数的增加，脉冲会变得越来越窄。此时，由于晶体管的非理想特性（如有限的开关速度），输出级无法复制脉冲。

Figure 2.6. Basic architecture of a PWM modulator.
图 2.6.PWM 调制器的基本结构。

Figure 2.7. Example of a PWM modulator output waveforms.
图 2.7.PWM 调制器输出波形示例。

The implementation of the PWM modulator in digital domain requires several digital signal-processing components, because direct PWM modulation of an audio signal is impractical.
在数字域实现 PWM 调制器需要多个数字信号处理组件，因为直接对音频信号进行 PWM 调制是不切实际的。
Audio samples have a long word-length, therefore the clock speed required to modulate such a signals difficult to realize.
音频采样的字长较长，因此难以实现调制此类信号所需的时钟速度。
The modulator designs based on cascading a Delta Sigma Modulator (DSM) and PWM modulator have been developed [14-16], and an example of the setup is illustrated in Figure 2.8. In this example, the up-sampler & interpolator stage increases the sampling frequency of the audio data. The up-sampled audio data is fed into a DSM with an 8bit output and an oversampling ratio of 16 . The DSM quantizes the audio data. Finally, the sample is converted to a gating pulses using PWM modulation [17].
基于级联ΔΣ调制器（DSM）和 PWM 调制器的调制器设计已经开发出来 [14-16]，图 2.8 举例说明了这种设置。在此示例中，上采样器和内插器阶段提高了音频数据的 采样频率。上采样音频数据被送入一个 8 位输出、过采样率为 16 的 DSM。DSM 对音频数据进行量化。最后，使用 PWM 调制将采样转换为门控脉冲[17]。
However, this technique still requires the use of a 200 MHz clock to convert the gating pulses.
不过，这种技术仍然需要使用 200 MHz 的时钟来转换门控脉冲。

Figure 2.8. Example architecture of a digital PWM modulator.
图 2.8.数字 PWM 调制器结构示例。

The architecture of a PDM is illustrated in Figure 2.9. The PDM modulation scheme produces a waveform of pulses whose average reflects the input signal by using a DSM with an 1bit output shown with Figure 2.9 [15].
PDM 的结构如图 2.9 所示。PDM 调制方案通过使用 DSM 产生脉冲波形，其平均值反映输入信号，输出为 1 位，如图 2.9 所示[15]。
A DSM uses noise shaping which can provide lower noise in the audio band shown in Figure 2.11. A higher order modulator can provide more noise attenuation. However, the higher the modulator order the lower the input range becomes as the modulator becomes unstable [18].
DSM 采用噪声整形技术，可降低图 2.11 所示音频频段的噪声。高阶调制器可以提供更多的噪声衰减。不过，调制器阶数越高，输入范围就越小，因为调制器会变得不稳定 [18]。
The PDM requires a higher clock frequency (12.5 MHz) to achieve comparable signal to noise (SNR) performance to PWM.
PDM 需要更高的时钟频率（12.5 MHz），才能达到与 PWM 相当的信噪比（SNR）性能。

An advantage of the PDM is that it has no fixed output frequency, which has no concentrated electromagnetic energy in the carrier band and harmonics. On other hand, an issue with PDM is that the shortest pulse width is 1 clock pulse wide.
PDM 的优势在于它没有固定的输出频率，因此不会在载波频段产生集中的电磁能量和谐波。另一方面，PDM 的问题是最短脉冲宽度为 1 个时钟脉冲宽。
Without additional signal processing, the output switching frequency ( ) will center around half of the clock frequency. The could be decreased by adding hysteresis to the PDM modulator, illustrated with Figure 2.10 .
如果不进行额外的信号处理，输出开关频率（ ）将以时钟频率的一半为中心。如图 2.10 所示，可以通过在 PDM 调制器中添加滞后来降低 。

Figure 2.9. Basic architecture of a PDM modulator.
图 2.9.PDM 调制器的基本结构。

Figure 2.10. PDM output waveforms with and without with hysteresis.
图 2.10.带滞后和不带滞后的 PDM 输出波形。

Figure 2.11. DSM noise transfer functions: Red is a order modulator and blue is a order modulator.
图 2.11.DSM 噪声传递函数：红色为 阶调制器，蓝色为 阶调制器。

Hysteresis is used in PDM in order to decrease the at the output. The modulation scheme is illustrated Figure 2.12 [19]. Hysteresis biases the output signal by adding or subtracting a coefficient after the integrator. The output signal remains higher or lower for extra clock cycles depending on the coefficient, which decreases . The output difference between the PDM with and without hysteresis are shown in Figure 2.10.
PDM 中使用磁滞来降低输出端的 。调制方案如图 2.12 所示 [19]。磁滞通过在积分器后添加或减去一个系数来偏置输出信号。根据系数的不同，输出信号在额外的时钟周期内保持较高或较低的水平，从而减小 。有磁滞和无磁滞 PDM 的输出差异如图 2.10 所示。

Figure 2.12. Basic architecture of a PDM modulator with hysteresis.
图 2.12.带滞后的 PDM 调制器的基本结构。

The PDM modulator implementation requires fewer digital signal-processing components compared to the PWM modulator, as the PDM modulator does not require an additional PWM modulator. The up-sampler & interpolator stage increases the sampling frequency ( ) of the audio data. The DSM with a 1-bit output, hysteresis and an oversampling ratio of 512, quantizes the word-length of the audio data and also converts the audio data to the gating signal. An example of the PDM modulator is illustrated in Figure 2.13.
与 PWM 调制器相比，PDM 调制器的实现所需的数字信号处理组件更少，因为 PDM 调制器不需要额外的 PWM 调制器。上采样器和插值器阶段提高了音频数据的采样频率（ ）。DSM 具有 1 位输出、滞后和 512 的过采样率，可量化音频数据的字长，并将音频数据转换为门控信号。图 2.13 举例说明了 PDM 调制器。

Figure 2.13. Example architecture of a digital PDM modulator.
图 2.13.数字 PDM 调制器结构示例。

The output of the PDM with different hysteresis coefficients is shown Figure 2.14 and Figure 2.15 are the histograms of the pulse widths with different hysteresis coefficients. When the hysteresis coefficient increases the decreases. With hysteresis, the performance of the PDM can be comparable to PWM as the output can be decreased.
图 2.14 和图 2.15 所示为 PDM 在不同滞后系数下的输出，图 2.15 是不同滞后系数下脉冲宽度的直方图。当磁滞系数增大时， 会减小。有了滞后，PDM 的性能可与 PWM 相媲美，因为输出 可以降低。

Figure 2.14. PDM single-tone spectrum with different hysteresis coefficient.
图 2.14.具有不同滞后系数的 PDM 单音频谱。

Figure 2.15. PDM output pulse width histogram with different hysteresis coefficient
图 2.15.不同滞后系数下 PDM 输出脉宽直方图

PDM and PWM are different modulation schemes with their own advantages and disadvantage. In this section, the differences between PDM and PWM are discussed.
PDM 和 PWM 是不同的调制方案，各有利弊。本节将讨论 PDM 和 PWM 的区别。

The pulse widths can affect the output distortion of the amplifier. The shorter the pulse widths, the more difficult it is for the output stage to reproduce.
脉冲宽度会影响放大器的输出失真。脉冲宽度越短，输出级就越难再现。
Therefore, more distortion can occur, as the transistors' non-idealities such as finite switching speed become more apparent.
因此，随着晶体管的非理想特性（如有限开关速度）变得更加明显，可能会出现更多失真。
As the input becomes larger, the pulse widths of the PWM modulator will become narrower or wider, as shown in Figure 2.16. On the other hand, for the PDM modulator as the input becomes larger, the pulse widths becomes wider, as shown in Figure 2.17. A similar is chosen for the simulation with PWM at 384 kHz and PDM at 360 kHz . The histograms also show that PWM has a fixed , because all the pulses revolve around the center point. However, PDM pulses are randomized, which indicates that the PDM has no fixed . The difference in the output pulse behaviors indicate that the electromagnetic interference (EMI) behavior between PWM and PDM will be different.
如图 2.16 所示，随着输入变大，PWM 调制器的脉冲宽度会变窄或变宽。另一方面，对于 PDM 调制器，当输入变大时，脉冲宽度会变宽，如图 2.17 所示。在 PWM 频率为 384 kHz 和 PDM 频率为 360 kHz 的模拟中，选择了类似的 。直方图还显示，PWM 的 是固定的，因为所有脉冲都围绕中心点旋转。然而，PDM 脉冲是随机的，这表明 PDM 没有固定的 。输出脉冲行为的不同表明 PWM 和 PDM 的电磁干扰（EMI）行为将有所不同。

Figure 2.16. Histogram of pulse width of the PWM modulator with different input sine wave.
图 2.16.不同输入正弦波时 PWM 调制器脉冲宽度的直方图。

Figure 2.17. Histogram of pulse width of the PDM modulator with different input sine wave.
图 2.17.PDM 调制器在不同输入正弦波条件下的脉冲宽度直方图。

EMI is an important consideration, because if large EMI disturbance is present, it may degrade the performance of the circuit or even stop it from functioning.
EMI 是一个重要的考虑因素，因为如果存在较大的 EMI 干扰，可能会降低电路的性能，甚至使其无法运行。
Figure 2.18 shows the supply current spectrum measured with a full-bridge output stage of a Class D amplifier for both PWM and PDM with 1 kHz input sine wave. The for PWM is at 384 kHz and PDM is at 360 kHz . PWM shows switching harmonics (EMI peaks) at 384 kHz , on the other hand PDM's switching harmonics has a spread spectrum affect, which decreases EMI.
图 2.18 显示了使用 D 类放大器全桥输出级测量的 PWM 和 PDM 电源电流频谱，输入正弦波频率均为 1 kHz。PWM 的 频率为 384 kHz，PDM 为 360 kHz。PWM 在 384 kHz 时会产生开关谐波（EMI 峰值），而 PDM 的开关谐波则会产生扩频效应，从而降低 EMI。

Figure 2.18. The supply current spectrum: Red is PDM and blue is PWM.
图 2.18.电源电流频谱：红色为 PDM，蓝色为 PWM。

Figure 2.19 and Figure 2.20 are the FFTs after an output stage. In order to capture the nonidealities of both PWM and PDM modulation schemes, similar are used. PDM with hysteresis can increase the pulse widths, hence decrease the , however not all pulse widths are increased leading to a few short pulses. The output stage cannot reproduce the short pulses property, which results in a higher noise floor.
图 2.19 和图 2.20 是输出级之后的 FFT 图。为了捕捉 PWM 和 PDM 调制方案的非理想性，使用了类似的 。带有滞后的 PDM 可以增加脉冲宽度，从而降低 ，但并非所有脉冲宽度都会增加，从而导致一些短脉冲。输出级无法再现短脉冲特性，从而导致更高的本底噪声。
In Figure 2.20 the slight rise in the PDM noise floor is the intermodulation between the fundamental frequency and the switching harmonics of PDM.
在图 2.20 中，PDM 本底噪声的轻微上升是 PDM 基频与开关谐波之间的互调。

Figure 2.19. PWM output single tone spectrums with an output stage.
图 2.19.带有输出级的 PWM 输出单音频谱。

Figure 2.20. PDM output single tone spectrums with an output stage.
图 2.20.带有输出级的 PDM 输出单音频谱。

Silicon transistors are reaching their performance limits due to its material properties. Researchers have turned to alternative semiconductor materials.
由于硅晶体管的材料特性，其性能已达到极限。研究人员已转向替代半导体材料。
In term of power devices, most of the current research is focused on wide bandgap materials, specifically GaN and silicon carbide .
在功率器件方面，目前的大部分研究都集中在宽带隙材料上，特别是氮化镓和碳化硅 。

Table 2.1. Material Properties of Silicon and Wide Band Gap Materials [20, 21].
表 2.1.硅和宽带隙材料的材料特性 [20, 21]。

In Table 2.1, it is evident that both GaN and SiC have material properties that make them better suited for power applications when compared to silicon.
从表 2.1 中可以明显看出，与硅相比，氮化镓和碳化硅都具有更适合功率应用的材料特性。
The wide band gap materials have a higher critical breakdown voltage making these transistors better suited for high voltages applications. GaN has higher electron mobility and saturation velocity, which improve the conductivity of the devices.
宽带隙材料具有更高的临界击穿电压，使这些晶体管更适合高压应用。氮化镓具有更高的电子迁移率和饱和速度，从而提高了器件的导电性。
In Figure 2.21, for the same sized transistors and the same breakdown voltage, the GaN transistors can provide a lower compared to silicon and SiC. However, GaN has a low thermal conductivity similar to silicon, meaning that it is less efficient in dissipating heat compared to SiC.
在图 2.21 中，对于相同尺寸的晶体管和相同的击穿电压，与硅和碳化硅相比，氮化镓晶体管可以提供更低的 。然而，氮化镓的热导率与硅类似较低，这意味着与碳化硅相比，氮化镓的散热效率较低。
The material properties of GaN indicates that a GaN based Class D amplifier will have lower power loss and distortion compared to a silicon based Class D amplifier.
氮化镓的材料特性表明，与硅基 D 类放大器相比，氮化镓 D 类放大器的功率损耗和失真更低。

Figure 2.21. versus breakdown voltage for silicon, SiC , and GaN [22].
图 2.21.硅、碳化硅和氮化镓的 与击穿电压的关系 [22]。

The GaN is a high electron mobility transistor (HEMT) has significant differences structure when compared to the structures of silicon power devices.
氮化镓是一种高电子迁移率晶体管（HEMT），其结构与硅功率器件的结构有很大不同。
The structure of a GaN HEMT is illustrated in Figure 2.22. The device is fabricated on a GaN-on-silicon substrate, with the aluminum nitride layer as a buffer between the GaN and silicon. An aluminum gallium nitride layer sits on top of the GaN layer, and at the interface a two dimensional electron gas (2DEG) is formed due to polarization. The electrons in the 2DEG is confined to movement in 2 dimensions, in the plane perpendicular to the surface of the device.
GaN HEMT 的结构如图 2.22 所示。该器件是在硅基氮化镓衬底上制造的，氮化铝层是氮化镓和硅之间的缓冲层。氮化镓层的顶部是氮化铝镓 层，由于极化作用，在界面上形成了二维电子气（2DEG）。二维电子气中的电子被限制在垂直于器件表面的平面内进行二维运动。
The properties of the 2DEG give rise to very high electron mobility, the reason behind the high electron mobility of GaN transistors. This is a depletion mode device, and is normally on.
二维电子元件的特性使其具有极高的电子迁移率，这也是氮化镓晶体管具有高电子迁移率的原因。这是一种耗尽模式器件，通常处于导通状态。

Figure 2.22. A typical GaN HEMT structure [22].
图 2.22.典型的 GaN HEMT 结构 [22]。

Figure 2.23. A typical silicon MOSFET structure.
图 2.23.典型的硅 MOSFET 结构。

The structure of a GaN HEMT is fundamentally different from silicon metal-oxide field effect transistor (MOSFET). The junction formed from the region of the body to region at the drain forms a body diode in a typical silicon MOSFET that is lacking in a GaN HEMT.
GaN HEMT 的结构与硅金属氧化物场效应晶体管 (MOSFET) 有本质区别。从本体的 区到漏极的 区形成的 结构成了典型硅 MOSFET 中的本体二极管，而这正是 GaN HEMT 所缺乏的。

In this section, sources of power loss from the devices are discussed in detail.
本节将详细讨论设备功率损耗的来源。

Conduction loss occurs when the device is switched on and voltage drops due to the . This can be calculated using the following equation:
当器件接通时，由于 导致电压下降，从而产生传导损耗。这可以用下式计算：

where is the percentage of time the transistor is on, is the current conducted by the transistor and is the on-resistance of the transistor.
其中， 是晶体管导通时间的百分比， 是晶体管传导的电流， 是晶体管的导通电阻。

Switching loss is associated with the turn-on and turn-off of the transistor, when both the voltage across the transistor and current conducting through the transistor is non-zero. They are calculated using the following equations:
当晶体管两端的电压和通过晶体管的电流都不为零时，开关损耗与晶体管的导通和关断有关。其计算公式如下

where, is the switching frequency, is the current conducted by the transistor and is the voltage conducted by the transistor. (refer to Figure 2.24) and (refer to Figure 2.25) are integrated over the turn-on and turn-off transition period, respectively.
其中， 是开关频率， 是晶体管传导的电流， 是晶体管传导的电压。 （参见图 2.24）和 （参见图 2.25）分别是开通和关断过渡期间的积分。

Figure 2.24. Switching loss during the turn-on of a power device.
图 2.24.功率器件接通时的开关损耗。

Figure 2.25. Switching loss during the turn-off a power device.
图 2.25.功率器件关断时的开关损耗。

The gate drive loss is the energy required to charge/discharge the gate capacitance of the transistor . The more the transistor turns-on and turns-off, the higher the , the higher the gate drive losses. Therefore, the gate drive loss is a function of , the supply voltage of the gate driver ( ) and .
栅极驱动损耗是对晶体管 的栅极电容进行充电/放电所需的能量。晶体管导通和关断的次数越多， 越高，栅极驱动损耗就越大。因此，栅极驱动损耗是 、栅极驱动器的电源电压（ ）和 的函数。

Reverse conduction loss is relevant to half-bridge and full-bridge configuration, but the effect on each one is different. Reverse conduction losses occur when all the switches are off and with current still flowing through the inductor.
反向传导损耗与半桥和全桥配置相关，但对每种配置的影响不同。反向传导损耗发生在所有开关都关断、电流仍流经电感器的情况下。
To provide a conduction path, the current flows through the body diode in the case of a silicon transistor. A GaN device does not have a body diode, therefore the current flows through the channel itself, as GaN device current can conducted in both directions.
为了提供传导路径，硅晶体管的电流流经体二极管。氮化镓器件没有体二极管，因此电流流经沟道本身，因为氮化镓器件的电流可以双向传导。

When reverse conduction occurs, the source and drain of the GaN device are reversed. Figure 2.26 is an illustration of reverse conduction in a GaN device in a half-bridge configuration. When both transistors are intended to be off, gate voltage is 0 V , the current flows through will require a conduction path. The current will flow through the channel of M2, requiring to turn-on. During reverse conduction, the source node functions as a drain node and vice versa. The voltage between and determines the gate to source voltage of . For to conduct, must be lower than negative threshold voltage , the of the transistor. The effects of reverse
发生反向传导时，氮化镓器件的源极和漏极会反向。图 2.26 是半桥配置中 GaN 器件反向传导的示意图。当两个晶体管都处于关断状态，栅极电压 为 0 V 时，流经 的电流将需要一个传导路径。电流将流经 M2 的沟道，要求 接通。在反向传导过程中，源极节点充当漏极节点，反之亦然。 和 之间的电压决定了 的栅极至源极电压。要使 导通， 必须低于负阈值电压 ，即晶体管的 。反向

conduction can be seen in the corresponding waveforms illustrated in Figure 2.27 where dips to .
从图 2.27 所示的相应波形中可以看出， 下降到 。

Figure 2.26. Reverse conduction in a half-bridge configuration with GaN devices.
图 2.26.采用氮化镓器件的半桥配置中的反向传导。

Figure 2.27. Waveforms for reverse conduction in a half-bridge configuration
图 2.27.半桥配置中的反向传导波形

In the full-bridge configuration since two transistors are required to provide the conduction path, the reverse conduction loss is doubled. As seen in Figure 2.28, and the waveforms in Figure 2.29, the reverse conduction effects are seen in the switching nodes of both legs.
在全桥配置中，由于需要两个晶体管提供传导路径，因此反向传导损耗增加了一倍。如图 2.28 和图 2.29 的波形所示，反向传导效应出现在两条腿的开关节点上。

Figure 2.28. Reverse conduction in a full-bridge configuration with GaN device.
图 2.28.采用氮化镓器件的全桥配置中的反向传导。

Figure 2.29. Waveforms for reverse conduction in a full-bridge configuration.
图 2.29.全桥配置中的反向传导波形。

GaN transistors have no reverse recovery losses due to a lack of an anti-parallel pn body diode that is inherent in the structure of silicon transistor. Therefore, the GaN devices do not have reverse recovery loss.
氮化镓晶体管没有反向恢复损耗，这是因为硅晶体管结构中没有固有的反并联 pn 体二极管。因此，氮化镓器件没有反向恢复损耗。
The reverse recovery loss occurs during the turn-on and turn-off transition of the transistors. During reverse recovery loss, the diode current rolls off at a constant ( ) to zero then reverses the direction. The negative current, also known as reverse recovery current ( ) reaches the negative peak ( ) and then goes back up to zero. The area of the negative current is known as reverse recovery charge ( ). The reverse recovery loss is illustrated in Figure 2.30. The is the energy loss during reverse recovery and the more transitions between turn on-and turnoff (higher ) and , the higher the reverse recovery loss. Therefore, reverse recovery loss is dependent and .
反向恢复损耗发生在晶体管的导通和关断转换期间。在反向恢复损耗期间，二极管电流以一定的速度（ ）滚动到零，然后反向。负电流也称为反向恢复电流（ ）达到负峰值（ ），然后回升到零。负电流的面积称为反向恢复电荷 ( )。反向恢复损耗如图 2.30 所示。 是反向恢复过程中的能量损耗，导通和关断之间的转换越多（ 越高）， 越高，反向恢复损耗就越大。因此，反向恢复损耗取决于 和 。