VLSI Design 4/M - Analogue
VLSI Design 4/M - 模拟

Edward Wasige
爱德华·瓦西格

EEE, University of Glasgow 74 Oakfield Ave., x8662 edward.wasige@glasgow.ac.uk
EEE，格拉斯哥大学 74 Oakfield Ave.，x8662 edward.wasige@glasgow.ac.uk

Introduction
介绍

CMOS (complimentary metal oxide semiconductor) technology has been the dominant technology for fabricating integrated circuits (ICs or chips). The process of creating an IC by combining thousands of transistors into a single chip is very−large−scale−integration (VGSI). CMOS is reliable, manufacturable, low power, low cost, and perhaps most importantly, scalable. For several decades the evolution of integrated circuits has followed Moore’s lam, according to which the number of transistors per square millimetre of silicon doubles every 18 months. At the same time transistors have become faster, making possible ever-increasing clock rates in digital circuits. This trend seems set to continue for at least another decade without slowing down. Thus, in the foreseeable future, the processing power of digital circuits will continue to increase at an accelerating pace. The gate lengths of early CMOS transistors were in the micrometer range (long-channel devices), the feature sizes of the current CMOS devices are in the nanometer range (short-channel devices).
CMOS（互补金属氧化物半导体）技术一直是制造集成电路（IC 或芯片）的主导技术。通过将数千个晶体管组合成单个芯片来创建 IC 的过程isvery−large−scale−integration（VGSI）CMOSisreliablemanufacturablelow功率、低成本，也许最重要的是，可 伸缩。几十年来，集成电路的发展一直遵循Moore的 lam，根据该理论，每平方毫米硅的晶体管数量每18个月翻一番。同时，晶体管变得更快，使数字电路中不断提高的时钟速率成为可能。这一趋势似乎将持续至少十年而不会放缓。因此，在可预见的未来，数字电路的处理能力将继续加速提高。早期CMOS晶体管的栅极长度在微米范围内（长通道器件），当前CMOS器件的特征尺寸在纳米范围（短通道器件）。

For analog circuits the evolution of technology is not as beneficial. Thus, there is a trend to move signal prcessing functions from the analog domain to the digital one, which, besides allowing for higher levels of accuracy, provides savings in power consumption and silicon area, increases robustness, speeds up the design process, brings flexibility and programmability, and increases the pos- sibilities for design re-use. In many applications the input and output signals of the system are inherently analog, preventing all-digital realisations; at the very least a conversion between analog and digital is needed at the interfaces. Typi- cally, moving the analog-digital boundary closer to the outside world increases the bit rate across it.
对于模拟电路来说，技术的发展并不那么有益。因此，信号处理功能从模拟域转移到数字域的趋势是，除了允许更高的精度外，还可以节省功耗和硅面积，提高鲁棒性，加快设计过程，带来灵活性和可编程性，并增加设计重用的可能性。在许多应用中，系统的输入和输出信号本质上是模拟的，无法实现全数字;至少在接口上需要在模拟和数字之间进行转换。通常，将模拟数字边界移近外部世界会增加其比特率。

In telecommunications systems the trend to boost bit rates is based on em- ploying wider bandwidths and a higher signal-to-noise ratio. At the same time radio architectures in many applications are evolving towards software-defined radio, one of the main characteristics of which is the shifting of the analog-digital boundary closer to the antenna. Because of these trends, there is an urgent need for data converters with increasing conversion rates and resolution. A part of
在电信系统中，提高比特率的趋势是基于采用更宽的带宽和更高的信噪比。与此同时，许多应用中的无线电架构正在向软件定义无线电发展，其主要特征之一是模拟数字的转变边界更靠近天线。由于这些趋势，迫切需要具有更高转化率和分辨率的数据转换器。的一部分

this needed performance upgrade comes with the technology evolution, but of- ten the demand is higher than this alone can provide. Thus, there is still room and need for innovations in circuit design.
这种所需的性能升级伴随着技术的发展而来，但OF TEN 的需求高于仅此一项所能提供的需求。因此，电路设计仍有创新空间和需求。

The increasing integration level leads to systems with a smaller number of chips, the ultimate goal being a single chip solution, the system on a chip (SoC). This means that analog and digital circuits have to live on the same silicon die, which brings additional challenges in analog design, such as mixed signal issues and limitations in the choice of technology. Data converters are inherently mixed-signal circuits and face the same challenges on a smaller scale even without going as far as SoC. Furthermore, the evolution of technology has been driven by the microprocessor industry and hence does not always go in the best direction for analog. However, the recent rapid growth of the wireless telecommunications devices market has given a boost to the development of advanced mixed signal technologies, such as silicon germanium-based BiCMOS. The main challenges in data converter design are decreasing supply volt- age, short channel effects in MOS devices, mixed signal issues, the development of design and simulation tools, and testability. In analog-to-digital convert- ers (ADCs), they need to be met at the same time as the requirements for sampling, linearity, conversion rate, resolution, and power consumption are be- coming tighter. This course will address these issues, including analysis of the
集成度的提高导致系统具有更少的芯片，最终目标是单芯片解决方案，即片上系统 （SoC）。这意味着模拟和数字电路必须位于同一硅芯片上，这给模拟设计带来了额外的挑战，例如混合信号问题和技术选择的限制。数据转换器本质上是混合信号电路，即使没有 SoC 的进一步发展，在较小的规模上也面临着相同的挑战。此外，技术的发展是由微处理器行业推动的，因此并不总是朝着模拟的最佳方向发展。然而，最近无线通信设备市场的快速增长推动了先进的混合信号技术的发展，例如基于硅锗的 BiCMOS。数据转换器设计的主要挑战是降低电源电压、MOS 器件中的短通道效应、混合信号问题、设计和仿真工具的开发以及可测试性。在模数转换器 （ADC） 中，需要同时满足这些要求，同时对采样、线性度、转换速率、分辨率和功耗的要求越来越严格。本课程将解决这些问题，包括分析

circuit toplogies of the various required components.
各种所需元件的电路拓扑。

Basic semiconductor concepts
基本半导体概念

The pn junction
pn结

If one dopes silicon with a pentavalent impurity, i.e. atoms of an element having a valence of five, or equivalently, five electrons in the outer shell available when bonding with neighbouring atoms, there will be an extra free electron for every impurity atom (assuming none recombines with the holes). These free electrons can be used to conduct current. A pentavalent impurity (e.g. P or As) is said to donate free electrons to the silicon crystal, and so the impurity is known as a donor. These impurities are also called n-type dopants since the free carriers resulting from their use have a negative charge. Similarly, if one dopes silicon with atoms having a valence of three, e.g. with boron (B), each of the impurity atoms accepts one one electron from the silicon crystal so that they may form covalent bonds in the lattice structure. Thus each impurity atom results in a vacancy or hole of positive charge, i.e. a trivalent impurity is an acceptor or a p-type dopant. It should emphasized that a piece of n-type or p- type silicon is electrically neutral; the majority free carriers (electrons in n-type silicon and holes in p-type silicon) are netralized by bound charges associated with the impurity atoms.
如果用五价杂质掺杂硅，即当与相邻原子键合时，外壳中具有5 个价态或 5 个电子的元素的原子，则每个杂质原子将有一个额外的自由电子（假设没有与空穴重新结合）。这些自由电子可用于传导电流。据说五价杂质（例如 P 或As）会向硅晶体提供自由电子，因此该杂质称为供体。这些杂质也称为n 型掺杂剂，因为它们使用产生的游离载流子带有负电荷。同样，如果用价为 3 的原子掺杂硅，例如用硼 （B），则每个杂质原子都从硅晶体中接受一个 1 电子，以便它们可以在晶格结构中形成共价键。因此，每个杂质原子都产生一个带正电荷的空位或空穴，即三价杂质是受体或 p 型掺杂剂。 它应该强调一块 n 型或 p 型硅是电中性的;大多数自由载流子（n 型硅中的电子和p 型硅中的空穴）被与杂质原子相关的束缚电荷净化。

A pn junction or diode is a semiconductor with one part doped n-type
pn 结或二极管是具有一部分掺杂 n 型的半导体

adjacent to another part doped p-type (Fig.1). The large number of free positive carriers, holes, in the p side will tend to diffuse into the n side, where the free electrons in the n side will tend to diffuse to the p side. As the two types of carriers diffuse together, they recombine. Every electron that diffuses from the n side to the p side leaves behind a bound positive charge close to the transition region. Similarly, every hole that diffuses from the p side leaves behind a bound electron near the pn interface. This results in a region without mobile carriers, a depletion or space−charge region, at the pn interface (Fig.2a). The charges on both sides of the depletion region cause an electric field to be established across the region; hence a potential difference results across the region, with the n side at a positive voltage relative to the p side (Fig.2b). This field opposes further diffusion of holes into the n region and electrons into the p region, i.e. the voltage drop across the depletion region acts as a barrier. The bound charges are like two plates of a capacitor and so also give rise to a parasitic capacitance
与另一个掺杂p 型零件相邻（图 1）。 p 侧的大量自由正载流子、空穴将倾向于扩散到 n 侧，而n 侧的自由电子将倾向于扩散到 p 侧。当两种类型的载流子扩散在一起时，它们会重新组合。每个从n侧扩散到p 侧的电子都会在过渡区附近留下一个束缚的正电荷。同样，从p侧扩散的每个空穴都会在 pn 界面附近留下一个束缚电子。 这导致该地区没有移动运营商，adepletionorspace−charg eregionatt hepninterface（Fig2a）Thechargeson耗尽区的两侧都会产生电场在整个地区建立;因此，在整个区域内产生电位差，其中n侧相对于 p 侧处于正电压（图 2b）。该场反对空穴进一步扩散到 n 区，电子进一步扩散到 p 区，即耗尽区的电压降起到屏障的作用。束缚电荷就像电容器的两块板，因此也会产生寄生电容

Figure 1: Simplified physical structure of the junction diode.
图 1：结二极管的简化物理结构。

called the depletion or junction capacitance.
称为耗尽型或结电容。

If the pn junction is reverse biased, i.e. the p side connected to the negative terminal and the n side to the positive terminal of a DC source (a p side to n side voltage of V₀ or less), the depletion region increases and no appreciable current flows. On the other hand, a positive voltage applied from the p side to the n side of a diode reduces the electric field opposing the diffusion of free carriers across the depletion region. The width of the depletion region is also reduced. If the forward voltage is large enough (a p side to n side voltage of V₀ or higher), the carriers will start to diffuse across the junction, resulting a current flow from the p to the n side. For Silicon, appreciable diode current starts to occur for a forward-bias voltage around 0.5V. An idealised IV characteristic of a pn junction is shown in Figure 3.
如果pn结是反向偏置的，即 p侧连接到负端，n侧连接到直流电源的正端（ap侧到V₀或更低的 n侧电压），耗尽区增加，没有明显的电流流过。另一方面，从二极管的p侧到n 侧施加的正电压会减小电场，从而阻止自由载流子在耗尽区的扩散。耗尽区的宽度也减小了。如果正向电压足够大（p侧到n侧的电压为V₀或更高），载流子将开始在结处扩散，导致电流从 p 侧流向 n 侧。对于硅，当正向偏置电压约为 0.5V 时，开始产生明显的二极管电流。 pn 结的理想化 IV 特性如图 3 所示。

MOS Field-Effect Transistors (MOSFETs)
MOS场效应晶体管 （MOSFET）

CMOS circuits normally use two complementary types of transistors - n-channel and p-channel. n-channel devices conduct with a positive gate voltage, while p-channel devices conduct with a negative gate voltage. Electrons are used to conduct current in n-channel transistors, while holes are used in p-channel transistors. Figure 4 shows the physical structure of the n-channel enhancement- type MOSFET. The transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that provides physical support for the device (and for the entire circuit in the case of an integrated circuit). Two heavily doped n-type regions, n⁺ source and n⁺ drain regions, are created in the substrate. A thin layer of silicon dioxide (SiO₂) of thickness t_ox (typically 2-50nm), which is an excellent insulator, is grown on the surface of the substrate, covering the area between the source and drain regions. Metal is deposited on top of the oxide layer to form the gate electrode of the device (in fact, modern MOSFETs are fabricated using a process known as silicon-gate technology in which polysil- icon, which is heavily doped noncrystalline (or amorphous) silicon, is used to form the gate electrode). Metal contacts are also made to the source region, the drain region, and the substrate, also known as the body. The gate is electri-
CMOS电路通常使用两种互补类型的晶体管 - n 沟道和 p 沟道。n 沟道器件以正栅极电压导通，而p 沟道器件以负栅极电压导通。电子用于在 n 沟道晶体管中传导电流，而空穴用于 p 沟道晶体管。图 4 显示了 n 沟道增强型 MOSFET 的物理结构。晶体管在 p 型衬底上制造，p 型衬底是一种单晶硅晶片，为器件（在集成电路的情况下，为整个电路）提供物理支持。在衬底中产生了两个重掺杂的 n 型区域，即 n⁺source和n⁺drain区域。在衬底表面生长一层厚度为 t_ox（通常为 2-50nm）的二氧化硅 （SiO₂） 薄层，这是一种极好的绝缘体，覆盖了源极和漏极区域之间的区域。金属沉积在氧化层的顶部以形成器件的栅极（事实上，现代MOSFET是使用称为硅栅技术的工艺制造的，其中 polysil-icon，即大量掺杂的非结晶（或非晶态）硅，用于形成栅极电极）。金属触点也连接到源极区域、漏极区域和基板，也称为主体。大门是带电的

Figure 2: (a) The pn junction with no applied voltage (open-circuited termi- nals). (b) The potential distribution along an axis perpendicular to the junction.
图 2：（a） 未施加电压的 pn 结（开路端）。（b） 沿垂直于结的轴的电位分布。

Figure 3: The IV characteristic of a silicon junction diode.
图 3：硅结二极管的 IV 特性。

Figure 4: Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 µm, W = 0.2 to 100 µm, and the thickness of the oxide layer (t_ox) is in the range of 2 to 50 nm.
图 4：增强型 NMOS 晶体管的物理结构：（a） 透视图;（b） 横截面。通常 L = 0.1 至 3 μm，W = 0.2 至 100 μm，氧化层 （tox） 的厚度在 2 至 50 nm 范围内。

cally isolated from the channel by the SiO₂ and affects the channel (and hence, the transistor current) only through electrostatic coupling, similar to capaci- tive coupling. Therefore, the gate never conducts dc current. Normally, the p substrate is connected to the most negative voltage in the circuit which in analog circuits might be the negative power supply, but in digital circuits it is normally ground or 0 V . This connection results in all transistors placed in the substrate being surrounded by reverse-biased junctions, which electrically isolates the transistors and thereby prevent conduction through the substrate between transistors.
通过SiO₂与通道隔离，并且仅通过静电耦合影响通道（因此，晶体管电流），类似于电容耦合。因此，栅极永远不会传导直流电流。通常，p 衬底连接到电路中最负的电压，在模拟电路中可能是负电源，但在数字电路中，它通常是接地或0V此连接导致放置在衬底中的所有晶体管都被反向偏置结包围，从而在电气上隔离晶体管，从而防止晶体管之间通过衬底传导。

Basic operation
基本操作

With no bias voltage applied to the gate, two back-to-back diodes exist in series between drain and source. One diode is formed by the pn junction between the n⁺ drain region and the p-type substrate, and the other diode is formed by the pn junction between the p-type substrate and the n⁺ source. These diodes prevent current conduction from drain to source when a voltage V_DS is applied. Now consider the case where the source, drain and substrate are all connected to ground, Fig.5. In this case, the MOS transistor operates similarly to a capacitor. The gate acts as one plate of the capacitor, and the surface of the silicon, just under the thin insultaing SiO₂, acts as the other plate. For small positive gate voltages, the positive carriers in the channel under the gate are initially repulsed and the channel changes from a p-doping level to a depletion region. As a more positive gate voltage is applied, the gate attracts negative charge from the source and drain regions, and the channel becomes an n region with mobile electrons connecting the drain and source regions. In short, a sufficiently large positive gate-source voltage changes the channel beneath the gate to an n region, and the channel is said to be inverted. The gate-to-source voltage, V_CS, for which
由于没有向栅极施加偏置电压，漏极和源极之间有两个背靠背二极管串联。一个二极管由 n⁺漏极区和 p 型衬底之间的 pn 结形成，另一个二极管由 p 型衬底和n⁺源极之间的pn结形成。当施加电压V_DS时，这些二极管可防止电流从漏极传导到源极。现在考虑源极、漏极和衬底都接地的情况，图 5。在这种情况下，MOS晶体管的工作原理类似于电容器。栅极充当电容器的一块板，而硅表面（就在薄绝缘 SiO₂ 下方）充当另一块板。对于小的正栅极电压，栅极下方通道中的正载流子最初被排斥，通道从p 掺杂能级变为耗尽区。当施加更正的栅极电压时，栅极会从源极和漏极区域吸引负电荷，并且通道变成一个n区域，移动电子连接漏极和源极区域。简而言之，足够大的正栅极-源极电压将栅极下方的沟道变为n区，该沟道称为倒置。栅源电压 V_CS，其中

Figure 5: The enhancement-type NMOS transistor with a positive voltage ap- plied to the gate. An n channel is induced at the top of the substrate beneath the gate.
图 5：增强型 NMOS 晶体管，正电压接合到栅极。在栅极下方的衬底顶部感应出一个n通道。

the concentration of electrons under the gate is equal to the concentration of holes in the p substrate far from the gate is known as the threshold voltage, V_tn, and typically lies in the range 0.5 V to 1.0 V.
栅极下的电子浓度等于远离栅极的 P 衬底中空穴的浓度，称为阈值电压，Vtnand 通常位于 0.5 V 至 1.0 V 的范围内。

V_eff = V_CS — V_tn (1)
Veff= VCS— Vtn（1）

The charge density of the electrons is then given by
电子的电荷密度由下式给出

_n = C_ox (V_CS — V_tn) (2)
n= 考克斯（VCS— Vtn） （2）

Here, C_ox, is the gate capacitance per unit area and is given by
其中，Cox是每单位面积的栅极电容，由下式给出

Cox

= Koxo0
= 科索0

tox

(3)

C_gs = C_oxW G (4)
Cgs= CoxW G （4）

where WL is the effective gate area, i.e. W is the gate width and L is the effective gate length. The gate capacitance is one of the major load capacitances that
其中 WL 是有效栅极面积，即 W 是栅极宽度，L 是有效栅极长度。栅极电容是主要的负载电容之一，它

circuits must be capable of driving. It is also important because when a MOS transistor is being turned off, the channel charge must flow from under the gate out through the terminals to other places in the circuit.
电路必须能够驱动。这也很重要，因为当 MOS 晶体管关闭时，通道电荷必须从栅极下方流出，通过端子流到电路中的其他位置。

Next, with V_CS > V_tn, if the drain voltage V_DS in increased above 0 V, a drain-source potential difference exists which results in a current flowing from drain to source, I_D. The relationship between I_D and V_DS is the same as for a resistor, assuming V_DS is small, and is given by
接下来，对于 V_CS> V_tn，如果漏极电压 V_DS增加到 0 V 以上，则存在漏源电位差，导致电流从漏极流向源极 I_D。I_D和 V_DS 之间的关系与电阻器的关系相同，假设V_DS很小，由下式给出

W

W

v_d = µnE (7)
vd= μnE （7）

has been used, where v_d is the drift velocity of electrons, µn is the electron mobility and E is the applied electric field.
，其中 V_D是电子的漂移速度，μn 是电子迁移率，E是施加的电场。

It is important to point out that the channel does not become inverted sud- denly, but rather gradually. In most circuit applications, non-cutoff MOSFETs are operated in strong inversion, with V_eff > 100 mV (many designers use
需要指出的是，通道不会突然倒置，而是逐渐倒置。在大多数电路应用中，非截止 MOSFET在强逆变下工作，V_eff>为 100mV（许多设计人员使用

Figure 6: Operation of the enhancement NMOS transistor as V_DS is increased. The induced channel acquires a tapered shape, and its resistance increases as V_DS is increased. Here, V_CS is kept constant at a value > V_tn
图 6：随着 VDSis 的增加，增强型 NMOS 晶体管的运行情况。感应通道呈锥形，其电阻随着 VDSis 的增加而增加。这里，VCSis 保持恒定在 Vtn >值.

Figure 7: The drain current I_D versus the drain-to-source voltage V_DS for an enhancement-type NMOS transistor operated with V_CS > V_tn
图 7：使用 V_CS>V_tn 工作的增强型NMOS晶体管的漏极电流 _{I D}与漏源电压 V_DS 的关系.

Figure 8: An n-channel enhancement-type MOSFET with V_CS and V_DS applied and with the normal directions of current flow indicated. (b) The I_D–V_DS characteristics for a device with k'_n (W/L) = 1.0 mA/V²
图 8：应用 VCS 和 VDS 并指示电流法向的 n 沟道增强型 MOSFET。（b） k'n（W/L） = 1.0 mA/V2 的器件的 ID-VDS 特性.

V_eff > 200 mV ). Weak inversion occurs when V_CS is approx. 100 mV or less above V_tn
V_有效> 200 mV ）。当 V_CS约为V_tn 以上 100 mV或更低.

The circuit of Figure 8a is used to determine the current-voltage character- istics of a MOSFET (Fig.8b). In the triode region, it can be shown that the drain current is given by
图 8a 的电路用于确定 MOSFET 的电流-电压特性（图 8b）。在三极管区域中，可以显示漏极电流由下式给出

2

(8)

where kn' = µnC_ox is the process transconductance parameter; its value is
其中 kn= μnCox是过程跨导参数;其值为

determined by the fabrication technology. In the active region, the drain current
由制造技术决定。在有源区域中，漏极电流

is given by
由下式给出

— V )² (9)
— V ）2（9）

Exercise 1 Dram the cross−section of a p−channel MOSFEf fabricated on a p−type substrate and explain clearly the operation of this device.
练习 1 简要介绍在 p-type 衬底上制造的 p-通道 MOSFEf 的横截面，并清楚地解释该器件的工作原理。

CMOS processing and layout
CMOS处理和布局

IC fabrication basics
IC制造基础知识

To develop a fundamental understanding of CMOS integrated circuit design and layout, a good understanding of the fabrication processes is necessary. CMOS integrated circuits are formed by patterning different layers on and in the silicon wafer. This wafer is doped with acceptor atoms such as boron for a p-type wafer (this is the most common substrate used in CMOS processing), or donor atoms such as phosphorous for an n-type wafer. When designing CMOS ICs with a p-type wafer, n-channel MOSFETs (NMOS for short) are fabricated directly on the p-type wafer, while p-channel transistors, PMOS, are fabricated in an n−mell (Depending on the choice of starting material (substrate), CMOS processes can be identified as n−mell, p−mell or tmin−mell processes)
要对 CMOS 集成电路设计和布局有基本的了解，必须对制造过程有很好的了解。CMOS 集成电路是通过在硅晶片上和硅晶片中对不同层进行图案化而形成的。该晶圆掺杂了受体原子，例如用于 p 型晶圆的硼（这是 CMOS 加工中最常用的衬底），或用于 n 型晶圆的供体原子，例如磷。在设计具有 p 型晶圆的 CMOS IC 时，n 沟道 MOSFET（简称 NMOS）直接在 p 型晶圆上制造，而 p 沟道晶体管 PMOS 则在 n-mell 中制造（根据起始材料（衬底）的选择，CMOS 工艺可以确定为 n-mellp-mell 或 tmin-mell 工艺）.

The following sequence of events apply, in a fundamental way, to any layer that we need to pattern. We start out with a clean, bare wafer, as shown in Fig. 9a. The distance given by the line A to B will be used as a reference is Figs. 9b-j, which are cross-sectional views of the dashed line shown in (a) . The small box in Fig. 9a is drawn with a layout program (and used for mask generation) to indicate where to put the patterned layer.
以下事件序列从根本上适用于我们需要 pattern 的任何层。我们从一块干净的裸晶圆开始，如图1 所示。9a.线 A 到 B 给出的距离将用作参考，如图所示。9b-j，它们是虚线的横截面图，如图 9a 中的小框是用布局程序绘制的（用于掩模生成），以指示将图案层放置的位置。

First an oxide, SiO₂ or glass, a very good insulator is grown on the wafer.
首先在晶圆上生长氧化物 SiO2 或玻璃，这是一种非常好的绝缘体。

This is done using a reaction with steam, H₂O, or with O₂ alone. The oxide resulting from the reaction with steam is called a wet oxide, while the reaction with O₂ is a dry oxide. Both are called thermal oxides due to the increased temperature used during oxide growth. Next, a photosensitive resist layer is spun across the wafer (Fig. 9)¹ . After the resist is baked, the mask derived from the layout program, Figs. 9e and f, is used to selectively illuminate areas of the wafer, Fig. 9g. The photoresist is developed (Fig. 9h), removing the areas that were illuminated. This process illustrated here is a positive resist process because the area that was illuminated is removed. A negative resist process removes the areas of resist that were not exposed to the light.
这是通过与蒸汽、H₂O 或单独与 O₂ 反应来完成的。与蒸汽反应产生的氧化物称为湿氧化物，而与 O₂ 的反应是干氧化物。由于氧化物生长过程中使用的温度升高，因此两者都被称为热氧化物。接下来，在晶圆上旋转光敏光刻胶层（图 D）。9）¹ .光刻胶烘烤后，使用从布局程序（图 9e 和 f）得出的掩模选择性地照亮晶圆的区域，图 9e 和 f。9g.显影光刻胶（图 D）。9h），删除被照亮的区域。此处说明的这个过程是一个正性光刻胶过程，因为被照亮的区域被去除了。负性光刻胶工艺去除了未暴露在光线下的光刻胶区域。

The next step in the patterning process is to remove the exposed oxide areas (Fig. 9i). Notice that the etchant etches under the resist, causing the opening in the oxide to be larger than what was specified by the mask. Fig. 9j shows the cross-sectional view of the opening after the resist has been removed. Because creating the masks is expensive, lowering the number of masks is equated with lowering the cost of a process. Standard CMOS processes require only 10 to 12 masking levels (compared with e.g. 15 to 20 for BiCMOS).
图案化过程的下一步是去除暴露的氧化物区域（图 9i）。请注意，蚀刻剂在光刻胶下方蚀刻，导致氧化物中的开口大于掩模指定的开口。图 9j 显示了去除光刻胶后开口的横截面图。由于创建掩码的成本很高，因此减少掩码的数量等同于降低过程的成本。标准 CMOS 工艺只需要 10 到 12 个掩蔽级别（而 BiCMOS 则需要 15 到 20 个掩蔽级别）。

n-Well CMOS process
n-WellCMOS工艺

1 Note that the dimensions of the layers, i.e. oxide, resit and wafer are not drawn to scale. Typical wafer thickness is ~ 500µm while thickness of grown oxide or spun resist is ~ 1µm
1 请注意，层的尺寸，即氧化物、reit 和 wafer 不是按比例绘制的。典型的晶圆厚度为 ~ 500μm，而生长的氧化物或纺丝光刻胶的厚度为 ~ 1μm.

Figure 9: Generic sequence of events used in photo patterning.
图 9：照片图案化中使用的通用事件序列。

Define n-well diffusion (mask #1)
定义 n 孔扩散（掩码 #1）

Define active regions (mask #2)
定义活动区域（蒙版 #2）

LOCOS oxidation
LOCOS氧化

n+ diffusion (mask #4)
n+ 扩散（掩码 #4）

p+ diffusion (mask #5)
P+ 扩散（掩码 #5）

(d) Contact holes (mask #6)
（d） 接触孔（面罩 #6）

(d) Polysilicon gate (mask #3) (h) Metallization (mask #7)
（d） 多晶硅栅极（掩模 #3）（h） 金属化（掩模 #7）

Figure 10: A typical n-well CMOS process flow.
图10：典型的 n 阱 CMOS 工艺流程。

for n-well diffusion. The unexposed regions will be protected from the n-type phosphorous impurity.
用于 N 孔扩散。未曝光的区域将受到保护，免受 n 型磷杂质的影响。

The second step is to define the active region (where transistors are to be placed) using a technique called local oxidation (LOCOS). A silicon nitride (Si₃N₄) layer is deposited and patterned relative to the previous n-well re- gions (Fig.10b). The nitride-covered regions will not be oxidized. After a long wet oxidation step, thick field-oxide will appear in regions between transistors (Fig.10c). This thick field-oxide is necessary for isolating the transistors. It also allows interconnection layers to be routed on top.
第二步是使用称为局部氧化 （LOCOS） 的技术定义有源区域（晶体管放置的位置）。氮化硅 （Si₃N₄） 层沉积并相对于之前的 n 阱重新形成图案化（图 10b）。氮化物覆盖的区域不会被氧化。经过漫长的湿式氧化步骤后，晶体管之间的区域会出现厚场氧化物（图 10c）。这种厚的场氧化物对于隔离晶体管是必需的。它还允许在顶部布线互连层。

The next step is the formation of the polysilicon gate (Fig.10d). This is one of the most critical steps in the CMOS process. The thin oxide layer in the active region is first removed using wet etching followed by the growth of a high quality thin gate oxide (0.13 µm and 0.18 µm processes use oxide thicknesses
下一步是形成多晶硅栅极（图 10d）。这是CMOS 工艺中最关键的步骤之一。首先使用湿法蚀刻去除活性区域中的薄氧化层，然后生长出高质量的薄栅极氧化物（0.13μm和0.18μm工艺使用氧化层厚度

as thin as 2nm to 50nm). A polysilicon layer, usually arsenic doped (n type), is then deposited and patterned. The photolithography is most demanding in this step, since the finest resolution is required to produce the shortest possible MOS channel length.
薄至 2nm 至 50nm）。然后沉积多晶硅层，通常是掺砷（n 型），并形成图案化。在此步骤中，光刻技术要求最高，因为需要最精细的分辨率来产生尽可能短的 MOS 通道长度。

The polysilicon gate is a self−aligned structure. A heavy arsenic implant can be used to form the n+ source and drain regions of the n-MOSFETs. The polysilicon acts as a barrier for this implant to protect the channel region. A layer of photoresit can be used to block the regions where the p-MOSFETs are to be formed (Fig.10e). The thick field-oxide stops the implant and prevents n+ regions forming outside the active regions. A reversed photolithography step can be used to protect the n-MOSFETs during the p+ boron source and drain implant for the p-MOSFETs (Fig.10f). In both cases the separation between the source and drain diffusions - the channel length - is defined by the polysilicon gate mask alone, hench the self-alignment.
多晶硅栅极是一种自对准结构。重砷植入物可用于形成 n-MOSFET 的 n+ 源极和漏极区域。多晶硅充当该植入物的屏障，以保护通道区域。可以使用一层photoresit来阻挡要形成 p-MOSFET的区域（图 10e）。厚场氧化物会阻止植入物并防止在活动区域之外形成n+区域。在 p-MOSFET 的 p+ 硼源极和漏极注入过程中，可以使用反向光刻步骤来保护 n-MOSFET（图 10f）。在这两种情况下，源极和漏极扩散之间的分离 - 沟道长度 - 仅由多晶硅栅极掩膜定义，与自对准有关。

A thick layer of CVD² oxide is next deposited over the entire wafer before contact holes are opened. A photomask is used to define the contact window opening (Fig.10g) followed by a wet or dry oxide etch. A thin aluminium layer is then evaporated or sputtered onto the wafer. A final masking and etching step is used to pattern the interconnection (Fig.10h). A final passivation step the follows prior to packaging and wire bonding in which a thick CVD oxide or pyrex glass is deposited on the wafer to serve as a protective layer. A minimum of 7 masking levels are necessary, but in practice additional levels such as n and p guards for better latch-up immunity, a second polysilicon layer for capacitors, and multilayer metals for high-density interconnections are used.
在打开接触孔之前，接下来在整个晶圆上沉积一层厚厚的 CVD²氧化物。光掩模用于定义接触窗口开口（图 10g），然后是湿式或干式氧化物蚀刻。然后，薄铝层蒸发或溅射到晶圆上。最后的掩蔽和蚀刻步骤用于对互连进行图案化（图 10h）。在封装和引线键合之前，最后的钝化步骤如下，其中厚的 CVD 氧化物或耐热玻璃沉积在晶圆上以用作保护层。至少需要 7 个掩蔽级别，但在实践中使用额外的级别，例如用于更好闩锁抗扰度的 n 和 p 保护、用于电容器的第二个多晶硅层以及用于高密度互连的多层金属。