Fully integrated electrophysiology interface chip with 16 channels of low-noise amplifiers and constantcurrent stimulators controlled by industry-standard serial peripheral interface (SPI) 具有 16 个低噪声放大器和恒定电流刺激器的完全集成电生理接口芯片，由行业标准串行外围接口（SPI）控制
Stimulators source and sink currents ranging from 10 nA to 2.55 mA over a 14 V range with integrated compliance monitors 刺激器在整合的合规监测器范围内，源和汇电流范围从 10 nA 到 2.55 mA，范围为 14 V。
Integrated charge-recovery circuits and fault current detection 集成充电恢复电路和故障电流检测
Low input-referred noise: typical 低输入参考噪声: 典型
ADC operation to 714 kSamples per second; supports sampling 16 amplifier channels at each ADC 操作每秒 714 kSamples；支持每个 采样 16 个放大器通道
Standard four-wire 32-bit SPI interface with CMOS or low-voltage differential signaling (LVDS) I/O pins 标准的四线 32 位 SPI 接口，带有 CMOS 或低压差分信号（LVDS）I/O 引脚
Upper cutoff frequency of all amplifiers set by on-chip registers; adjustable from 100 Hz to 20 kHz 所有放大器的上限截止频率由芯片上的寄存器设置；可调节范围从 100 赫兹到 20 千赫兹
Lower cutoff frequency of all amplifiers set by on-chip registers; adjustable from 0.1 Hz to 1 kHz 所有放大器的下截止频率由芯片上的寄存器设置；可调节范围从 0.1 赫兹到 1 千赫兹
Fast amplifier artifact recovery for post-stimulus recording 后刺激记录的快速放大器工件恢复
Integrated multi-frequency in situ electrode impedance measurement capability 集成多频在位电极阻抗测量能力
Individual amplifier and stimulator power up/down for power minimization 个别放大器和刺激器的上电/下电以实现功耗最小化
Applications 应用程序
Miniaturized multi-channel headstages for neural recording and stimulation 小型化的多通道头戴式电极用于神经记录和刺激
Low-power wireless headstages or backpacks for electrophysiology experiments 用于电生理实验的低功耗无线头戴式设备或背包
Multielectrode array (MEA) in vitro recording and stimulation systems 多电极阵列（MEA）体外记录和刺激系统
Digital Electrophysiology Stimulator/Amplifier Chip 数字电生理刺激器/放大器芯片
20 January 2016; updated 13 May 2021 2016 年 1 月 20 日；更新于 2021 年 5 月 13 日
See page 15 for important addendum from May 2021 请查看 2021 年 5 月的重要附录，见第 15 页
Description 描述
The Intan Technologies RHS2116 microchip is a complete bidirectional electrophysiology interface system. This device contains an array of 16 stimulation/amplifier blocks. Each channel includes a low-noise amplifier with programmable bandwidth and a constant-current stimulator with programmable amplitude. Intan Technologies RHS2116 微芯片是一种完整的双向电生理接口系统。该设备包含一个由 16 个刺激/放大器块组成的阵列。每个通道包括一个带可编程带宽的低噪声放大器和一个带可编程幅度的恒定电流刺激器。
The RHS2116 is suitable for a wide variety of biopotential interfacing applications. Innovative circuit architecture combines stimulators, amplifiers, analog and digital filters, a multiplexed 16 -bit analog-to-digital converter (ADC), and a flexible electrode impedance measurement module on a single silicon chip. In practice, an array of electrodes are connected directly to one side of the chip, and a digital bus on the other side is used to control stimulation and read digitized electrode signals. RHS2116 适用于各种生物电接口应用。创新的电路架构将刺激器、放大器、模拟和数字滤波器、多路复用的 16 位模数转换器（ADC）以及灵活的电极阻抗测量模块集成在单个硅片上。在实践中，一组电极直接连接到芯片的一侧，另一侧的数字总线用于控制刺激和读取数字化的电极信号。
The bandwidths of the amplifiers may be dynamically programmed by means of internal registers on each chip. This flexibility allows the chips to be optimized for different types of signals. Integrated charge-recovery circuits and fast amplifier settling can be employed following stimulation pulses to minimize residual artifacts. 放大器的带宽可以通过每个芯片上的内部寄存器动态编程。这种灵活性使得芯片可以针对不同类型的信号进行优化。在刺激脉冲后可以使用集成的电荷恢复电路和快速放大器定位来最小化残留伪影。
A low-distortion, high-speed analog multiplexer (MUX) allows all the amplifiers to share one on-chip ADC. The ADC can sample each channel up to . Additional on-chip circuitry enables in situ electrode impedance measurements at user-programmable frequencies. By interfacing electrodes directly with a digital command and data stream, the RHS2116 replaces all analog instrumentation circuitry in electrophysiology monitoring and stimulation systems. 一种低失真、高速模拟多路复用器（MUX）允许所有放大器共享一个芯片上的 ADC。ADC 可以对每个通道进行采样，最多达到 。额外的芯片电路使得用户可以在现场以可编程频率进行电极阻抗测量。通过直接将电极与数字命令和数据流接口，RHS2116 替代了电生理监测和刺激系统中的所有模拟仪器电路。
RHS2116 chips are packaged in standard QFN surface mount packages, or available in bare die form. The small footprint and low power consumption of the multichannel chips enable the miniaturization of front end electronics for miniature headstages and other portable biopotential interface systems. RHS2116 芯片采用标准 QFN 表面贴装封装，或以裸片形式提供。多通道芯片的小尺寸和低功耗使得前端电子设备可以被微型化，用于微型头戴式和其他便携生物电接口系统。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Simplified Chip Diagrams 简化芯片图解
RHS2000-SERIES FAMILY RHS2000 系列家族
There is currently one device in the RHS2000-series electrophysiology interface family: the RHS2116, which is described in this datasheet. The following table lists the features of this chip: 目前 RHS2000 系列电生理接口家族中有一种设备：RHS2116，该设备在本数据表中有详细描述。以下表格列出了该芯片的特点：
DEVICE
放大器/刺激器
每个芯片的通道数
AMPLIFIER/STIMULATOR
CHANNELS PER CHIP
AMPLIFIER INPUT PINS 放大器输入引脚
PACKAGE SIZE 包装尺寸
BARE DIE SIZE 裸芯尺寸
RHS2116
16
16 单极放大器输入;
1 个常见的参考输入
16 unipolar amplifier inputs;
1 common reference input
pin QFN 引脚 QFN
Package Description 包描述
RHS2116 Simplified Diagram RHS2116 简化图解
The RHS2116 contains an array of 16 stimulator/amplifier blocks controlled through a digital SPI interface. Each stimulator/amplifier channel includes two amplifiers for sensing electrode voltages: (1) an AC-coupled high-gain amplifier for observing small electrophysiological signals (e.g., extracellular action potentials, local field potentials) in the range of a few microvolts to a few millivolts; and (2) a DC-coupled low-gain amplifier for monitoring electrode potential in response to stimulation, in the range of tens of millivolts to several volts. The high-gain amplifiers are referenced to a common, shared pin (ref_elec) that can be connected to a low-impedance reference electrode to reduce common-mode interference (e.g., line noise). The low-gain amplifiers are referenced to ground. In many applications, the reference electrode will also be used as the stimulation counter (return) electrode and will be tied to ground. RHS2116 包含一个由 16 个刺激器/放大器模块组成的阵列，通过数字 SPI 接口进行控制。每个刺激器/放大器通道包括两个放大器，用于感测电极电压：(1)用于观察微电压至几毫伏范围内的小电生理信号（例如细胞外动作电位、局部场电位）的交流耦合高增益放大器；以及(2)用于监测电极电位响应刺激的直流耦合低增益放大器，范围为几十毫伏至几伏。高增益放大器参考一个共用引脚（ref_elec），可以连接到低阻抗参考电极以减少共模干扰（例如 线噪声）。低增益放大器参考地。在许多应用中，参考电极也将用作刺激计数（返回）电极，并将接地。
Each channel has an independent stimulator module that can generate biphasic constant-current pulses with amplitudes varying from 10 nanoamps to 2.55 milliamps. These stimulators are capable of maintaining constant current output over a wide range of electrode voltages, with compliance limits near the stimulation voltage supplies VSTIM+ and VSTIM-. Stimulator modules automatically detect electrode voltages exceeding compliance limits and set corresponding register bits. 每个通道都有一个独立的刺激器模块，可以产生幅度从 10 纳安到 2.55 毫安变化的双相恒流脉冲。这些刺激器能够在广泛的电极电压范围内保持恒定的电流输出，其合规限制接近刺激电压供应 VSTIM+和 VSTIM-。刺激器模块会自动检测超过合规限制的电极电压，并设置相应的寄存器位。
Most stimulation protocols use charge-balanced pulses to avoid oxidation-reduction reactions at the electrode-tissue interface. Variations in transistor characteristics across a chip make it impossible to achieve perfect charge balance, so recovery circuits are included to bleed off residual charge after stimulation pulses. A charge recovery switch can be used to briefly connect an electrode to a common stim_GND pin, which is typically tied to ground. Other charge recovery circuits in each channel pull the electrodes toward a user-specified potential with small, programmable currents. A global fault current detector is also included on the chip; this circuit can be inserted into a common return current path and used to detect any unintended current. 大多数刺激协议使用平衡电荷的脉冲，以避免电极-组织界面的氧化还原反应。芯片上晶体管特性的变化使得完美的电荷平衡不可能实现，因此在刺激脉冲后包括恢复电路以释放残余电荷。充电恢复开关可用于短暂连接电极到一个通用的刺激_GND 引脚，通常与地线相连。每个通道中的其他充电恢复电路通过小型可编程电流将电极拉向用户指定的电位。芯片上还包括全局故障电流检测器；该电路可以插入到一个通用回流电流路径中，并用于检测任何意外电流。
PIN
TYPE
FUNCTION
VDD, GND VDD，GND
power 力量
3.3 V 电源（ ). 所有 VDD 引脚必须连接到同一个
潜在。所有 GND 引脚必须连接到相同的地面电位。
3.3 V power supply ( ). All VDD pins must be connected to the same
potential. All GND pins must be connected to the same ground potential.
VSTIM+, VSTIM- VSTIM+，VSTIM-
power 力量
刺激电源。总刺激电源（VSTIM+ - VSTIM-）
可能不超过 14 V。VSTIM+受限于+3.3 V 至+10.7 V 范围内
到地面。 VSTIM- 限制在相对于地面的范围内为-3.3 V 至-10.7 V。
在芯片运行期间必须向这些引脚施加电源，否则
过大的电流将通过 VDD 绘制。不要让它们保持未连接状态。
Stimulation power supplies. The total stimulation power supply (VSTIM+ - VSTIM-)
may not exceed 14 V . VSTIM+ is limited to the range of +3.3 V to +10.7 V with respect
to ground. VSTIM- is limited to the range of -3.3 V to -10.7 V with respect to ground.
Power must be applied to these pins during operation of the chip, otherwise
excessive current will be drawn through VDD. Do not leave these unconnected.
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Electrical Characteristics 电气特性
unless otherwise noted. 除非另有说明。
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNITS
COMMENTS
Size of Packaged RHS2116 包装后的 RHS2116 尺寸
引脚塑料 QFN 封装
厚
pin plastic QFN package
thick
Mass of Packaged RHS2116 包装的 RHS2116 的质量
133
mg 毫克
Size of RHS2116 Bare Die RHS2116 裸片的尺寸
4.74
Bare silicon die ( 0.20 mm thick 裸硅晶片（0.20 毫米厚
Mass of RHS2116 Bare Die RHS2116 裸片的质量
11
mg 毫克
Stimulator/Amplifier Block 刺激器/放大器模块
At the core of the RHS2116 chip is an array of 16 stimulator/amplifier blocks containing the circuitry modules illustrated in the diagram above. These modules perform three basic functions: (1) monitoring the AC and DC voltage on each electrode; (2) delivering constant-current stimulation pulses to the same electrode; and (3) recovering residual charge from the electrode following stimulation pulses. The circuits responsible for these tasks are listed here and described in more detail in the following pages. RHS2116 芯片的核心是一个包含 16 个刺激器/放大器模块的阵列，其中包含上图所示的电路模块。这些模块执行三个基本功能：（1）监测每个电极上的交流和直流电压；（2）向同一电极提供恒定电流的刺激脉冲；以及（3）在刺激脉冲后从电极中恢复残留电荷。负责这些任务的电路在此列出，并在接下来的页面中进行更详细的描述。
AC-Coupled High-Gain Amplifier 交流耦合高增益放大器
Each channel has a high-gain amplifier with a band-pass response that senses electrophysiological signals (e.g., extracellular neural action potentials, local field potentials, electrocorticogram signals) within a range of and a typical noise floor of rms. The upper and lower cutoff frequencies of these amplifiers can be selected by registers. Two different mechanisms are provided for recovering quickly from large voltage artifacts caused by stimulation pulses. Unused amplifiers may be disabled to reduce power consumption. These amplifiers are sampled at 16-bit resolution by the on-chip ADC 每个通道都配备了一个带通响应的高增益放大器，用于感知生理信号（例如细胞外神经动作电位、局部场电位、脑皮层电信号）在 范围内，典型噪声电平为 rms。这些放大器的上限和下限截止频率可以通过寄存器选择。提供了两种不同的机制，用于快速恢复由刺激脉冲引起的大电压伪迹。未使用的放大器可以被禁用以减少功耗。这些放大器通过芯片上的 ADC 以 16 位分辨率进行采样。
The high-gain amplifiers are referenced to a common, shared pin (ref_elec) that can be connected to a lowimpedance reference electrode to reduce common-mode interference (e.g., 50/60 Hz line noise). 高增益放大器参考一个共同的、共享的引脚（ref_elec），可以连接到低阻抗参考电极，以减少共模干扰（例如 50/60 赫兹线噪声）。
DC-Coupled Low-Gain Amplifier 直流耦合低增益放大器
A second DC-coupled amplifier with a wide range (from VSTIM- + 1.2V to VSTIM+ -0.6 V ) can be used to monitor electrode potentials in response to stimulation pulses (e.g., to ensure that electrodes remain inside the "water window" to prevent chemical reactions from occurring). Unused amplifiers may be disabled to reduce power consumption. These amplifiers are sampled at 10-bit resolution by the onchip ADC. 第二个宽范围（从 VSTIM- + 1.2V 到 VSTIM+ -0.6V）的直流耦合放大器可用于监测电极电位对刺激脉冲的响应（例如，以确保电极保持在“水窗口”内，以防止化学反应发生）。未使用的放大器可以禁用以减少功耗。这些放大器通过芯片上的 ADC 以 10 位分辨率进行采样。
Stimulator Current Source and Sink 刺激器电流源和沉没
Constant-current stimulation can be delivered using an integrated current source and current sink. These circuits produce currents with user-specified magnitudes in the range of 10 nA to 2.55 mA . Each current source and sink is controlled by an 8-bit current-output DAC which has an 8-bit "trim" setting that can adjust the current by to compensate for variations between devices. The step size of the current-output DACs is set globally. Each stimulator has a built-in compliance monitor that sets a register bit if the electrode voltage becomes so high or low (i.e., close to VSTIM+ or VSTIM-) that it becomes impossible to deliver the specified current. 恒流刺激可以使用集成的电流源和电流汇进行传递。这些电路产生用户指定幅度范围在 10 nA 至 2.55 mA 之间的电流。每个电流源和电流汇由一个 8 位电流输出 DAC 控制，该 DAC 具有一个 8 位的“修剪”设置，可以通过 来调整电流，以补偿设备之间的差异。电流输出 DAC 的步进大小是全局设置的。每个刺激器都有一个内置的合规性监视器，如果电极电压变得过高或过低（即接近 VSTIM+或 VSTIM-），以至于无法传递指定的电流，则设置一个寄存器位。
All stimulators are disabled until the stim_en pin is pulled to VDD and a specific 32-bit code is programmed into the stim enable registers. This prevents random stimulation from occurring when the chip is first powered up. 所有刺激器在刺激引脚被拉到 VDD 并且特定的 32 位代码被编程到刺激使能寄存器之前都是禁用的。这可以防止芯片首次上电时发生随机刺激。
Charge Recovery Switch 充电恢复开关
Most stimulation protocols use charge-balanced pulses to avoid oxidation-reduction reactions at the electrode-tissue interface. Variations in transistor characteristics across a chip make it impossible to achieve perfect charge balance, so recovery circuits are included to bleed off residual charge after stimulation pulses. Each stimulator/amplifier block includes a charge recovery switch which can be used to briefly connect an electrode to a common stim_GND pin, which is typically tied to ground. This switch has an 'on' resistance on the order of . 大多数刺激协议使用平衡电荷的脉冲，以避免电极-组织界面的氧化还原反应。芯片上晶体管特性的变化使得完美的电荷平衡变得不可能，因此在刺激脉冲后包括恢复电路以释放残余电荷。每个刺激器/放大器块包括一个电荷恢复开关，可以用于短暂连接电极到一个通用的刺激_GND 引脚，通常与地线相连。这个开关的'开'电阻大约为 。
An alternate charge recovery circuit is included in each stimulator/amplifier block. The current-limited (CL) charge recovery circuit pulls the electrode toward a user-specified voltage with a small, programmable current ranging from 1 nA to . The target recovery voltage may be set in the range of . Some stimulation protocols initially hold the electrode at a slightly positive potential when using biphasic pulses that begin with a cathodic (negative) current. This issue is discussed in greater depth below. 每个刺激器/放大器块中都包含一个备用的充电恢复电路。 限流（CL）充电恢复电路使用从 1 nA 到 的小型可编程电流将电极拉向用户指定的电压。 目标恢复电压可以设置在 范围内。 一些刺激协议在使用以阴极（负）电流开始的双相脉冲时，最初将电极保持在略微正电位。 这个问题在下面更深入地讨论。
AC Amplifier Bandwidth AC 放大器带宽
Electrophysiological signals of interest are sensed by an array of AC-coupled low-noise amplifiers with integrated analog filters that can be configured to isolate frequencies of interest and minimize aliasing by attenuating signals above the Nyquist rate (i.e., half the ADC per-channel sampling rate). Each AC high-gain amplifier has a pass band extending from a low-frequency cutoff fi to a high-frequency cutoff . The upper end of the pass band has a 3rd-order Butterworth low-pass filter at the 3-dB frequency . The lower end of the pass band has a -order high-pass filter characteristic at the frequency fL . 感兴趣的电生理信号由一组交流耦合低噪声放大器感知，这些放大器带有集成模拟滤波器，可以配置为隔离感兴趣的频率并通过衰减超过奈奎斯特率（即每通道采样率的一半）的信号来最小化混叠。每个交流高增益放大器的通带从低频截止频率 fi 延伸到高频截止频率 。通带的上端具有一个 3 阶 Butterworth 低通滤波器，其 3dB 频率为 。通带的下端具有一个 阶高通滤波器特性，其频率为 。
The -order Butterworth low-pass filter characteristic at has a maximally flat pass band region with decade ( octave) of attenuation beyond . The diagram below illustrates the analog frequency response of the AC highgain amplifiers: 在 处的 阶 Butterworth 低通滤波器特性具有最大平坦的通带区域，超过 有 个十年（ 个八度）的衰减。下图显示了 AC 高增益放大器的模拟频率响应：
An additional pole of high-pass filtering can be applied using the optional DSP filter module described later in the datasheet. 可以使用后面数据表中描述的可选 DSP 滤波器模块来应用额外的高通滤波极。
Setting Amplifier Bandwidth 设置放大器带宽
Registers 4 and 5 are used to set the upper bandwidth of the high-gain amplifiers ( fH ) in the range of 100 Hz to 20 kHz . Registers 6 and 7 are used to set the lower bandwidth of the high-gain amplifiers ( ) in the range of 0.1 Hz to 1 kHz . Register values for common bandwidths are listed in a table on page 11. For bandwidths not listed on this table, contact Intan Technologies for recommended values. 寄存器 4 和 5 用于设置高增益放大器的上带宽（fH）范围为 100 Hz 至 20 kHz。寄存器 6 和 7 用于设置高增益放大器的下带宽（ ）范围为 0.1 Hz 至 1 kHz。常见带宽的寄存器值列在第 11 页的表格中。对于此表格中未列出的带宽，请联系 Intan Technologies 获取推荐值。
Amplifier Stimulus Artifact Recovery 放大器刺激物伪迹恢复
If an AC-coupled amplifier is subjected to a large voltage pulse (like the artifacts created by stimulation pulses) the amplifier responds with a large step in its output (which may saturate the amplifier) that decays exponentially back to baseline with a time constant equal to . If the amplifier saturates in response to a stimulation pulse, it is effectively blind until its output decays back into its operating range. 如果一个交流耦合放大器受到大电压脉冲的影响（比如刺激脉冲产生的伪迹），放大器会产生一个输出的大跃变（可能会使放大器饱和），然后以一个时间常数等于 的指数方式衰减回基线。如果放大器对刺激脉冲饱和，那么它在输出衰减回操作范围之前实际上是盲目的。
In many situations it is desirable to set quite low to observe low-frequency signals of interest (e.g., local field potentials or electrocorticograms). However, a low value of implies long recovery time from stimulation artifacts: with set to 0.1 Hz , the amplifier recovery time constant is 1.6 seconds! Yet it is often necessary to observe neural activity a few milliseconds following stimulation. 在许多情况下，希望将 设置得非常低，以观察感兴趣的低频信号（例如，局部场电位或电皮层图）。然而， 的低值意味着从刺激伪影中恢复所需的长时间：当 设置为 0.1 赫兹时，放大器恢复时间常数为 1.6 秒！然而，通常需要在刺激后几毫秒内观察神经活动。
The RHS2116 provides two mechanisms for reducing the time required to recovery from a stimulation artifact: lowfrequency cutoff shifting and amplifier fast settle. RHS2116 提供了两种减少从刺激伪影恢复所需时间的机制：低频截止频率移位和放大器快速稳定。
Low-Frequency Cutoff Shifting 低频截止频率偏移
The RHS2116 provides a means to select two different values of (an "A version" and a "B version") and rapidly switch between them to speed up amplifier recovery following stimulation. Registers 6 and 7 select the two value of fl (e.g., 5 Hz for normal recording and 500 Hz for poststimulation recovery) and the amp fL select variable in Register 12 selects which value of is used for each amplifier channel. RHS2116 提供了一种选择两个不同值的 （“A 版本”和“B 版本”）并快速在它们之间切换以加快刺激后放大器恢复的方法。寄存器 6 和 7 选择 fl 的两个值（例如，正常记录为 5 赫兹，刺激后恢复为 500 赫兹），寄存器 12 中的 amp fL 选择变量选择每个放大器通道使用的 的值。
Amplifier Fast Settle 放大器快速安定
It may also be useful to reset the amplifiers if a large stimulation artifact causes the output signals to saturate. The "fast settle" function built into each high-gain amplifier allows users to clamp the output of the amplifier at baseline. To settle the amplifiers, the amp fast settle bit in Register 10 should be set high momentarily and then returned to zero. The recommended duration of a fast settle pulse is ; as the upper bandwidth of the amplifiers is lowered, settling takes more time. Using this guideline, if 如果大幅度刺激伪影导致输出信号饱和，重置放大器可能也会有用。每个高增益放大器内置的“快速稳定”功能允许用户将放大器的输出夹在基线上。为了稳定放大器，应将寄存器 10 中的 amp fast settle 位设置为高，然后立即返回零。快速稳定脉冲的推荐持续时间为 ；随着放大器的上限带宽降低，稳定需要更多时间。根据这个准则，如果
is set to 10 kHz then setting amp fast settle high for , and then low, is sufficient to settle the amplifiers to baseline. 设置为 10 千赫，然后将放大器快速稳定高设置为 ，然后低，就足以使放大器稳定到基线。
Depending on the nature and severity of the stimulation artifacts encountered, either or both of these artifact recovery techniques may be used to optimize amplifier performance. 根据遇到的刺激性伪影的性质和严重程度，可以使用这两种伪影恢复技术中的一种或两种来优化放大器性能。
Recommended Artifact Recovery Procedure 推荐的工件恢复程序
In benchtop testing at Intan Technologies, we found the following procedure to be effective in recovering from artifacts within 1-2 ms following a stimulation pulse delivered to a simple series RC model of an electrode: 在 Intan Technologies 的台式测试中，我们发现以下程序在向电极的简单串联 RC 模型传递刺激脉冲后，在 1-2 毫秒内有效地恢复从伪影中恢复
Set the "A version" of to the desired lower cutoff frequency for recording (e.g., 5 Hz ) (Register 6). 将 的“A 版本”设置为所需的录制下限频率（例如，5 赫兹）（寄存器 6）。
Set the "B version" of to a much higher frequency in the range of 500 to 1000 Hz (Register 7). 将“ ”的“B 版本”设置为 500 至 1000 赫兹的更高频率（寄存器 7）。
Immediately before the onset of a stimulation pulse on channel X, switch the low-frequency cutoff on channel from the "A version" of to the "B version" of (Register 12) 在 X 通道上的刺激脉冲开始之前立即将通道 上的低频截止从 的“A 版本”切换到 的“B 版本”（寄存器 12）
After the stimulation pulse has ended, wait 1 ms before switching back to the "A version" of (Register 12) 刺激脉冲结束后，等待 1 毫秒后再切换回“ （寄存器 12）的“A 版本”
It may be necessary to disable the DSP high-pass filter for offset removal to optimize the recovery speed (Register 1). 可能需要禁用 DSP 高通滤波器以优化恢复速度（寄存器 1）的偏移移除。
The optimum technique for artifact recovery may depend on the particular type of electrode used. Some experimentation may be necessary to find the best parameters for a given situation. 人工物品恢复的最佳技术可能取决于所使用的电极类型。可能需要进行一些实验来找到特定情况下的最佳参数。
In general, artifact recovery time will shorten with higher values of and higher values of the DSP high-pass filter cutoff frequency. Consider using the highest acceptable lower bandwidth in any particular recording application. 通常情况下，随着 的值和 DSP 高通滤波器截止频率的值越高，文物恢复时间会缩短。考虑在任何特定录音应用中使用最高可接受的较低带宽。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
The following settings for variables in Registers 4 and 5 are used to configure the upper bandwidth ( ) of the amplifiers. These settings are identical to the ones used by the RHD2000 series of amplifier chips from Intan Technologies. 变量在寄存器 4 和 5 中的以下设置用于配置放大器的上限带宽（ ）。这些设置与 Intan Technologies 的 RHD2000 系列放大器芯片使用的设置相同。
The following settings for variables in Registers 6 and 7 are used to configure the lower bandwidth (fL) of the amplifiers. These settings are identical to the ones used by the RHD2000 series of amplifier chips from Intan Technologies. 变量在寄存器 6 和 7 中的以下设置用于配置放大器的低频带宽（fL）。这些设置与 Intan Technologies 的 RHD2000 系列放大器芯片使用的设置相同。
LOWER
带宽 fL
LOWER
BANDWIDTH fL
RL sel1
RL sel2
RL sel3
1.0 kHz 1.0 千赫 ertz
10
0
0
500 Hz 500 赫兹
13
0
0
300 Hz 300 赫兹
15
0
0
250 Hz 250 赫兹
17
0
0
200 Hz 200 赫兹
18
0
0
150 Hz 150 赫兹
21
0
0
100 Hz 100 赫兹
25
0
0
75 Hz 75 赫兹
28
0
0
50 Hz 50 赫兹
34
0
0
30 Hz 30 赫兹
44
0
0
25 Hz 25 赫兹
48
0
0
20 Hz 20 赫兹
54
0
0
15 Hz 15 赫兹
62
0
0
10 Hz 10 赫兹
5
1
0
7.5 Hz 7.5 赫兹
18
1
0
5.0 Hz 5.0 赫兹
40
1
0
3.0 Hz 3.0 赫兹
20
2
0
2.5 Hz 2.5 赫兹
42
2
0
2.0 Hz 2.0 赫兹
8
3
0
1.5 Hz 1.5 赫兹
9
4
0
1.0 Hz 1.0 赫兹
44
6
0
0.75 Hz 0.75 赫兹
49
9
0
0.50 Hz 0.50 赫兹
35
17
0
0.30 Hz 0.30 赫兹
1
40
0
0.25 Hz 0.25 赫兹
56
54
0
0.10 Hz 0.10 赫兹
16
60
1
16
0
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Constant-Current Stimulator 恒流刺激器
Each stimulator/amplifier block in the RHS2116 includes a constant-current stimulator capable of driving positive or negative currents ranging in magnitude from 10 nA to 2.55 mA . Each stimulator has an 8 -bit current-output DAC with an 8 -bit trim setting that can adjust the DAC over the range of . The step size of these DACs is set globally by the step DAC variables in Register 34. RHS2116 中的每个刺激器/放大器块都包括一个恒定电流刺激器，能够驱动幅度从 10 nA 到 2.55 mA 的正向或负向电流。每个刺激器都有一个 8 位电流输出 DAC，带有一个 8 位修剪设置，可以在 范围内调整 DAC。这些 DAC 的步长由寄存器 34 中的步长 DAC 变量全局设置。
The following step DAC settings are used to configure the step size of the stimulators. For values not listed on this table, contact Intan Technologies for recommended values. 以下步骤 DAC 设置用于配置刺激器的步长。对于此表中未列出的值，请联系 Intan Technologies 获取推荐值。
刺激器
步长
STIMULATOR
STEP SIZE
全尺寸
范围
FULL SCALE
RANGE
sel1
sel2
sel3
10 nA
64
19
3
20 nA
40
40
1
50 nA
64
40
0
100 nA
30
20
0
200 nA
25
10
0
500 nA
101
3
0
98
1
0
94
0
0
38
0
0
15
0
0
Note: Stimulation currents exceeding are possible if multiple channels are tied together off-chip and stimulation pulses on these channels are coordinated. 注意：如果将多个通道连接在一起并协调这些通道上的刺激脉冲，则可能出现超过 的刺激电流。
Once a stimulator step size has been selected, the stim Pbias and stim Nbias variables in Register 35 should be set to optimize the compliance range of the current drivers. The following settings should be used. 一旦选择了刺激器步长，应将寄存器 35 中的刺激 Pbias 和刺激 Nbias 变量设置为优化电流驱动器的兼容范围。应使用以下设置。
刺激器
步长
STIMULATOR
STEP SIZE
刺激器
全尺寸
范围
STIMULATOR
FULL SCALE
RANGE
STIM
PBIAS
STIM
NBIAS
10 nA
6
6
20 nA
7
7
50 nA
7
7
100 nA
7
7
200 nA
8
8
500 nA
9
9
10
10
11
11
14
14
15
15
Once a global stimulator step size has been configured, the positive and negative stimulation magnitudes can be set in Registers 64-79 and 96-111. Then, stimulation currents are easily turned on and off, and polarities selected, with the 32 bits in Registers 42 and 44. 一旦配置了全局刺激步长，就可以在寄存器 64-79 和 96-111 中设置正负刺激幅度。然后，通过寄存器 42 和 44 中的 32 位轻松打开和关闭刺激电流，并选择极性。
Note that all of these stimulation controls are in triggered registers, which means many of them can be updated using WRITE commands but their new contents are stored in internal buffers. The new values only take effect when an SPI command is issued with the flag set. At this time, all triggered registers on the chip update to their new values simultaneously. This mechanism allows complex stimulation patterns to be choreographed and executed with precision timing. 请注意，所有这些刺激控制都在触发寄存器中，这意味着许多可以使用写命令进行更新，但它们的新内容存储在内部缓冲区中。只有在发出带有 标志的 SPI 命令时，新值才会生效。此时，芯片上的所有触发寄存器都同时更新为它们的新值。这种机制允许精确定时地编排和执行复杂的刺激模式。
Note that there are no timers on the RHS2116 to control the duration of stimulation pulses. All timing is controlled explicitly through sequences of SPI commands. To generate a biphasic current pulse a stimulator must first be set to a negative polarity (for example) and turned on, then set to a positive polarity, and then turned off, each with separate SPI commands. The timing of the commands determines the duration of the stimulation pulses, so the host that is dispatching commands must observe a regimented timing structure. 请注意，RHS2116 上没有定时器来控制刺激脉冲的持续时间。所有的定时都是通过一系列 SPI 命令来明确控制的。要生成双相电流脉冲，刺激器必须首先设置为负极性（例如），然后打开，然后设置为正极性，然后关闭，每个步骤都需要使用单独的 SPI 命令。命令的时间确定了刺激脉冲的持续时间，因此发送命令的主机必须遵守一定的时间结构。
A typical biphasic current pulse is shown in the diagram below, along with a simplified series RC model of an electrode. The positive and negative currents can be of different magnitudes, but in this case the pulse durations are typically adjusted to maintain a constant area under the positive and negative curves, which corresponds to the total charge delivered. 下图显示了典型的双相电流脉冲，以及电极的简化串联 RC 模型。正负电流可以具有不同的大小，但在这种情况下，脉冲持续时间通常会调整以保持正负曲线下的面积恒定，这对应于传递的总电荷。
The resulting electrode voltage is shown in the lower half of the figure. The onset of a stimulation pulse causes a quick voltage drop across the electrode equal to IR. The capacitive component of the electrode then begins charging towards a negative voltage with a constant rate of . When the current stops, the drop goes away. The positive stimulation current pulse produces the same voltage changes in the opposite direction. 图的下半部分显示了产生的电极电压。刺激脉冲的开始导致电极上的电压迅速下降 ，等于 IR。然后，电极的电容性组分开始以恒定速率向负电压充电 。当电流停止时， 的降压消失。正刺激电流脉冲产生相反方向的相同电压变化。
If charge balance is maintained (and if the electrode behaves linearly) the electrode voltage should end where it started. The DC low-gain amplifiers on the RHS2116 may be employed to track this voltage following stimulation pulses. If a consistent positive or negative drift is observed, the trim settings in particular stimulation current drivers can be adjusted to compensate for inherent biases and maintain charge balance. 如果保持电荷平衡（并且电极表现线性），电极电压应该在原点结束。RHS2116 上的直流低增益放大器可以用来跟踪刺激脉冲后的电压。如果观察到一致的正向或负向漂移，可以调整特定刺激电流驱动器的修剪设置，以补偿固有偏差并保持电荷平衡。
Note that the plot of electrode voltage on the previous page is asymmetric with respect to voltage: because the stimulation started with a negative current pulse in this example, the electrode voltage excursion is primarily in the negative direction. That is, . In this case, voltage compliance problems or "water window" concerns will be skewed towards the negative voltage supply VSTIMor the negative end of the water window. 请注意，前一页电极电压的图是关于电压不对称的：因为在这个例子中，刺激是从负电流脉冲开始的，电极电压的变化主要是向负方向。也就是说， 。在这种情况下，电压合规问题或“水窗口”问题将偏向于负电压供应 VSTIM 或水窗口的负端。
To balance electrode voltages in the middle of the water window or voltage compliance range, the current-limited recovery circuit can be used to bias the resting potential of the electrode to small positive voltages (that stay within the water window) and make the electrode voltage excursions more symmetric with respect to ground. Alternatively, an asymmetric stimulation voltage supply may be used (e.g., VSTIM ; VSTIM- ). 为了在水窗口中间或电压允许范围内平衡电极电压，可以使用限流恢复电路来偏置电极的静息电位至小正电压（保持在水窗口内），使电极电压偏移相对于地面更对称。另外，也可以使用不对称的刺激电压供应（例如，VSTIM ；VSTIM- ）。
Compliance Monitor 合规监控器
Each stimulator has a built-in compliance monitor that sets a bit in Register 40 if the electrode voltage becomes so high or low (i.e., close to VSTIM+ or VSTIM-) that it becomes impossible to deliver the specified current. Register 40 is a read-only register containing compliance monitor bits from all 16 channels, but its value can be reset to zero by issuing an SPI command with the M flag asserted. Typically this register should be cleared prior to stimulation and checked periodically during or after stimulation to detect voltage compliance problems. 每个刺激器都有一个内置的合规性监视器，如果电极电压变得过高或过低（即接近 VSTIM+或 VSTIM-），导致无法传递指定电流，则在寄存器 40 中设置一个位。寄存器 40 是一个只读寄存器，包含来自所有 16 个通道的合规性监视器位，但可以通过发出带有 M 标志的 SPI 命令将其值重置为零。通常应在刺激之前清除此寄存器，并在刺激期间或之后定期检查，以检测电压合规性问题。
If a particular channel consistently exceeds the compliance limit, there are several potential remedies: 如果特定频道持续超过合规限制，有几种潜在的补救措施：
(1) Reduce the magnitude of the stimulation currents. 减小刺激电流的幅度。
(2) Reduce the duration of stimulation pulses. (2) 减少刺激脉冲的持续时间。
(3) Increase the stimulation voltage supplies. Although the total stimulation supply is limited to 14 V (e.g., (3) 增加刺激电压供应。尽管总刺激供应受限于 14 伏特（例如，
VSTIM , VSTIM ), it may be better to use asymmetric supplies (e.g., VSTIM , VSTIM- ) to accommodate particular stimulation protocols (e.g., negative currents first). VSTIM , VSTIM ), 最好使用不对称的供电（例如，VSTIM , VSTIM- ）以适应特定的刺激协议（例如，首先是负电流）。
(4) Use lower-impedance electrodes. (4) 使用阻抗较低的电极。
(5) Use the current-limited charge recovery circuits to set a resting potential within the water window but opposite the direction of the electrode voltage excursion during stimulation (see discussion in the previous section). 使用限流充电恢复电路来设定一个在水窗口内但与刺激过程中电极电压偏移方向相反的静息电位（请参见前一节中的讨论）。
Charge Recovery Switch 充电恢复开关
Most stimulation protocols use charge-balanced pulses to avoid oxidation-reduction reactions at the electrode-tissue interface. Variations in transistor characteristics across a chip make it impossible to achieve perfect charge balance, so recovery circuits are included to bleed off residual charge after stimulation pulses. Each stimulator/amplifier block includes a charge recovery switch which can be used to briefly connect an electrode to a common stim_GND pin, which is typically tied to ground. Register 46 controls these switches for all 16 channels. 大多数刺激协议使用平衡电荷脉冲，以避免电极-组织界面的氧化还原反应。芯片上晶体管特性的变化使得完美的电荷平衡不可能实现，因此在刺激脉冲后包括恢复电路以释放残余电荷。每个刺激器/放大器块包括一个电荷恢复开关，可用于短暂连接电极到一个通用的刺激_GND 引脚，通常与地线相连。寄存器 46 控制这些开关以用于所有 16 个通道。
The 'on' resistance of this switch is on the order of but varies with stimulation supply voltages. The following table lists the typical on resistance of the charge recovery switch as a function of the stimulation supply voltages VSTIM + and VSTIM- 该开关的“通态”电阻大约为 ，但随着刺激供电电压的变化而变化。以下表格列出了充电恢复开关的典型通态电阻，作为刺激供电电压 VSTIM +和 VSTIM-的函数。
An alternate charge recovery circuit is included in each stimulator/amplifier block. The current-limited (CL) charge recovery circuit, illustrated in the diagram below, pulls the electrode toward a user-specified voltage with a small, programmable current Imax ranging from 1 nA to (set in Register 37). The target recovery voltage Vrecov may be set in the range of with the charge recovery DAC variable in Register 36. The target recovery voltage and current limit are set globally for all channels. 每个刺激器/放大器块中都包含一个备用的充电恢复电路。下图所示的限流（CL）充电恢复电路使用一个小型可编程电流 Imax，范围从 1 nA 到 （在寄存器 37 中设置），将电极拉向用户指定的电压。目标恢复电压 Vrecov 可以在 范围内设置，充电恢复 DAC 变量在寄存器 36 中。目标恢复电压和电流限制是全局设置的，适用于所有通道。
The graph above shows the current driven by the currentlimited buffer as the electrode voltage Velec differs from the target recovery voltage Vrecov. For voltages differences greater than about , the buffer supplies a constant current Imax that weakly drives the electrode toward the target recovery voltage. 上图显示了由电流限制缓冲器驱动的电流，当电极电压 Velec 与目标恢复电压 Vrecov 不同时。对于大约 的电压差异，缓冲器提供一个恒定电流 Imax，弱驱动电极朝向目标恢复电压。
The table to the right lists settings for variables in Register 37 are used to configure the current limit Imax of the buffer. 右侧的表格列出了用于配置缓冲区的电流限制 Imax 的寄存器 37 中变量的设置。
For voltages differences smaller than , the buffer acts like a resistor with a resistance of approximately 75 mV / Imax. 对于小于 的电压差异，缓冲器的作用类似于具有约 75 mV / Imax 的电阻的电阻器。
Some stimulation protocols initially hold the electrode at a slightly positive potential when using biphasic pulses that begin with a cathodic (negative) current. This issue is discussed in greater depth at the end of the "ConstantCurrent Stimulator" section. 一些刺激协议最初在使用从阴极（负极）电流开始的双相脉冲时，会将电极保持在略微正电位。这个问题在“恒流刺激器”部分的末尾有更深入的讨论。
恢复
当前
限制
RECOVERY
CURRENT
LIMIT
等效
RESISTANCE FOR
小 V
EQUIVALENT
RESISTANCE FOR
SMALL V
sel1
sel2
sel3
1 nA
0
30
2
2 nA
0
15
1
5 nA
0
31
0
10 nA
50
15
0
20 nA
78
7
0
50 nA
22
3
0
100 nA
56
1
0
200 nA
71
0
0
500 nA
26
0
0
9
0
0
Supply Voltage Levels 供电电压级别
RHS2116 chips require a regulated voltage supply (VDD) between 3.2 V and 3.6 V for operation meeting all performance specifications. A nominal supply voltage of 3.3 V is recommended for most applications. All VDD pins should be kept at identical potentials. RHS2116 芯片需要在 3.2V 至 3.6V 之间的稳定电压供应（VDD）以满足所有性能规格的操作。大多数应用建议使用名义供电电压为 3.3V。所有 VDD 引脚应保持在相同的电位。
An additional bipolar power supply VSTIM is required for the constant-current stimulators on the chip. The VSTIM+ pins must be tied to a voltage within the range of +3.3 V to +10.7 V . The VSTIM- pins must be tied to a voltage within the range of -3.3 V to -10.7 V . It is not necessary to use symmetric supplies (i.e., |VSTIM-| does not have to equal VSTIM+), but the total stimulation voltage supply cannot exceed 14 V : (VSTIM+ - VSTIM-) . 芯片上的恒流刺激器需要额外的双极电源 VSTIM。 VSTIM+引脚必须连接到+3.3V 至+10.7V 范围内的电压。 VSTIM-引脚必须连接到-3.3V 至-10.7V 范围内的电压。 不需要使用对称电源（即|VSTIM-|不必等于 VSTIM+），但总刺激电压供应不能超过 14V：（VSTIM+ - VSTIM-）。
Important Addendum 重要附录
In May 2021, Intan identified a hardware degradation mode in the RHS2116 chip. When powering these chips from a supply (the previously recommended VSTIM voltages), the anodic (positive) current generator in each stimulator circuit begins to fail after many stimulation pulses, typically in the range of 30,000 to 1 million pulses. After degradation, the positive current output will be too low, often zero. This is a permanent hardware failure that cannot be reset by power-cycling the chip. 2021 年 5 月，Intan 在 RHS2116 芯片中确定了一种硬件退化模式。当从 供电（先前推荐的 VSTIM 电压）时，每个刺激器电路中的阳极（正）电流发生器在许多刺激脉冲后开始失效，通常在 30,000 至 1 百万脉冲范围内。退化后，正电流输出将过低，通常为零。这是一种无法通过重新上电来重置芯片的永久性硬件故障。
The cathodic (negative) current generators do not degrade 阴极（负）电流发生器不会降解
We have run extensive tests and determined that lowering the supply voltage to protects the chip against these failures. We have tested RHS2116 chips to more than 100 million stimulation cycles at these supply levels with no anodic current failures observed. 我们进行了大量测试，并确定将供电电压降低到 可以保护芯片免受这些故障的影响。我们已经在这些供电电压水平下对 RHS2116 芯片进行了超过 1 亿次刺激循环的测试，没有观察到阳极电流故障。
All customers using RHS2116 chips are advised to reduce power supplies to no more than a total of 14 V between VSTIM+ and VSTIM- to avoid long-term degradation of anodic current generators on the chip. 建议所有使用 RHS2116 芯片的客户将电源供应降低到 VSTIM+和 VSTIM-之间的总电压不超过 14V，以避免芯片上阳极电流发生器的长期降解。
All GND pins must be kept at the same potential, and the DC level of tissue connected to the amplifier inputs and reference should be kept at this same ground potential. 所有 GND 引脚必须保持在相同的电位，并且连接到放大器输入和参考的组织的直流电平应保持在相同的地面电位。
Power Supply Decoupling Capacitors 电源去耦电容
A ceramic power supply bypass capacitor should be connected between VDD and GND pins, and should be located less than 1 cm from the bottom side of the chip (near pins 13 and 22) on the printed circuit board. This capacitor should have an X5R or X7R dielectric, should be no smaller than a 0402 SMD device, and should be rated for at least 16 V . (While the capacitor will only be exposed to 3.3V, small SMD capacitors are known to dramatically decrease in capacitance as the voltage across the device approaches the maximum rated voltage. It is best to use a capacitor with a voltage rating several times higher than the expected voltage.) 应在印刷电路板上芯片底部（靠近引脚 13 和 22）距离小于 1 厘米的位置，连接一个 X5R 或 X7R 介质的陶瓷 电源旁路电容器，该电容器应连接在 VDD 和 GND 引脚之间。该电容器不应小于 0402 SMD 器件，并且额定电压至少为 16V。（尽管电容器只暴露在 3.3V 下，但众所周知，当器件跨越最大额定电压时，小型 SMD 电容器的电容会急剧减少。最好使用额定电压是预期电压数倍的电容器。）
If LVDS signaling is used, a single 100 nF capacitor near the bottom edge of the chip is sufficient to smooth the power supply for the RHS2116. If standard CMOS signaling is used, an additional 100 nF capacitor should be placed within 1 cm of the right side of the chip (near pins 24-28). 如果使用 LVDS 信号，芯片底部附近的单个 100 nF 电容器足以平滑 RHS2116 的电源供应。如果使用标准 CMOS 信号，则应在芯片右侧（24-28 号引脚附近）1 厘米内放置额外的 100 nF 电容器。
Ceramic power supply bypass capacitors should be connected between VSTIM+ and GND pins, and between VSTIM- and GND pins near the left side of the chip (near pins 4-8). These capacitors should have an X5R or X7R dielectric, should be no smaller than a 0402 SMD device, and should be rated for at least 25 V . 陶瓷 电源旁路电容器应连接在芯片左侧（4-8 号引脚附近）的 VSTIM+和 GND 引脚之间，以及 VSTIM-和 GND 引脚之间。这些电容器应具有 X5R 或 X7R 介质，尺寸不应小于 0402 SMD 器件，并且额定电压至少为 25V。
Analog-to-Digital Converter 模拟到数字转换器
The RHS2116 contains a 16-bit successive-approximation ADC with an integrated analog MUX, allowing it to sample voltage signals from the AC high-gain amplifiers and DC lowgain amplifiers connected to each electrode pin. When sampling the DC low-gain amplifiers, the ADC performs a 10-bit conversion. In most applications, the SPI master device will sample all 16 channels in round-robin fashion and then include perhaps four additional commands for sending commands related to stimulation or impedance measurement. In this case, the per-channel sampling rate will be 20 times lower than the total ADC sampling rate. (See the "SPI Command Sequences" section for details.) RHS2116 包含一个 16 位逐次逼近 ADC，带有集成的模拟 MUX，使其能够从连接到每个电极引脚的 AC 高增益放大器和 DC 低增益放大器中采样电压信号。在采样 DC 低增益放大器时，ADC 执行 10 位转换。在大多数应用中，SPI 主设备将以循环方式采样所有 16 个通道，然后可能包括四个额外的命令，用于发送与刺激或阻抗测量相关的命令。在这种情况下，每通道的采样率将比总 ADC 采样率低 20 倍。（有关详细信息，请参阅“SPI 命令序列”部分。）
ADC results are easily converted into electrode voltages using the following equations (assuming the twoscomp bit in Register 1 is set to zero and the ADC result is read as an unsigned integer). For the AC-coupled high-gain amplifiers, the electrode voltage is given by: ADC 结果可以使用以下方程式轻松转换为电极电压（假设寄存器 1 中的 twoscomp 位设置为零，并且 ADC 结果被读取为无符号整数）。对于交流耦合高增益放大器，电极电压由以下公式给出：
For the DC-coupled low-gain amplifiers, the electrode voltage is given by: 对于直流耦合低增益放大器，电极电压由以下公式给出：
Note the negative sign on the DC amplifier conversion. The least-significant bit (LSB) of the DC amplifier conversion is not reliable, and can be ignored (cleared to zero) for improved linearity. 注意 DC 放大器转换上的负号。DC 放大器转换的最低有效位（LSB）不可靠，可以忽略（清零）以提高线性度。
The ADC may be operated at speeds up to , which permits 16 channels to be sampled at more than each. (For typical neural recording applications, perchannel sampling rates of to are sufficient since the analog bandwidth of the amplifiers is usually set to 10 kHz or lower.) The variables ADC buffer bias and MUX bias in Register 0 should be set to the following values based on the total ADC sampling rate: ADC 可以以高达 的速度运行，这允许对 16 个通道进行超过 的采样。（对于典型的神经记录应用程序，每通道的采样率为 至 是足够的，因为放大器的模拟带宽通常设置为 10 kHz 或更低。）寄存器 0 中的变量 ADC 缓冲偏置和 MUX 偏置应根据总 ADC 采样率设置为以下值：
ADC 采样
费率
ADC sampling
rate
ADC 缓冲区
偏见
ADC buffer
bias
MUX bias MUX 偏置
32
40
16
40
8
40
8
32
8
26
4
18
3
16
3
5
The ADC contains a temperature- and supply-independent voltage reference that requires an off-chip 10 nF ceramic capacitor to be placed near the chip (within 1 cm of pin 23) and tied from ADC_ref to ground. This capacitor should have an X5R, X7R, C0G, or NP0 dielectric and should be rated for at least 16V. (See the "Supply Voltage Levels" section for an explanation of this requirement.) When the chip is powered up, a DC voltage of approximately 1.225 V should appear on this capacitor. ADC 包含一个温度和供电独立的电压参考，需要在芯片附近（距离引脚 23 不超过 1 厘米）放置一个 10 nF 的陶瓷电容，并将其从 ADC_ref 连接到地。这个电容应该具有 X5R、X7R、C0G 或 NP0 介质，并且额定电压至少为 16V。（有关此要求的解释，请参阅“供电电压级别”部分。）当芯片上电时，这个电容上应该出现约 1.225V 的直流电压。
If multiple RHS2116 chips are used, each chip must have its own 10 nF capacitor. The ADC_ref pins of different chips should not be connected. 如果使用多个 RHS2116 芯片，则每个芯片必须有自己的 10 nF 电容器。不应连接不同芯片的 ADC_ref 引脚。
Amplifier Input Protection 放大器输入保护
All CMOS integrated circuits are susceptible to damage by exposure to electrostatic discharge (ESD) from charged bodies. Electrostatic charges of greater than 1000 V can accumulate on the human body or test equipment and can discharge without detection. All RHS2116 chips incorporate protection circuitry to guard against mild ESD events. However, permanent damage may occur on devices subjected to high energy electrostatic discharges. It is important for users to understand the nature of the ESD protection circuitry used on the chip. 所有 CMOS 集成电路都容易受到来自带电体的静电放电（ESD）的损害。人体或测试设备上可能积累超过 1000 伏的静电电荷，并且可能在不被察觉的情况下放电。所有 RHS2116 芯片都集成了保护电路，以防范轻微的 ESD 事件。然而，设备可能会因高能量的静电放电而永久损坏。用户了解芯片上使用的 ESD 保护电路的性质是很重要的。
The figure above illustrates the on-chip passive elements (diodes and resistors) used for ESD protection at the input to each amplifier. Diodes are connected to VSTIM+ and VSTIM-, and are used to bleed off charge quickly to prevent the voltage on the series capacitors from exceeding damaging levels. Small series resistors create voltage drops in response to large transient ESD currents, further protecting the amplifiers. 上图显示了用于每个放大器输入处的芯片被动元件（二极管和电阻）用于静电放电保护。二极管连接到 VSTIM+和 VSTIM-，用于快速泄放电荷，以防止串联电容器上的电压超过破坏性水平。小 串联电阻对大型瞬态静电放电电流产生电压降，进一步保护放大器。
The DC level of all amplifier input pins should never rise above (VSTIM ++0.4 V ) or drop below (VSTIM- -0.4 V ). This prevents the ESD diodes from becoming significantly forward biased and passing current. As long as the electrode pin voltage stays between the stimulation power supplies, the resulting current will be less than 200 pA . 所有放大器输入引脚的直流电平不应升高到（VSTIM ++0.4 V）以上或降低到（VSTIM- -0.4 V）以下。这可以防止静电放电二极管显著正向偏置并通过电流。只要电极引脚电压保持在刺激电源之间，产生的电流将小于 200 pA。
The voltages on VSTIM+ and VSTIM- capacitively couple to amplifier inputs through the capacitance of the reversebiased ESD diodes, these power supplies should be kept free of noise. Otherwise, noise will be injected directly into the amplifier input (and the electrode). VSTIM+和 VSTIM-上的电压通过反向偏压 ESD 二极管的电容耦合到放大器输入，这些电源应该保持没有噪声。否则，噪声将直接注入放大器输入（和电极）。
Electrode Impedance Test 电极阻抗测试
All RHS2116 chips have built-in circuitry that provides selectable, direct access to any of the amplifier input pins for the purpose of measuring the impedance of electrodes connected to the chip. Additional on-chip circuitry is provided to generate an AC current waveform needed to measure electrode impedance. 所有 RHS2116 芯片都具有内置电路，可选择直接访问放大器输入引脚中的任何一个，以测量连接到芯片的电极的阻抗。还提供了额外的片上电路来生成测量电极阻抗所需的交流电流波形。
The figure on the next page shows a detailed schematic of the amplifier array input circuitry on the RHS2116. Transistor switches S0 through S15 can be closed to connect one selected amplifier to the on-chip current generator. If the register Zcheck en is set to zero, all switches remain open. This is the normal mode of operation for the chip. 下一页的图示显示了 RHS2116 上放大器阵列输入电路的详细原理图。晶体管开关 S0 至 S15 可以关闭，以连接一个选定的放大器到芯片上的电流发生器。如果寄存器 Zcheck en 设置为零，则所有开关保持打开。这是芯片的正常操作模式。
If Zcheck en is set to one, then the switch corresponding to the amplifier that is selected by the Zcheck select register is closed, and that amplifier's input is connected to the onchip current generator. This mode of operation should be used for measuring the impedance of individual electrodes. If an AC current waveform (with no DC current component) is generated on chip, then the resulting voltage waveform will pass through a high-gain amplifier and may be observed by the ADC. The impedance of the electrode may then be calculated as the ratio of peak voltage to peak current. 如果 Zcheck en 设置为 1，则与 Zcheck 选择寄存器选择的放大器对应的开关关闭，并且该放大器的输入连接到芯片上的电流发生器。应该使用这种操作模式来测量单个电极的阻抗。如果在芯片上产生交流电流波形（没有直流电流分量），则产生的电压波形将通过高增益放大器，并可以被 ADC 观察到。然后可以将电极的阻抗计算为峰值电压与峰值电流的比值。
Note that this technique requires small currents, as the RHS2116 amplifiers saturate for input voltages larger than . For example, a 5 nA peak current will elicit a 5 mV peak voltage with an electrode impedance of . 请注意，该技术需要小电流，因为 RHS2116 放大器在大于 的输入电压时会饱和。例如，当电极阻抗为 时，5 nA 的峰值电流将引发 5 mV 的峰值电压。
Note that any impedance measurement will include the input capacitance of the on-chip amplifiers and parasitic capacitance associated with the ESD protection diodes, stimulator circuitry, bond pad, and QFN package. This 10 pF of capacitance has an impedance magnitude of at 1 kHz , and should only affect impedance measurements for relatively high-impedance electrodes. 请注意，任何阻抗测量都将包括芯片放大器的输入电容和与 ESD 保护二极管、刺激器电路、焊盘和 QFN 封装相关的寄生电容。这 10 pF 的电容在 1 kHz 时的阻抗幅度为 ，应仅影响相对高阻抗电极的阻抗测量。
On-Chip AC Current Waveform Generator 芯片上的交流电流波形发生器
RHS2116 chips include circuitry for generating userspecified low-magnitude AC current waveforms that may be directed to any selected electrode for the purposes of electrode impedance testing. The waveform generator consists of an 8-bit digital-to-analog converter (DAC) followed by a two-pole 10 kHz low-pass filter to smooth the "stairstep" edges of the DAC waveform. The DAC is enabled by setting the Zcheck DAC power bit to one. The voltage produced by the DAC varies from a minimum of 0 V to a maximum of , and is set by the register Zcheck DAC. Incrementing this register by one increases the DAC output voltage by 4.785 mV . RHS2116 芯片包括用于生成用户指定的低幅值交流电流波形的电路，该波形可以定向到任选电极以进行电极阻抗测试。波形发生器由一个 8 位数模转换器（DAC）和一个两极 10 kHz 低通滤波器组成，用于平滑 DAC 波形的“阶梯”边缘。通过将 Zcheck DAC 电源位设置为 1 来启用 DAC。DAC 产生的电压从最小值 0 V 变化到最大值 ，并由寄存器 Zcheck DAC 设置。通过递增这个寄存器 1，DAC 输出电压增加 4.785 mV。
The resulting "test waveform" is connected to the selected electrode via a series capacitor that transforms the AC voltage into an AC current. The value of this capacitor is selectable by means of the Zcheck scale register and can have a value of , or 10 pF . 生成的“测试波形”通过一个串联电容器 连接到所选电极，将交流电压转换为交流电流。该电容器的值可通过 Zcheck 比例寄存器选择，并且可以为 或 10 pF。
If the DAC/filter produces a voltage waveform , the resulting current idaC injected to the electrode under test is given by 如果 DAC/滤波器产生电压波形 ，则注入到测试电极下的结果电流 idaC 由以下公式给出
If the DAC output is unchanging then IDAC , so the SPI master must regularly update the output DAC to create an voltage waveform in order to produce an AC current waveform through the series capacitor. For example, the DAC could be used to approximate a sine wave with an amplitude and a DC offset of (which is needed since the DAC output cannot go below zero), described as 如果 DAC 输出不变，则 IDAC ，因此 SPI 主机必须定期更新输出 DAC，以创建一个 电压波形，从而通过串联电容器产生交流电流波形。例如，DAC 可以用来近似一个振幅为 和直流偏移为 的正弦波（这是因为 DAC 输出不能低于零），描述为
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
The resulting current injected into the electrode under test will be a cosine wave with zero offset and amplitude given by: 注入到被测试电极的结果电流将是一个余弦波，其偏移为零，幅度由以下公式给出：
For example, if we regularly update the DAC to approximate a 1 kHz sine wave with the maximum possible amplitude of (and an offset of 0.6125 V ), then the following table shows the current amplitude produced by all possible series capacitor settings: 例如，如果我们定期更新 DAC 以近似 1 kHz 正弦波，其最大可能幅度为 （并且偏移为 0.6125 V），那么以下表格显示了所有可能串联电容器设置产生的电流幅度：
1 kHz 下的当前幅度
正弦波（最大振幅）
CURRENT AMPLITUDE WITH 1 kHz
SINE WAVE (MAX. AMPLITUDE)
0.1 pF 0.1 皮法
0.38 nA
1 pF 1 皮法
3.8 nA
10 pF 10 皮法德
38 nA
If we chose a series capacitor value of 1 pF and connected the 3.8 nA amplitude AC current waveform to a electrode, the resulting electrode voltage would have an amplitude of , which is within the range of the amplifiers. 如果我们选择了 1 pF 的串联电容值，并将 3.8 nA 幅值的交流电流波形连接到 电极，那么产生的电极电压幅值将为 ，这在放大器的 范围内。
If the frequency of the test waveform were reduced to 100 Hz then the test current would also drop by a factor of ten. However, switching from 1 pF to 10 pF would boost the current back to its original value. 如果测试波形的频率降低到 100 赫兹，那么测试电流也会减少十倍。然而，将电容从 1 皮法增加到 10 皮法会将电流提升回原始值。
By adjusting the series capacitor value and the amplitude of the waveform produced by the DAC, the AC test current amplitude can be adjusted to measure a wide range of electrode impedances at a number of different frequencies. 通过调整串联电容器值和 DAC 产生的波形幅度，可以调整交流测试电流幅度，以测量多种电极阻抗在多个不同频率下的范围。
Electrode Activation 电极激活
The stimulation circuitry may also be used to activate electrodes connected to an RHS2116 chip by applying sustained DC currents while electrodes are immersed in electroplating solution that is held at the ground potential with a low-impedance counter electrode. 刺激电路还可用于通过施加持续的直流电流来激活连接到 RHS2116 芯片的电极，同时电极浸入保持在地电位的电镀溶液中，该电镀溶液使用低阻抗对电极。
Some microelectrode electroplating procedures use 10 second current pulses between - 30 nA and -60 nA , but this can vary depending on electrode surface area, plating material, and many other factors. 一些微电极电镀程序使用-30 nA 和-60 nA 之间的 10 秒电流脉冲，但这取决于电极表面积、镀层材料和许多其他因素可能会有所变化。
Fault Current Detector 故障电流检测器
A global fault current detector is also included on the chip, connected between the stim_GND pin and the sense_GND pin. This circuit can be inserted into a common return current path (e.g., from the counter electrode to ground) and used to detect any unintended current that might result from erroneous SPI commands or partial chip failure. 芯片上还包括一个全球故障电流检测器，连接在 stim_GND 引脚和 sense_GND 引脚之间。该电路可以插入到一个公共回流电流路径中（例如，从计数电极到地面），用于检测可能由于错误的 SPI 命令或部分芯片故障而导致的任何意外电流。
As shown in the diagrams above, the fault current detector consists of a sense resistor and an amplifier that looks for significant positive or negative voltages across this resistor. The fault current detect bit in Register 50 goes high any time the current through the sense resistor exceeds a typical threshold of in either direction, though this detection threshold can vary between and from chip to chip. 如上图所示，故障电流检测器由一个 感应电阻和一个放大器组成，该放大器寻找跨越该电阻的显著正或负电压。寄存器 50 中的故障电流检测位在感应电阻中的电流超过典型阈值 时变高，尽管这种检测阈值在芯片之间可以在 和 之间变化。
To enable the fault current detector, the return current from a common counter electrode should be routed to ground through the sense resistor as shown in the left figure above. If the fault current detector will not be used, the counter electrode should be configured as shown in the right figure above, with both sides of the sense resistor shorted to the same potential (usually ground) 为了启用故障电流检测器，应将来自共同计数电极的回流电流通过感应电阻器路由到地面，如上图左侧所示。如果不打算使用故障电流检测器，则应将计数电极配置为上图右侧所示，感应电阻器的两侧短接到相同的电位（通常是地面）。
A typical use case of the fault current detector is to occasionally check the fault current detect bit when all stimulators are turned off. If current is detected, then various means can be taken to stop current flow, from reprogramming the SPI registers responsible for stimulation, to cutting power to the RHS2116 chip. 故障电流检测器的典型用例是在关闭所有刺激器时偶尔检查故障电流检测位。如果检测到电流，则可以采取各种手段来阻止电流流动，从重新编程负责刺激的 SPI 寄存器，到切断对 RHS2116 芯片的电源。
Auxiliary Digital Outputs 辅助数字输出
All RHS2116 chips have three user-programmable digital output pins (auxout1, auxout2, and auxoutOD) which may be used to control external devices via SPI commands. Register 1 contains control registers that configure the states of these signals. Setting digout1 HiZ to zero enables the auxout1 pin; if digout1 HiZ is set to one then the auxout1 pin assumes a high-impedance state. The digout1 register controls the value of the auxout1 pin. If digout1 is set to zero then auxout1 is driven to ground; if digout1 is set to one then auxout1 is driven to VDD. 所有 RHS2116 芯片都有三个用户可编程的数字输出引脚（auxout1、auxout2 和 auxoutOD），可以通过 SPI 命令控制外部设备。寄存器 1 包含配置这些信号状态的控制寄存器。将 digout1 HiZ 设置为零可以启用 auxout1 引脚；如果将 digout1 HiZ 设置为一，则 auxout1 引脚将处于高阻态。digout1 寄存器控制 auxout1 引脚的值。如果将 digout1 设置为零，则 auxout1 被拉低；如果将 digout1 设置为一，则 auxout1 被拉高到 VDD。
Similarly, the digout2 HiZ and digout2 variables control the auxout2 pin. A plot on the next page shows the maximum currents the auxout1 and auxout2 pins can supply while maintaining particular voltage levels. If additional drive current is needed, the user must add external circuitry. 类似地，digout2 HiZ 和 digout2 变量控制 auxout2 引脚。下一页的图表显示了 auxout1 和 auxout2 引脚在保持特定电压水平时可以提供的最大电流。如果需要额外的驱动电流，用户必须添加外部电路。
The digoutOD variable controls the open-drain auxoutOD pin. This pin is connected to the drain of an on-chip MOSFET switch whose source is tied to VSTIM-. Setting digoutOD to one pulls the auxoutOD pin to the negative stimulation voltage. If digoutOD is set to zero, the auxoutOD pin assumes a high-impedance state. The voltage on the auxoutOD pin can range between VSTIM+ and VSTIM-, so this pin may be used to control devices that require voltages larger than 3.3V (e.g., blue or white LEDs). Any load connected to auxoutOD must be tied to a voltage above VSTIM-, like VSTIM+ or GND, that will pull this pin to a higher voltage when it is placed in a high impedance state. digoutOD 变量控制开漏 auxoutOD 引脚。该引脚连接到芯片上的 MOSFET 开关的漏极，其源极连接到 VSTIM-。将 digoutOD 设置为 1 会将 auxoutOD 引脚拉到负刺激电压。如果将 digoutOD 设置为零，则 auxoutOD 引脚会处于高阻态。auxoutOD 引脚上的电压可以在 VSTIM+和 VSTIM-之间变化，因此该引脚可用于控制需要大于 3.3V 电压的设备（例如蓝色或白色 LED）。连接到 auxoutOD 的任何负载必须连接到高于 VSTIM-的电压，如 VSTIM+或 GND，这样当将该引脚置于高阻态时，它会被拉到更高的电压。
The auxoutOD pin can sink a typical maximum output current of 25 mA (see plot above). For pin voltages greater than 3 V above VSTIM- this pin behaves as a current source. For pin voltages less than 2 V above VSTIM- the on-chip MOSFET behaves like a resistor with a typical 'on' resistance of . If precise current levels are needed, a current-limiting resistor should be added in series with the load connected to this pin. auxoutOD 引脚可以吸收典型的最大输出电流为 25 毫安（见上图）。对于大于 VSTIM-以上 3V 的引脚电压，此引脚将表现为电流源。对于小于 VSTIM-以上 2V 的引脚电压，芯片上的 MOSFET 将表现为典型的“通”电阻，为 。如果需要精确的电流水平，则应在连接到此引脚的负载上串联添加限流电阻。
The auxiliary digital output pins can be used for many applications: to control the gate of an external MOSFET that optionally shorts ref_elec to ground or enable an LED or laser diode for optogenetic stimulation. It is important to remember that the values of these registers are indeterminate when the chip is first turned on, so care should be taken to ensure that any device connected to this pin does not cause trouble if an auxiliary digital output pin assumes an unexpected value when the chip is initially powered up. 辅助数字输出引脚可用于许多应用：用于控制外部 MOSFET 的门，该 MOSFET 可以选择将 ref_elec 短接到地或启用 LED 或激光二极管进行光遗传学刺激。重要的是要记住，当芯片首次开启时，这些寄存器的值是不确定的，因此应注意确保连接到此引脚的任何设备在芯片初始上电时，如果辅助数字输出引脚假定意外值，不会造成问题。
Absolute Value Mode 绝对值模式
If the absmode bit in Register 1 is set to one, the output results from all AC high-gain amplifier channels are passed through an absolute value function: all negative results are sign inverted so that the output of each channel is a strictly positive "full wave rectified" waveform. This destroys some information in the waveform (e.g., both -100 and +100 are reported as +100 ), but this function may be useful if only the amplitude or "energy" of a signal is required for a particular application. 如果寄存器 1 中的 absmode 位设置为 1，则所有 AC 高增益放大器通道的输出结果将通过绝对值函数传递：所有负结果都会被符号反转，以便每个通道的输出都是严格正的“全波整流”波形。这会破坏波形中的一些信息（例如，-100 和+100 都报告为+100），但如果只需要信号的幅度或“能量”用于特定应用，则此功能可能很有用。
For example, in a system that detects and counts neural spikes using a simple threshold algorithm, enabling absolute value mode allows the controller to check only one threshold instead of checking both a positive and negative threshold. Also, many EMG-based prosthetic limb controllers estimate the energy or envelope of the EMG signal, and computing the absolute value of the raw EMG waveform is often the first step in this estimation. The ability of the RHS2116 to perform this operation automatically can relieve some of the computational burden on the controller in an electrophysiology acquisition system. 例如，在一个使用简单阈值算法检测和计数神经突触的系统中，启用绝对值模式可以使控制器只检查一个阈值，而不是同时检查正阈值和负阈值。此外，许多基于 EMG 的假肢控制器估计 EMG 信号的能量或包络，并且计算原始 EMG 波形的绝对值通常是此估计的第一步。RHS2116 执行此操作的能力可以自动减轻电生理采集系统中控制器的一些计算负担。
It is recommended that absolute value mode be used with the DSP high-pass filter enabled so that the amplifier offsets are removed and the baseline level of each channel will be precisely zero. 建议使用绝对值模式，并启用 DSP 高通滤波器，以便消除放大器的偏移，并确保每个通道的基线水平精确为零。
ADC results from the DC low-gain amplifiers are not affected by the absmode bit. ADC 结果不受 absmode 位影响。
DSP High-Pass Filter for Offset Removal DSP 高通滤波器用于去除偏移
RHS2116 chips include a custom digital module that performs digital signal processing (DSP) to implement single-pole high-pass filters on each sampled amplifier channel. This feature can be used to remove the residual DC offset voltages associated with the AC high-gain amplifiers, which can range from (referred to the electrode). (Despite the series capacitors that block DC voltages at the amplifier input, small DC offsets are introduced in the amplifier circuitry after the capacitors.) The DSP module can also be used to add an additional pole of high-pass filtering to the single pole inherent in the amplifier circuits. The chip uses an IIR filter architecture; the RHS2116 芯片包括一个定制的数字模块，执行数字信号处理（DSP）以在每个采样放大器通道上实现单极高通滤波器。此功能可用于消除与 AC 高增益放大器相关的剩余直流偏移电压，其范围可以从 （指电极）开始。（尽管串联电容器阻止放大器输入处的直流电压，但在电容器之后的放大器电路中引入了小的直流偏移。）DSP 模块还可用于在放大器电路中固有的单极中添加一个额外的高通滤波器极点。该芯片使用 IIR 滤波器架构；
magnitude and phase characteristics of this filter are similar to those of an analog high-pass filter implemented with a capacitor and resistor. 该滤波器的幅度和相位特性类似于使用电容器和电阻器实现的模拟高通滤波器。
The DSP high-pass filter module is enabled by setting the DSPen bit in Register 1 to one. The DSP module affects only affects AC high-gain amplifier channels; DC low-gain amplifiers are not filtered. DSP 高通滤波器模块通过将寄存器 1 中的 DSPen 位设置为 1 来启用。DSP 模块仅影响交流高增益放大器通道；直流低增益放大器不受滤波。
The cutoff frequency of the DSP high-pass filter is determined by two factors: the rate at which each amplifier channel is sampled ( ), and the four-bit DSP cutoff freq variable in Register 4. The cutoff frequency is calculated using the following equation: DSP 高通滤波器的截止频率由两个因素决定：每个放大器通道采样的速率（ ）和寄存器 4 中的四位 DSP 截止频率变量。截止频率 使用以下方程计算：
where is the value of the DSP cutoff freq variable, ranging from 1 to 15 . Calculated values of are presented in the table below for convenience: 其中 是 DSP 截止频率变量的值，范围从 1 到 15。方便起见，计算出的 值如下表所示：
DSP 截止
频率 [3:0]
DSP cutoff
freq [3:0]
0
differentiator; see below 差异化器;见下文
1
0.1103
2
0.04579
3
0.02125
4
0.01027
5
0.005053
6
0.002506
7
0.001248
8
0.0006229
9
0.0003112
10
0.0001555
11
0.00007773
13
0.00003886
14
0.00001943
15
0.000009714
Note that is the sampling frequency of each channel; not the overall ADC sampling frequency. 请注意， 是每个通道的采样频率；而不是整体 ADC 采样频率。
For example, if we sample each amplifier channel at 30 kSamples/s and set the DSP cutoff freq variable to 12 , the resulting DSP high-pass cutoff frequency will be , which is a good value for removing offsets while preserving low frequency biological signals such as cortical local field potentials (LFPs). Alternatively, if we sample at and set the DSP cutoff freq variable to 4 , the resulting DSP highpass cutoff frequency will be 308 Hz , which is a good value for removing LFP fluctuations so that neural action potentials can be subjected to amplitude thresholds. 例如，如果我们以 30 kSamples/s 对每个放大器通道进行采样，并将 DSP 截止频率变量设置为 12，则得到的 DSP 高通截止频率将为 ，这是一个很好的值，可以去除偏移同时保留低频生物信号，如皮层局部场电位（LFPs）。另外，如果我们以 进行采样，并将 DSP 截止频率变量设置为 4，则得到的 DSP 高通截止频率将为 308 Hz，这是一个很好的值，可以去除 LFP 波动，以便神经动作电位可以受到幅度阈值的影响。
If the DSP cutoff freq variable is set to zero, the DSP filter acts like a perfect differentiator; the output of the filter is the current ADC result minus the previous ADC result for a particular channel. 如果 DSP 截止频率变量设置为零，则 DSP 滤波器的作用类似于完美的微分器；滤波器的输出是特定通道的当前 ADC 结果减去先前 ADC 结果。
Since the DSP filter has perfect linearity while the analog amplifier circuits have imperfect linearity, it is good practice to set the DSP cutoff frequency higher than the analog amplifier lower cutoff frequency fL to minimize the distortion of large signals. 由于 DSP 滤波器具有完美的线性性，而模拟放大器电路具有不完美的线性性，因此最佳做法是将 DSP 截止频率 设置得比模拟放大器的截止频率 fL 更高，以最小化大信号的失真。
If a large signal is applied to an AC high-gain amplifier channel with the DSP filter enabled, the sampled output will "hard limit" at the numerical minimum or maximum permitted by the 16 bit representation; it will not "roll over" due to numerical overflow or underflow. 如果对带有 DSP 滤波器的交流高增益放大器通道施加大信号，则采样输出将在 16 位表示允许的数字最小值或最大值处“硬限制”；它不会因数字溢出或下溢而“翻转”。
When using the DSP filter module, it is important to sample amplifiers at a steady and consistent rate. The filter state variables for each channel are updated only when that particular channel is sampled. If each channel is not sampled at exactly the same rate during the time the DSP filter is enabled, the filter output will not be accurate. 在使用 DSP 滤波器模块时，重要的是以稳定和一致的速率对放大器进行采样。每个通道的滤波器状态变量仅在采样该特定通道时更新。如果在启用 DSP 滤波器时，每个通道在同一时间内的采样速率不完全相同，则滤波器输出将不准确。
The time constant associated with the DSP high-pass filter is given by . If a step input is applied to the filter, the output will exponentially decay back to zero with this time constant. If a relatively low value of is used (e.g., less than 1 Hz ), the time constant can become quite long and result in long recovery times from large transient signals. Each channel's DSP high-pass filter can be instantly reset to zero by setting the H flag of the CONVERT command to one. This operation clears the digital state variable associated with the selected amplifier channel. 与 DSP 高通滤波器相关的时间常数由 给出。如果将阶跃输入应用于滤波器，则输出将以这个时间常数指数衰减回零。如果使用相对较低的 值（例如，小于 1 Hz），时间常数可能会变得非常长，并导致从大幅瞬态信号中的长恢复时间。每个通道的 DSP 高通滤波器可以通过将 CONVERT 命令的 H 标志设置为 1 来立即重置为零。此操作会清除与所选放大器通道相关的数字状态变量。
Power Dissipation 功耗
The total power dissipation of an RHS2116 chip depends on how it is configured and operated. This section provides a breakdown of currents pulled from the three power supplies (VDD, VSTIM+, and VSTIM-) under various modes of operation. Power dissipation can then be calculated as the absolute value of the product of the supply current and the supply voltage. RHS2116 芯片的总功耗取决于其配置和操作方式。本节提供了在各种操作模式下从三个电源（VDD、VSTIM+和 VSTIM-）中提取的电流的分解。然后可以将功耗计算为供电电流和供电电压的乘积的绝对值。
The most important consideration in reducing power in the RHS2116 is setting the DC amp power variable in Register 38 to all ones (hex FFFF). While this register was originally included on the chip to provide a modest power savings in cases where the DC amplifiers were not used, a hardware bug in the chip counterintuitively causes current drawn from VDD to increase when these amplifiers are 在减少 RHS2116 功耗方面最重要的考虑是将寄存器 38 中的直流安培功率变量设置为全 1（十六进制 FFFF）。虽然该寄存器最初是在芯片上包含的，以在不使用直流放大器的情况下提供适度的功耗节约，但芯片中的硬件错误导致从 VDD 拉取的电流在这些放大器被使用时增加。
powered down. For each DC amplifier channel that is powered down, the current from VDD increases by 1.93 mA . It is therefore strongly recommended that Register 38 be set to all ones as soon as the chip is powered up. 关闭电源。对于每个关闭电源的 DC 放大器通道，来自 VDD 的电流增加 1.93 毫安。因此强烈建议在芯片上电后立即将寄存器 38 设置为全 1。
Once this register is set, currents drawn from the VSTIM supplies are relatively constant if stimulation pulses are not being generated. The table below lists quiescent currents for various supply levels. 一旦设置了此寄存器，如果不生成刺激脉冲，则从 VSTIM 供应中提取的电流相对恒定。下表列出了各种供应电平的静态电流。
VSTIM
供应电流
来自 VSTIM +
supply current
from VSTIM +
供应电流
来自 VSTIM-
supply current
from VSTIM-
0.57 mA 0.57 毫安
0.41 mA 0.41 毫安
0.61 mA 0.61 毫安
0.46 mA 0.46 毫安
0.62 mA 0.62 毫安
0.48 mA 0.48 毫安
0.57 mA 0.57 毫安
0.51 mA 0.51 毫安
0.64 mA 0.64 毫安
0.41 mA 0.41 毫安
Currents drawn from the VSTIM supplies may increase significantly during stimulation, as discussed below. 从 VSTIM 供应中提取的电流在刺激过程中可能会显著增加，如下所讨论。
The bulk of non-stimulation current is drawn from the +3.3 V) power supply (VDD). Following is a list of guidelines for estimating total VDD supply current under various operating conditions. 非激励电流的大部分来自+3.3 V）电源（VDD）。以下是在各种工作条件下估计总 VDD 供电电流的准则列表。
Baseline current: Each RHS2116 pulls 3.2 mA of quiescent current from VDD to power various voltage references, bias current generators, and ADC circuitry. 基准电流：每个 RHS2116 从 VDD 提取 3.2 毫安的静态电流，以为各种电压参考、偏置电流发生器和 ADC 电路供电。
AC amplifiers: Each AC amplifier consumes current in proportion to its upper cutoff frequency, approximately per amplifier. Powering off an amplifier via Register 8 essentially sets its upper cutoff frequency to zero for power calculation purposes. AC 放大器：每个 AC 放大器消耗的电流与其上截止频率成比例，每个放大器约为 。通过寄存器 8 关闭放大器实质上将其上截止频率设置为零，用于功率计算目的。
ADC and MUX dynamic current: The ADC/MUX assembly consumes additional current in proportion to the total sampling rate, approximately . Enabling or disabling 10-bit sampling of the DC amplifiers (via the D flag in the CONVERT command) does not significantly affect power consumption. ADC 和 MUX 动态电流：ADC/MUX 组件的额外电流消耗与总采样率成比例，大约 。通过 CONVERT 命令中的 D 标志启用或禁用 DC 放大器的 10 位采样不会显著影响功耗。
LVDS I/O: If LVDS_en is pulled high to enable on-chip LVDS driver and receivers, the chip pulls an additional 5.7 mA . Current draw with standard CMOS signaling is proportional to SPI data rate and MISO wire capacitance; for low data rates and short wires, it is very small. LVDS I/O：如果将 LVDS_en 拉高以启用芯片上的 LVDS 驱动器和接收器，则芯片会额外拉高 5.7 mA。使用标准 CMOS 信号传输时的电流消耗与 SPI 数据速率和 MISO 线电容成正比；对于低数据速率和短线，电流消耗非常小。
Impedance measurement module: With Zcheck DAC power in Register 2 set to one, the DAC used for impedance testing consumes . 阻抗测量模块：将寄存器 2 中的 Zcheck DAC 电源设置为 1 后，用于阻抗测试的 DAC 消耗 。
Using these guidelines, we can now estimate whole-chip power dissipation, not including additional current required for stimulation pulses: 使用这些准则，我们现在可以估计整个芯片的功耗，不包括刺激脉冲所需的额外电流：
Example: Wideband neural recording headstage
VSTIM
sample rate channel
Baseline current: 3.2 mA
AC amplifiers:
ADC/MUX:
LVDS I/O: 5.7 mA
Impedance measurement: 0.12 mA
Total supply current from VDD: 12.99 mA
Total supply current from VSTIM+: 0.65 mA
Total supply current from VSTIM-: 0.51 mA
Total power dissipation: 示例：宽带神经记录头戴式设备
VSTIM
采样率 通道
基线电流：3.2 毫安
AC 放大器:
ADC/MUX:
LVDS I/O: 5.7 mA
阻抗测量：0.12 毫安
总供电电流来自 VDD：12.99 毫安
总供应电流来自 VSTIM +：0.65 毫安
总供应电流来自 VSTIM-：0.51 毫安
总功耗：
Example: ECoG recording front-end with CMOS I/O
VSTIM
sample rate channel
Baseline current: 3.2 mA
AC amplifiers:
ADC/MUX:
Impedance measurement: 0.12 mA
Total supply current from VDD: 3.64 mA
Total supply current from VSTIM+: 0.61 mA
Total supply current from VSTIM-: 0.46 mA
Total power dissipation: (3.64 mA 示例：带有 CMOS I/O 的 ECoG 记录前端
VSTIM
采样率 通道
基线电流：3.2 毫安
AC 放大器:
ADC/MUX:
阻抗测量：0.12 毫安
总供电电流来自 VDD：3.64 毫安
VSTIM+的总供应电流：0.61 毫安
总供应电流来自 VSTIM-：0.46 毫安
总功耗：(3.64 毫安
Power Due to Stimulation 由于刺激而产生的力量
Generating stimulation pulses draws additional current from all three power supplies. If a positive stimulation current with magnitude is supplied from one channel, the currents drawn from each power supply increase by the following amounts during stimulation: 生成刺激脉冲会从所有三个电源中吸取额外电流。如果从一个通道提供幅度为 的正刺激电流，则在刺激过程中，从每个电源吸取的电流将增加以下数量：
VDD:
VSTIM+:
VSTIM-:
supplied from one channel, the currents drawn from each power supply increase by the following amounts during stimulation: 从一个通道提供的电流，在刺激过程中，每个电源提供的电流增加如下：
VDD:
VSTIM+:
VSTIM-:
Note: If any of the auxiliary digital output pins (auxout1, auxout2, or auxoutOD) are used with low-impedance loads, these may draw additional supply current as well. See the "Auxiliary Digital Outputs" section for more details. 注意：如果任何辅助数字输出引脚（auxout1、auxout2 或 auxoutOD）与低阻抗负载一起使用，这些可能会额外吸取供电电流。有关更多详细信息，请参阅“辅助数字输出”部分。
Minimizing Power Consumption 最小化功耗
While the criteria listed above are the major factors determining power consumption in the RHS2116, several other chip settings can help to minimize current drawn from the VDD supply: 尽管上述列出的标准是决定 RHS2116 功耗的主要因素，但其他几个芯片设置可以帮助最小化从 VDD 供应中抽取的电流：
Set the stimulation current magnitudes of all unused channels to zero (Registers 64-79 and 96-111). 将所有未使用通道的刺激电流幅度设置为零（寄存器 64-79 和 96-111）。
If current-limited charge recovery is not used, set the charge recovery current limit to 1 nA (Register 37). 如果不使用限流充电恢复功能，请将充电恢复电流限制设置为 1 nA（寄存器 37）。
If stimulation is not used, set the stimulation current step size to 10 nA (Register 34). 如果不使用刺激，请将刺激电流步长设置为 10 nA（寄存器 34）。
If the second AC amplifier lower cutoff frequency is not used, set it to 0.10 Hz (Register 7). 如果不使用第二个 AC 放大器的下截止频率，请将其设置为 0.10 Hz（寄存器 7）。
Power down unused AC amplifiers (Register 8), but make sure to leave all DC amplifiers powered up (Register 38; see above for explanation). 关闭未使用的交流放大器（寄存器 8），但请确保所有直流放大器保持通电（寄存器 38；请参见上文解释）。
Excessive Power Consumption Warning 过度耗电警告
Leaving VSTIM+ and VSTIM- unconnected will cause excessive power dissipation. These power pins should always be connected to voltage supplies during operation of the chip. If stimulation functions will not be used, VSTIM+ can be tied to VDD and VSTIM- can be tied to ground. 将 VSTIM+和 VSTIM-保持未连接会导致过多的功耗。在芯片运行期间，这些电源引脚应始终连接到电压供应。如果不打算使用刺激功能，VSTIM+可以连接到 VDD，VSTIM-可以连接到地。
SPI Command Sequences SPI 命令序列
The rate and timing of SPI commands sent to the chip determines the ADC sampling rate; sample times are set by the falling edge of . In most applications, all 16 amplifiers on the chips will be sampled in round-robin fashion. This can be accomplished by repeating the following command sequence: SPI 命令发送到芯片的速率和时间确定 ADC 采样率；样本时间由 的下降沿设置。在大多数应用中，芯片上的所有 16 个放大器将以循环方式进行采样。这可以通过重复以下命令序列来实现：
If a per-channel sampling rate of is desired, then SPI commands are sent at a rate of . 如果需要每通道采样率为 ，则 SPI 命令以 的速率发送。
The problem with simply repeating 16 CONVERT commands is that additional commands (e.g., to write to registers to control stimulation) must be substituted for regular CONVERT commands (which results in a missing sample on one channel) or else the sequence must be interrupted by an inserted command, which makes the perchannel sampling rate irregular. 简单重复 16 个 CONVERT 命令的问题在于必须替换常规的 CONVERT 命令以进行额外的命令（例如，写入寄存器以控制刺激），否则序列必须被插入命令中断，这会导致每通道采样率不规则。
The simplest solution to this problem is to always insert a fixed number (typically 1-4) of extra "auxiliary" commands into the round-robin command sequence: 解决这个问题的最简单方法是始终在轮询命令序列中插入固定数量（通常为 1-4）的额外“辅助”命令
CONVERT(0) 转换(0)
CONVERT(1) 转换(1)
CONVERT(2) 转换(2)
...
CONVERT(14) 转换(14)
auxiliary command 1 辅助命令 1
auxiliary command 2 辅助命令 2
auxiliary command 3 辅助命令 3
auxiliary command 4 辅助命令 4
Now having a list of 20 commands, the SPI commands are sent at a rate of to achieve a per-channel sampling rate of R. Extra commands (e.g., to control stimulation, to update the impedance check DAC, etc.) may be inserted into one of the auxiliary command "slots", and these extra commands will not interrupt the steady, constant-rate sampling of the amplifiers on the chip. Dummy commands (e.g., reading a ROM register) can be inserted into these slots as place holders when no auxiliary actions are required. 现在有一个包含 20 个命令的列表，SPI 命令以 的速率发送，以实现每通道采样率为 R。额外的命令（例如，用于控制刺激，更新阻抗检查 DAC 等）可以插入到辅助命令“槽”中的一个，并且这些额外的命令不会中断芯片上放大器的稳定、恒定速率采样。当不需要辅助操作时，可以在这些槽中插入虚拟命令（例如，读取 ROM 寄存器）作为占位符。
See the "Example Chip Initialization Procedure" section near the end of this datasheet for an example SPI command sequence to initialize the chip. 请查看本数据表末尾附近的“示例芯片初始化过程”部分，了解初始化芯片的示例 SPI 命令序列。
Circuit Board Design 电路板设计
Careful printed circuit board (PCB) design is critical for achieving the specified performance of the RHS2116. The chip is designed to work with a single ground and a single VDD, plus positive and negative stimulation voltage supplies. It is not necessary (or recommended) to use separate "analog" and "digital" power lines. Rather, it is important to use a good ground plane and power plane underneath the chip. This requires the use of a four-layer PCB, at minimum. If a four-layer board is used, the top (first) and bottom (fourth) layers should be used for signal routing. The second layer should be a ground plane and the third layer should be a VDD plane. 小心的印刷电路板（PCB）设计对于实现 RHS2116 的指定性能至关重要。该芯片设计为与单一地线和单一 VDD 一起工作，再加上正负刺激电压供应。不需要（或建议）使用单独的“模拟”和“数字”电源线。相反，重要的是在芯片下方使用良好的地面层和电源层。这需要至少使用四层 PCB。如果使用四层板，顶层（第一层）和底层（第四层）应用于信号路由。第二层应为地面层，第三层应为 VDD 层。
A ceramic capacitor between VDD and ground should be placed as close as possible to the bottom of the chip (near pins 13 and 22). Additional 100 nF capacitors should be tied from VSTIM+ to ground and from VSTIM- to ground; these capacitors should be placed close to the left side of the chip (near pins ). See the "Supply Voltage Levels" section for guidance selecting the proper types of capacitors. If standard CMOS signaling will be used, place an additional 100 nF decoupling capacitor near pins 24-28 on the right side of the chip. 应尽可能靠近芯片底部（靠近引脚 13 和 22）放置一个 陶瓷电容器，连接 VDD 和地。应该从 VSTIM+到地和从 VSTIM-到地连接额外的 100 nF 电容器；这些电容器应该靠近芯片的左侧（靠近引脚 ）。查看“供电电压级别”部分，以选择适当类型的电容器。如果将使用标准 CMOS 信号传输，请在芯片右侧的引脚 24-28 附近放置额外的 100 nF 去耦电容器。
A 10 nF ceramic capacitor should be tied from ADC_ref to ground and placed close to the bottom or right side of the 应该从 ADC_ref 连接到地面，并放置在底部或右侧的地方
chip, near the ADC_ref pin. See the "Analog-to-Digital Converter" section above for guidance selecting the proper type of capacitor. 芯片，靠近 ADC_ref 引脚。请参阅上面的“模数转换器”部分，以选择适当类型的电容。
If LVDS signaling is used, termination resistors for , SCLK, and MOSI should be placed within 20 cm of the chip. The termination resistor for MISO should be placed near the controller and will likely not reside on the same board as the RHS2116. (Many LVDS receivers and FPGAs have built-in termination resistors, so this device may not be necessary.) 如果使用 LVDS 信号，应在芯片附近 20 厘米内放置 ，SCLK 和 MOSI 的 终端电阻。MISO 的 终端电阻应放置在控制器附近，可能不会与 RHS2116 位于同一板上。（许多 LVDS 接收器和 FPGA 都内置了终端电阻，因此可能不需要此设备。）
A recommended PCB footprint for QFN-packaged RHS2116 chips is shown on page 45. The center pad of the QFN package is connected to the VSTIM- power supply, so the center pad on the circuit board should be tied to the negative stimulation power supply. If a solder paste mask is used for reflow assembly, the paste mask for the center pad should be made smaller than the pad so excess solder is not deposited. When the QFN component is placed on the PCB, excess solder paste from the center pad can short to peripheral pins. QFN 封装的 RHS2116 芯片的推荐 PCB 焊盘尺寸显示在第 45 页。QFN 封装的中心焊盘连接到 VSTIM-电源，因此电路板上的中心焊盘应该连接到负刺激电源。如果使用焊膏遮罩进行回流组装，则中心焊盘的焊膏遮罩应该比焊盘小，以防止过多的焊料沉积。当 QFN 元件放置在 PCB 上时，中心焊盘的过多焊膏可能会短接到外围引脚。
Leakage Currents Due to Residual Solder Flux 由残留焊膏引起的泄漏电流
Solder contains flux, a chemical compound that helps to clean surfaces and facilitate solder flow and proper bonding. While flux is useful for the soldering process, residual flux left behind on the surface of the circuit board can be slightly conductive. Conductive paths between electrodes and power supply lines can cause leakage currents that may polarize electrodes and lead to oxidation or, in extreme cases, electrolysis of water near the electrodes. 焊料含有助焊剂，这是一种化学化合物，有助于清洁表面，促进焊料流动和正确的结合。虽然助焊剂对焊接过程很有用，但残留在电路板表面上的助焊剂可能具有轻微的导电性。电极和电源线之间的导电路径可能导致泄漏电流，这可能使电极极化并导致氧化，或在极端情况下，在电极附近发生水电解。
If leakage currents are a concern, solder paste should be omitted on the center pad of the QFN. This is not a critical electrical connection, and since this pad is at the VSTIMpotential and very close to the electrode pads, it is an obvious concern due to residual solder flux that ends up underneath the QFN and cannot be cleaned effectively. Additionally, solder with water soluble flux should be used, and after assembly the boards should be thoroughly washed in warm deionized (DI) water. These are standard services that most circuit board assembly companies can provide on request. 如果泄漏电流是一个问题，应该在 QFN 的中心焊盘上省略焊膏。这不是一个关键的电气连接，由于这个焊盘处于 VSTIM 电位并且非常靠近电极焊盘，由于残留的焊剂会进入 QFN 底部并且不能有效清洁，这是一个明显的问题。此外，应该使用含水溶性焊剂的焊料，并且在组装后，电路板应该在温暖的去离子水中彻底清洗。这些是大多数电路板组装公司可以根据要求提供的标准服务。
Digital Signaling Modes 数字信令模式
The RHS2116 chip communicates over a standard digital Serial Peripheral Interface (SPI) bus. The bus protocol and data structures used are described in later sections. The voltage levels used to send digital signals over this bus can assume one of two forms: standard CMOS signaling or lowvoltage differential signaling (LVDS). The above figure illustrates the differences between a digital value (e.g., MISO) transmitted using these two signaling methods. RHS2116 芯片通过标准数字串行外围接口（SPI）总线进行通信。所使用的总线协议和数据结构在后面的部分中描述。用于在总线上传输数字信号的电压电平可以采用标准 CMOS 信号或低压差分信号（LVDS）中的一种形式。上图说明了使用这两种信号方法传输的数字值（例如 MISO）之间的差异。
Standard CMOS Signaling 标准 CMOS 信号传输
Standard CMOS signaling (upper left) transmits a digital one or zero by switching the voltage on a single output wire between ground and VDD. The current drawn from the power supply (lower left) is nearly zero until the output switches state; at this point, a burst of current is pulled from the power supply to charge or discharge the capacitance of the output wire. These bursts of supply current introduce high frequency noise to the on-chip power supply; this noise can adversely affect noise levels. For typical data streams containing similar numbers of ones and zeros, the dynamic power dissipation of a standard CMOS output driving a wire with capacitance at R bits/s is 标准 CMOS 信号传输（左上）通过在单个输出线上的电压在地线和 VDD 之间切换来传输数字 1 或 0。从电源（左下）吸取的电流几乎为零，直到输出切换状态；在这一点上，从电源中拉出一阵电流来充电或放电输出线的电容。这些电源电流突发引入高频噪声到芯片上的电源；这种噪声可能对噪声水平产生不利影响。对于包含相似数量的 1 和 0 的典型数据流，驱动具有电容 的导线以 R 位/s 的标准 CMOS 输出的动态功耗耗散是
(The actual power dissipation will be slightly higher than this due to secondary effects like the momentary short-circuit current that leaks through CMOS circuits every time they switch state.) 实际功耗会略高于此值，因为存在诸如瞬时短路电流之类的次要影响，每当 CMOS 电路切换状态时，这些电流会泄漏出来。
If we operate an RHS2116 at the maximum sampling rate of , the data rate R is bits . Typical coaxial cables have a capacitance of . The power required to transmit 22.8 Mbit/s over a 2.0 m cable is approximately 25 mW . 如果我们以最大采样率 操作 RHS2116，数据速率 R 为 位 。典型同轴电缆的电容为 。在 2.0 米长的电缆上传输 22.8 兆位/秒所需的功率约为 25 毫瓦。
Transmitting high-frequency data reliably over long wires is challenging due to the presence of reflections that occur when a propagating signal reaches the high-impedance input of a digital receiver. These reflections interfere with the transmitted signal and corrupt the data stream. The characteristic impedance of a cable is given by 通过长电线可靠传输高频数据是具有挑战性的，因为当传播信号到达数字接收器的高阻抗输入时会发生反射。这些反射会干扰传输信号并破坏数据流。电缆的特征阻抗 由以下公式给出
where is the cable inductance per unit length and is the cable capacitance per unit length. For most common cable geometries (e.g., coaxial, twisted pair, ribbon), Z0 falls in the range of . To eliminate reflections, the cable must be terminated with a parallel resistance equal to . 其中 是单位长度的电缆电感， 是单位长度的电缆电容。对于大多数常见的电缆几何形状（例如同轴、双绞线、带状电缆），Z0 落在 的范围内。为了消除反射，电缆必须用与 相等的并联电阻终端。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Standard CMOS digital outputs lack the current sourcing capability to drive the high DC currents necessary to support VDD-level signals (i.e., 3.3 V ) across such small resistances, so proper cable termination cannot be used in these cases. A series resistor with a value of placed near a CMOS digital output can prevent multiple reflections from the highimpedance input at the far end of a cable by absorbing the first reflection, but this is an imperfect solution that fails with high data rates or long cables. 标准 CMOS 数字输出缺乏电流源能力，无法驱动高直流电流，以支持 VDD 电平信号（即 3.3V）通过如此小的电阻，因此在这些情况下无法使用适当的电缆终端。在 CMOS 数字输出附近放置一个值为 的串联电阻可以防止来自电缆远端高阻抗输入的多次反射，通过吸收第一个反射，但这是一个不完美的解决方案，在高数据速率或长电缆的情况下会失败。
LVDS Signaling LVDS 信号传输
LVDS signaling (upper right, previous page) uses a pair of wires (e.g., MISO+ and MISO-) to transmit each digital signal; the wires are terminated with a resistor tied between them near the LVDS receiver. The average voltage on the wire pair is held roughly at 1.25 V , and a 3.5 mA current is forced through the wires in one direction or the other, creating a differential voltage across the terminating resistor to signal a digital one or zero. LVDS 信号（右上角，上一页）使用一对电线（例如，MISO+和 MISO-）来传输每个数字信号；电线在接近 LVDS 接收器处通过一个 电阻器终止。电线对的平均电压大致保持在 1.25 V，通过电线强制流过 3.5 mA 电流，以一种或另一种方向，在终端电阻器之间产生 差分电压，以表示数字一或零。
LVDS signaling offers several advantages over standard CMOS signaling. First, the use of terminated wires drastically reduces reflections, maintaining high signal integrity on long wires and at high data rates. Second, the use of small differential voltages greatly reduces crosstalk to other nearby wires in a cable bundle, especially if twisted pairs are used. Electromagnetic interference and emissions are also minimized using LVDS signaling. Finally, the current drawn from the power supply of the LVDS transmitter is nearly constant (lower right, previous page). This constant current draw does not introduce noise to the on-chip power supply. Thus, LVDS signaling is far better suited for lownoise operation on a chip containing both analog and digital components. LVDS 信号传输相对于标准 CMOS 信号传输具有几个优点。首先，使用终端电缆大大减少了反射，保持了长电缆和高数据速率上的高信号完整性。其次，使用小差分电压大大降低了对电缆捆绑中其他附近电缆的串扰，尤其是在使用绞线对时。使用 LVDS 信号传输还可以最大程度地减少电磁干扰和辐射。最后，从 LVDS 发射器的电源中提取的电流几乎是恒定的（右下角，上一页）。这种恒定的电流不会给芯片上的电源引入噪音。因此，LVDS 信号传输非常适合在同时包含模拟和数字组件的芯片上进行低噪声操作。
The minimum power dissipation of an LVDS transmitter is given by using a 3.3 V power supply. At low frequencies and short wire lengths, standard CMOS signaling can operate at far lower power levels. However, as the calculations in the previous section demonstrate, LVDS can operate at lower power levels when data rates are high and wires are long. LVDS 发射机的最小功耗由 给出，使用 3.3 V 电源。在低频率和短电线长度下，标准 CMOS 信号可以以更低的功率水平运行。然而，正如前一节中的计算所示，当数据速率高且电线较长时，LVDS 可以以更低的功率水平运行。
Cables several meters in length can be used with LVDS signaling as long as the geometry of the cable is fairly consistent along its length. Twisted pairs are particularly good structures for LVDS signaling, and many standard cables contain multiple twisted pairs (e.g., USB, HDMI). The DC series resistance of the cable typically has no effect on the performance of the system as long as it is much less than the terminating resistance of . Signals propagate along standard cables at approximately two-thirds the speed of light, or , so a five-meter cable will introduce a round-trip delay of around 50 ns . As long as the SPI controller accounts for these delays, long cables may be used to communicate with RHS2116 chips reliably. 长度为几米的电缆可以与 LVDS 信号一起使用，只要电缆的几何形状沿着其长度相当一致。扭曲对是 LVDS 信号的特别好结构，许多标准电缆包含多个扭曲对（例如 USB，HDMI）。电缆的 DC 串联电阻通常对系统性能没有影响，只要远端电阻远远小于 。信号在标准电缆上传播的速度约为光速的三分之二，或 ，因此五米长的电缆将引入约 50 纳秒的往返延迟。只要 SPI 控制器考虑到这些延迟，长电缆可以可靠地用于与 RHS2116 芯片通信。
The LVDS inputs and outputs on the RHS2116 use industrystandard LVDS signal levels. Many commercially available FPGAs and microcontrollers have built-in LVDS I/O pins, and can be interfaced directly with the RHS2116. If a controller lacks LVDS I/O, a wide variety of commercially available LVDS-to-standard-CMOS driver and receiver interface chips may be used to translate signal levels (e.g., TI SN65LVDS, SN65LVDT, DS90LV, and DS90C lines; Fairchild FIN10xx line). RHS2116 上的 LVDS 输入和输出使用行业标准的 LVDS 信号电平。许多商用 FPGA 和微控制器都具有内置的 LVDS I/O 引脚，并可以直接与 RHS2116 进行接口。如果控制器缺乏 LVDS I/O，则可以使用各种商用 LVDS 到标准 CMOS 驱动器和接收器接口芯片来转换信号电平（例如 TI SN65LVDS、SN65LVDT、DS90LV 和 DS90C 系列；Fairchild FIN10xx 系列）。
Selecting Signaling Modes on the RHS2116 在 RHS2116 上选择信令模式
If the LVDS_en pin on an RHS2116 is tied to GND, the SPI bus operates with standard CMOS signals, using a single wire for each digital signal. The digital input pins on the RHS2116 interpret any voltage below 0.7 V as logic "low" and any voltage above 2.4 V as logic "high", so the chip can be interfaced with standard , or 3.3 V signals. Digital inputs to the RHS2116 should not go below -0.4 V , and should never exceed 3.6 V . Digital outputs from the RHS2116 chip are driven to ground for logic "low" and to VDD for logic "high". 如果 RHS2116 上的 LVDS_en 引脚接地，SPI 总线将使用标准 CMOS 信号运行，每个数字信号使用单根导线。 RHS2116 上的数字输入引脚将任何低于 0.7 V 的电压解释为逻辑“低”，任何高于 2.4 V 的电压解释为逻辑“高”，因此芯片可以与标准 或 3.3 V 信号进行接口。 RHS2116 的数字输入不应低于-0.4 V，并且永远不应超过 3.6 V。 RHS2116 芯片的数字输出驱动到地为逻辑“低”，驱动到 VDD 为逻辑“高”。
If the LVDS_en pin is tied to VDD, the SPI bus operates in LVDS mode, where every signal in the SPI bus is represented by a differential voltage across a pair of wires (e.g., SCLK+ and SCLK-). The LVDS inputs on the RHS2116 expect a common-mode voltage near 1.25 V and differential signals near , but are fairly tolerant of moderate variations in these values. The LVDS inputs do not include on-chip termination, so a resistor should be placed between each LVDS input signal pair near the chip. Connection diagrams on the following pages provide examples of termination schemes. 如果 LVDS_en 引脚连接到 VDD，SPI 总线将以 LVDS 模式运行，其中 SPI 总线中的每个信号都由一对线（例如，SCLK+和 SCLK-）之间的差分电压表示。RHS2116 上的 LVDS 输入期望一个接近 1.25V 的共模电压和接近 的差分信号，但对这些值的适度变化相当宽容。LVDS 输入不包括芯片上的终端，因此应在每个 LVDS 输入信号对附近的芯片上放置 电阻。以下页面上的连接图提供了终端方案的示例。
Enabling LVDS mode on the RHS2116 increases current consumption by approximately 5.7 mA (from VDD to ground). This includes the 3.5 mA of current driven through the MISO output as well as current to power the three onchip LVDS receivers for CS, SCLK, and MOSI. (Commercial LVDS interface chips typically consume over 17 mA to perform the same functions as the RHS2116 LVDS I/O system.) 在 RHS2116 上启用 LVDS 模式会使电流消耗增加约 5.7 毫安（从 VDD 到地）。这包括通过 MISO 输出驱动的 3.5 毫安电流，以及用于为 CS、SCLK 和 MOSI 供电的三个片上 LVDS 接收器的电流。（商用 LVDS 接口芯片通常消耗超过 17 毫安来执行与 RHS2116 LVDS I/O 系统相同的功能。）
Increased Noise Levels with Standard CMOS Signaling 标准 CMOS 信号传输的噪音水平增加
If standard CMOS signaling is used in combination with high ADC sampling rates, the amplifier noise level on the RHS2116 may rise above its nominal value of , particularly if long, high-capacitance wires are used for the SPI bus. 如果标准 CMOS 信号与高 ADC 采样率结合使用，RHS2116 上的放大器噪声电平可能会超过其标称值 ，特别是如果 SPI 总线使用长、高电容的导线。
The diagram below shows a typical circuit schematic for a single RHS2116 chip interfaced to a controller that is located in close proximity and uses a standard CMOS four-wire SPI interface. In addition to the chip, only four SMD (surface mount device) capacitors are required for a complete biopotential recording/stimulation front end. 下面的图表显示了一个典型的电路原理图，用于将单个 RHS2116 芯片与一个位于附近并使用标准 CMOS 四线 SPI 接口的控制器进行接口连接。除了芯片之外，只需要四个 SMD（表面贴装器件）电容器，就可以完成生物电位记录/刺激前端。
Additional RHS2116 chips can be added using only one additional MISO wire and MOSI wire per chip, provided that all chips receive commands using the same and SCLK signals, as shown below. 只需每个芯片添加一个额外的 MISO 线和 MOSI 线，即可添加额外的 RHS2116 芯片，前提是所有芯片都使用相同的 和 SCLK 信号接收命令，如下所示。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
The diagram below shows a typical circuit schematic for a single RHS2116 chip interfaced to a controller over a long cable, using an SPI interface with low-voltage differential signaling and termination resistors. 下面的图表显示了一个典型的电路原理图，用于将单个 RHS2116 芯片通过一根长电缆与控制器接口连接，使用具有低电压差分信号和 终端电阻的 SPI 接口。
Additional RHS2116 chips can be added as shown below. Only one termination resistor should be used for each LVDS pair; this resistor should be located within 20 cm of LVDS input pins on the RHS2116 chips or the CPU or FPGA. 可以按照下面所示添加额外的 RHS2116 芯片。每个 LVDS 对只应使用一个终端电阻；此电阻应位于距离 RHS2116 芯片或 CPU 或 FPGA 上的 LVDS 输入引脚不超过 20 厘米的位置。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
SPI Bus Signals SPI 总线信号
RHS2116 chips communicate using a standard SPI interface consisting of four signals: an active-low chip select ( ); a serial data clock (SCLK) with a base value of zero; a "Master Out, Slave In" data line (MOSI) to receive commands from the master device; and a "Master In, Slave Out" data line (MISO) to send pipelined results from prior commands to the master device. The RHS2116 chip always functions as the SPI slave device. During each chip select cycle, 32-bit data words are transferred in each direction, MSB first. As shown below, the RHS2116 samples MOSI on the rising edge of SCLK. The master should sample MISO on the rising edge of SCLK. (The master device SPI interface should be configured with SPI options CPOL=0 and CPHA=0.) The line must be pulsed high between every 32-bit data transfer. RHS2116 芯片使用标准的 SPI 接口进行通信，包括四个信号：一个低电平有效的芯片选择（ ）；一个串行数据时钟（SCLK）基值为零；一个“主输出，从输入”数据线（MOSI）用于接收主设备的命令；以及一个“主输入，从输出”数据线（MISO）用于将之前命令的流水线结果发送给主设备。RHS2116 芯片始终作为 SPI 从设备运行。在每个芯片选择周期中，32 位数据字在每个方向传输，最高位先传输。如下所示，RHS2116 在 SCLK 的上升沿上采样 MOSI。主设备应在 SCLK 的上升沿上采样 MISO。（主设备 SPI 接口应配置为 SPI 选项 CPOL=0 和 CPHA=0。）在每次 32 位数据传输之间， 线必须脉冲高电平。
Timing Diagram 时序图
SPI BUS TIMING SPECIFICATIONS SPI 总线定时规格
unless otherwise noted. 除非另有说明。
SYMBOL
PARAMETER
MIN
MAX
UNIT
COMMENTS
tscLK
SCLK Period SCLK 周期
40
ns
Maximum SCLK frequency is 25 MHz 最大 SCLK 频率为 25 MHz
tscLKH
SCLK Pulse Width High SCLK 脉冲宽度高
20
ns
tscLKL
SCLK Pulse Width Low SCLK 脉冲宽度低
20
ns
tcs1
Low to SCLK High Setup SCLK 高电平设置低
20
ns
tcs2
SCLK Low to High Setup SCLK 低至 高设置
20
ns
tcsoff
High Duration 高持续时间
100
ns
tmosi
MOSI 数据有效到 SCLK 高
设置
MOSI Data Valid to SCLK High
Setup
10
ns
tyiso
SCLK 或 下降沿至
MISO 数据有效
SCLK or Falling Edge to
MISO Data Valid
12
ns
torCLE
之间的总周期时间
ADC 样本
Total Cycle Time Between
ADC Samples
1400
ns
最大采样率为 ，或 per
用于 16 个复用通道的通道。
Maximum sample rate is , or per
channel for 16 multiplexed channels.
SPI Command Words SPI 命令字
Each RHS2116 chip responds to four basic commands: perform an analog-to-digital conversion on amplifier signals from a particular channel; initialize ADC settings; write to a RAM register; or read from a RAM or ROM register. Each chip contains many 16-bit RAM registers that configure various aspects of chip behavior and several 16-bit ROM registers that store basic properties of the chip. In addition to the five commands, there are four one-bit flags present in some command words that also control various functions. 每个 RHS2116 芯片响应四个基本命令：对来自特定通道的放大器信号执行模拟到数字转换；初始化 ADC 设置；写入 RAM 寄存器；或从 RAM 或 ROM 寄存器读取。每个芯片包含许多 16 位 RAM 寄存器，用于配置芯片行为的各个方面，以及几个存储芯片基本属性的 16 位 ROM 寄存器。除了这五个命令外，还有四个一位标志存在于一些命令字中，也控制各种功能。
The RHS2116 uses a pipelined communication protocol; each command sent over the MOSI line generates a 32-bit result that is transmitted over the MISO line two commands later. Communication with the chip is illustrated in the following example diagram: RHS2116 使用流水线通信协议；通过 MOSI 线发送的每个命令会生成一个 32 位结果，该结果会在两个命令后通过 MISO 线传输。与芯片的通信如下示例图所示：
In the above diagram, a CONVERT command for channel 3 is issued during the first set of 32 SCLK pulses. Positive pulses separate successive SPI commands. The ADC conversion is executed during the following SPI communication cycle: the AC high-gain amplifier is sampled on the falling edge of following the CONVERT command. If the flag in the CONVERT command is asserted, the DC low-gain amplifier is sampled on the rising edge of the SCLK pulse during this SPI cycle. The results of these ADC conversions are returned over the MISO line during the second SPI communication cycle following the original CONVERT command. See the full description of the CONVERT command below for more details. 在上图中，在前 32 个 SCLK 脉冲的第一组期间发出了通道 3 的 CONVERT 命令。正 脉冲分隔连续的 SPI 命令。ADC 转换在接下来的 SPI 通信周期内执行：在 CONVERT 命令之后的 下降沿上对 AC 高增益放大器进行采样。如果在 CONVERT 命令中断言 标志，则在此 SPI 周期内的 SCLK 脉冲的上升沿上对 DC 低增益放大器进行采样。这些 ADC 转换的结果在原始 CONVERT 命令之后的第二个 SPI 通信周期内通过 MISO 线返回。有关 CONVERT 命令的完整描述，请参见下面的更多详细信息。
A register WRITE command is illustrated below: 下面说明了一个寄存器写入命令：
Here, the MOSI line issues a command to the chip to write the value 5123 to Register 8 . The on-chip register value is not updated until the falling edge of the SCLK pulse during the following SPI communication cycle. The result of the WRITE command is returned via MISO during the following communication cycle. 在这里，MOSI 线向芯片发出命令，将值 5123 写入寄存器 8。在接下来的 SPI 通信周期中，直到 SCLK 脉冲的下降沿，芯片上的寄存器值才会更新。写入命令的结果将在接下来的通信周期中通过 MISO 返回。
Some registers on the RHS2216 are triggered registers. Triggered registers have internal buffers that are programmed with a WRITE command, but the new values do not become active to internal circuits until a command is sent that has the (Update) flag asserted. When the flag is asserted, all triggered registers across the chip update to their buffered values simultaneously. This allows complex, synchronized stimulation patterns to be created across multiple electrodes. RHS2216 上的一些寄存器是触发寄存器。触发寄存器具有内部缓冲区，通过 WRITE 命令进行编程，但新值直到发送具有 （更新）标志的命令才对内部电路生效。当 标志被断言时，芯片上的所有触发寄存器同时更新到它们的缓冲值。这允许在多个电极之间创建复杂的同步刺激模式。
The diagram below shows an example of a WRITE command being issued with the flag asserted: 下面的图表显示了一个使用 标志发出的 WRITE 命令的示例：
Following a command with the flag asserted, all triggered registers update their contents on the falling edge of the SCLK pulse during the SPI communication cycle following the command. 在断言了 标志的情况下，所有触发的寄存器在命令后的 SPI 通信周期中，在 SCLK 脉冲的下降沿更新其内容。
Note that when reading a triggered register, the value returned is the value stored in the internal buffer, which is not necessarily the "active" value of this register unless the flag has been asserted after the last WRITE command issued to this register. 请注意，当读取一个触发寄存器时，返回的值是存储在内部缓冲区中的值，这不一定是该寄存器的“活动”值，除非在上次发出写命令后已经断言了 标志。
The RHS2116 commands are described by the following bit patterns: RHS2116 命令由以下位模式描述：
Command: - Run analog-to-digital conversion on channel C 命令： - 在通道 C 上运行模拟到数字转换
MSB
LSB
31
30
29
28
27
26
0000
000000000000000
Result: 结果：
Comments: 评论：
The CONVERT(C) command executes an analog-to-digital conversion of analog channel C. Channels correspond to the 16 amplifier channels sharing the chip with the ADC. The AC high-gain amplifier is sampled with 16 bits of resolution; its value is returned in the high 16 bits of the 32 -bit result. If the D flag is set to one then the DC low-gain amplifier of channel C is sampled with 10 -bit resolution, and its value is returned in the lower 10 bits of the result. CONVERT(C)命令执行模拟通道 C 的模拟到数字转换。通道 对应于与 ADC 共享芯片的 16 个放大器通道。AC 高增益放大器以 16 位分辨率进行采样；其值返回到 32 位结果的高 16 位中。如果 D 标志设置为 1，则通道 C 的 DC 低增益放大器以 10 位分辨率进行采样，并将其值返回到结果的低 10 位中。
A special case of the CONVERT command with can be used to cycle through successive amplifier channels. The CONVERT(63) command automatically increments the multiplexer to the next amplifier channel. After reaching the end of the amplifier array, the multiplexer rolls back to channel 0 . (Note: The state of the chip is undefined at power-up, so at least one CONVERT(0) command should be sent before executing this variant of the command.) 使用 的 CONVERT 命令的特殊情况可用于循环浏览连续的放大器通道。 CONVERT(63)命令会自动将多路复用器递增到下一个放大器通道。在到达放大器数组的末尾后，多路复用器将回滚到通道 0。（注意：芯片在上电时的状态是未定义的，因此在执行该命令的变体之前，应发送至少一个 CONVERT(0)命令。）
Flags: 标志：
U flag: Setting the U (Update) flag to one updates all "triggered registers" to new values that were previously programmed. U 标志：将 U（更新）标志设置为 1 会将所有“触发寄存器”更新为先前编程的新值。
M flag: Setting the M (Monitor) flag to one clears the compliance monitor register (Register 40). M 标志：将 M（监视器）标志设置为 1 会清除合规性监视器寄存器（寄存器 40）。
D flag: If the D (DC amplifier) flag of a CONVERT command is set to one then the DC low-gain amplifier of channel is also sampled (with 10-bit resolution), and its value is returned in the lower 10 bits of the result. D 标志：如果 CONVERT 命令的 D（DC 放大器）标志设置为 1，则通道 的 DC 低增益放大器也会被采样（分辨率为 10 位），其值将返回在结果的低 10 位中。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
H flag: If the H (High-pass filter) flag of a CONVERT command is set to one when DSP offset removal is enabled (see "DSP HighPass Filter for Offset Removal" section) then the output of the digital high-pass filter associated with amplifier channel C is reset to zero. This can be used to rapidly recover from a large transient and settle to baseline. H 标志：如果在启用 DSP 偏移移除时将 CONVERT 命令的 H（高通滤波器）标志设置为 1（请参见“用于偏移移除的 DSP 高通滤波器”部分），则与放大器通道 C 相关联的数字高通滤波器的输出将被重置为零。这可用于快速从大的瞬态中恢复并稳定到基线。
The CALIBRATE command was included in the Intan Technologies RHD2000 family of amplifier-only chips to initiate an ADC selfcalibration routine that was performed after chip power-up and register configuration. Although the command is included in this chip for continuity, use of the CALIBRATE command is not recommended for the RHS2116. Rather, a CLEAR command should be issued after the chip has been powered up (see next command). CALIBRATE 命令包含在 Intan Technologies RHD2000 系列仅放大器芯片中，用于启动 ADC 自校准例程，该例程在芯片上电和寄存器配置后执行。尽管该命令包含在此芯片中以保持连续性，但不建议在 RHS2116 上使用 CALIBRATE 命令。相反，在芯片上电后应发出 CLEAR 命令（请参见下一个命令）。
The CLEAR command initializes the ADC on the RHS2116 for normal operation. This command should be executed once after chip power-up to maximize the precision of the ADC. CLEAR 命令初始化 RHS2116 上的 ADC，以进行正常操作。应在芯片上电后执行此命令一次，以最大化 ADC 的精度。
The result returned by the RHS2116 consists of all zeros except for the MSB. The MSB will be zero if two's complement mode is enabled (see Register 1 description below); otherwise it will be one. RHS2116 返回的结果除了最高位外全为零。如果启用了二进制补码模式（请参见下面的寄存器 1 描述），则最高位将为零；否则为一。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Command: WRITE(R,D) - Write data D to register R 命令：WRITE（R，D）- 将数据 D 写入寄存器 R
MSB
31
30
29
28
1
0
U
M
0000
LSB
Result: 结果：
MSB
LSB
111111111111111
Comments: 评论：
The WRITE (R,D) command writes a 16-bit data word D to chip register . The data word is echoed back to the master in the lower 16 bits of the result so that correct reception of the data word can be confirmed. The upper 16 bits of the result consist of all ones. WRITE (R,D) 命令将一个 16 位数据字 D 写入芯片寄存器 。数据字 被回传到主机的结果的低 16 位，以便确认数据字的正确接收。结果的高 16 位由全 1 组成。
Any attempt to write to a read-only register (or non-existent register) will produce the same result, but in this case will not be written to the register. 任何尝试写入只读寄存器（或不存在的寄存器）的操作都会产生相同的结果，但在这种情况下， 不会被写入寄存器。
Flags: 标志：
U flag: Setting the U flag to one updates all "triggered registers" to new values that were previously programmed. U 标志：将 U 标志设置为 1 会将所有“触发寄存器”更新为先前编程的新值。
M flag: Setting the M flag to one clears the compliance monitor register (Register 40). M 标志：将 M 标志设置为 1 会清除合规监视器寄存器（寄存器 40）。
Command: READ(R) - Read contents of register 命令：读取（R）- 读取寄存器 的内容
MSB
31
30
29
28
LSB
1
U
M
0000
0000000000000000
Result: 结果：
MSB
LSB
0000000000000000
Comments: 评论：
The command reads the contents of chip register . The data word is sent to the master in the lower 16 bits of the result. The upper 16 bits consist of all zeros. 命令读取芯片寄存器 的内容。数据字 被发送到结果的低 16 位主机。高 16 位由全零组成。
Flags: 标志：
U flag: Setting the U flag to one updates all "triggered registers" to new values that were previously programmed. U 标志：将 U 标志设置为 1 会将所有“触发寄存器”更新为先前编程的新值。
M flag: Setting the M flag to one clears the compliance monitor register (Register 40). M 标志：将 M 标志设置为 1 会清除合规监视器寄存器（寄存器 40）。
Unknown Commands: 未知命令：
If an invalid command is sent (i.e., any command beginning with ' 01 ' that does not correspond to ADC calibration commands), the results returned by the chip will consist of all zeros except for the MSB. The MSB will be zero if two's complement mode is enabled (see Register 1 description below); otherwise it will be one. 如果发送了无效命令（即任何以'01'开头且不对应 ADC 校准命令的命令），芯片返回的结果将由除了最高位之外的所有零组成。如果启用了二进制补码模式（请参见下面的寄存器 1 描述），则最高位将为零；否则为一。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
On-Chip Registers 芯片上的寄存器
Each RHS2116 chip is capable of addressing up to 256 16-bit registers, in any combination of writable (RAM) registers and readonly (ROM) registers. Upon power-up, all RAM registers contain indeterminate data and should be promptly configured by the SPI master device. A CLEAR command should also be issued to set parameters that optimize ADC operation. 每个 RHS2116 芯片能够寻址高达 256 个 16 位寄存器，可以是可写（RAM）寄存器和只读（ROM）寄存器的任意组合。上电时，所有 RAM 寄存器都包含不确定的数据，应该由 SPI 主设备及时配置。还应发出 CLEAR 命令以设置优化 ADC 操作的参数。
Individual bits in a register can be changed only by rewriting the entire 16 -bit contents. Therefore, it is recommended that the SPI master device maintain a copy of RHS2116 register contents in its memory so bitwise operations can be performed there before writing the updated word to the chip using a WRITE command on the SPI bus. 寄存器中的单个位只能通过重新写入整个 16 位内容来更改。因此，建议 SPI 主设备在其内存中保留 RHS2116 寄存器内容的副本，以便在使用 SPI 总线上的写命令将更新的字写入芯片之前在那里执行位操作。
The RAM registers present in each RHS2116 are described below. The detailed functions of some programmable variables were described previously in the datasheet. Note: All multi-bit variables have their most significant bits (MSBs) on the left in the diagrams below, towards the direction of the register MSB D[15]. Bits marked X have no function but should be set to zero for compatibility with any future chip versions. 每个 RHS2116 中的 RAM 寄存器如下所述。一些可编程变量的详细功能在数据表中已经描述过。注意：下面图表中所有多位变量的最高有效位（MSB）在左侧，朝向寄存器 MSB D[15]的方向。标记为 X 的位没有功能，但应设置为零，以便与任何未来芯片版本兼容。
Amplifier Control Registers 放大器控制寄存器
Register 0: Supply Sensor and ADC Buffer Bias Current 寄存器 0：供应传感器和 ADC 缓冲偏置电流
ADC buffer bias ADC 缓冲偏置
MUX bias MUX 偏置
MUX bias [5:0]: This variable configures the bias current of the MUX that routes the selected analog signal to the ADC input. The optimum value for this variable is a function of ADC sampling rate and is listed in a table in the "Analog-to-Digital Converter" section earlier in the datasheet. MUX 偏置[5:0]：此变量配置 MUX 的偏置电流，该电流将选定的模拟信号路由到 ADC 输入。此变量的最佳值是 ADC 采样率的函数，并在数据表中列出，该数据表在数据表早期的“模拟-数字转换器”部分中。
ADC buffer bias [5:0]: This variable configures the bias current of an internal reference buffer in the ADC. The optimum value for this variable is a function of ADC sampling rate and is listed in a table in the "Analog-to-Digital Converter" section earlier in the datasheet. ADC 缓冲偏置[5:0]：此变量配置 ADC 中内部参考缓冲器的偏置电流。此变量的最佳值是 ADC 采样率的函数，并在数据表中的“模数转换器”部分中列出。
Register 1: ADC Output Format, DSP Offset Removal, and Auxiliary Digital Outputs 寄存器 1：ADC 输出格式、DSP 偏移移除和辅助数字输出
XXX
digoutOD 挖掘 OD
digout2 挖掘 2
digout2
HiZ
digout1 挖掘 1
digout1
HiZ
弱
MISO
weak
MISO
twoscomp 二进制补码
absmode 绝对模式
DSPen
DSP 截止
频率
DSP cutoff
freq
DSP cutoff freq [3:0]: This variable sets the cutoff frequency of the DSP filter used to for offset removal. See the "DSP High-Pass Filter for Offset Removal" section for details. DSP 截止频率[3:0]:此变量设置用于去除偏移的 DSP 滤波器的截止频率。有关详细信息，请参阅“用于去除偏移的 DSP 高通滤波器”部分。
DSPen: When this bit is set to one, the RHS2116 performs digital signal processing (DSP) offset removal from all 16 amplifier channels using a first-order high-pass IIR filter. See the "DSP High-Pass Filter for Offset Removal" section for details. DSPen: 当此位设置为 1 时，RHS2116 使用一阶高通 IIR 滤波器从所有 16 个放大器通道执行数字信号处理（DSP）偏移去除。有关详细信息，请参阅“用于去除偏移的 DSP 高通滤波器”部分。
absmode: Setting this bit to one passes all amplifier ADC conversions through an absolute value function. This is equivalent to performing full-wave rectification on the signals, and may be useful for implementing symmetric positive/negative thresholds or envelope estimation algorithms. This bit has no effect on ADC conversions from non-amplifier channels (i.e., ). See the "Absolute Value Mode" section for more information. absmode: 将此位设置为 1 会通过绝对值函数传递所有放大器 ADC 转换。这相当于对信号执行全波整流，并且可能对实现对称正/负阈值或包络估计算法有用。此位对非放大器通道的 ADC 转换没有影响（即 ）。有关更多信息，请参阅“绝对值模式”部分。
twoscomp: If this bit is set to one, AC high-gain amplifier conversions from the ADC are reported using a "signed" two's complement representation where the amplifier baseline is reported as zero and values below baseline are reported as negative numbers. If this bit is set to zero, AC high-gain amplifier conversions from the ADC are reported using "unsigned" offset binary notation where the baseline level of a 16 -bit conversion is represented as 1000000000000000 . ADC conversions from DC lowgain amplifiers are always reported as unsigned binary numbers. twoscomp：如果此位设置为 1，则从 ADC 转换的 AC 高增益放大器使用“有符号”二进制补码表示，其中放大器基线报告为零，低于基线的值报告为负数。如果此位设置为 0，则从 ADC 转换的 AC 高增益放大器使用“无符号”偏移二进制表示，其中 16 位转换的基线级别表示为 1000000000000000。来自 DC 低增益放大器的 ADC 转换始终报告为无符号二进制数。
weak MISO: If this bit is set to zero and the LVDS_en pin is pulled low, the MISO line goes to high impedance mode (HiZ) when is pulled high, allowing multiple chips to share the same MISO line so long as only one of their chip select lines is activated at any time. If only one RHS2116 chip will be using a MISO line, this bit may be set to one, and when is pulled high the MISO 弱 MISO：如果将此位设置为零并且将 LVDS_en 引脚拉低，则当 被拉高时，MISO 线进入高阻态（HiZ），允许多个芯片共享同一 MISO 线，只要它们的芯片选择线中只有一个被激活。如果只有一个 RHS2116 芯片将使用 MISO 线，则可以将此位设置为一，当 被拉高时，MISO
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
line will be driven weakly by the chip. This can prevent the line from drifting to indeterminate values between logic high and logic low. This variable has no effect when LVDS communication is enabled. 线路将由芯片弱驱动。这可以防止线路漂移到逻辑高和逻辑低之间的不确定值。当启用 LVDS 通信时，此变量无效。
digout1 HiZ: The RHS2116 chips have an auxiliary digital output pin auxout1 that may be used to activate off-chip circuitry (e.g., MOSFET switches, LEDs). Setting this bit to one puts this digital output into high impedance (HiZ) mode. See the "Auxiliary Digital Outputs" section for details. digout1 HiZ: RHS2116 芯片具有一个辅助数字输出引脚 auxout1，可用于激活芯片外电路（例如，MOSFET 开关，LED）。将此位设置为 1 会将此数字输出置于高阻态（HiZ）模式。有关详细信息，请参阅“辅助数字输出”部分。
digout1: This bit is driven out of the auxiliary CMOS digital output pin auxout1, provided that the digout1 HiZ bit is set to zero. See the "Auxiliary Digital Outputs" section for details. digout1：此位从辅助 CMOS 数字输出引脚 auxout1 中驱动出来，前提是将 digout1 HiZ 位设置为零。有关详细信息，请参阅“辅助数字输出”部分。
digout2 HiZ: The RHS2116 chips have an auxiliary digital output pin auxout2 that may be used to activate off-chip circuitry (e.g., MOSFET switches, LEDs). Setting this bit to one puts this digital output into high impedance (HiZ) mode. See the "Auxiliary Digital Outputs" section for details. digout2 HiZ: RHS2116 芯片具有一个辅助数字输出引脚 auxout2，可用于激活芯片外电路（例如，MOSFET 开关，LED）。将此位设置为 1 会将此数字输出置于高阻态（HiZ）模式。有关详细信息，请参阅“辅助数字输出”部分。
digout2: This bit is driven out of the auxiliary CMOS digital output pin auxout2, provided that the digout1 HiZ bit is set to zero. See the "Auxiliary Digital Outputs" section for details. digout2：此位从辅助 CMOS 数字输出引脚 auxout2 驱动，前提是将 digout1 HiZ 位设置为零。有关详细信息，请参阅“辅助数字输出”部分。
digoutOD: This bit controls an open-drain auxiliary high-voltage digital output pin auxoutOD. Setting this bit to one pulls the auxoutOD pin to VSTIM-. Setting this bit to zero puts the auxoutOD pin into a high impedance state. See the "Auxiliary Digital Outputs" section for details. digoutOD：此位控制一个开漏辅助高压数字输出引脚 auxoutOD。将此位设置为 1 会将 auxoutOD 引脚拉到 VSTIM-。将此位设置为 0 会将 auxoutOD 引脚置于高阻态。有关详细信息，请参阅“辅助数字输出”部分。
Register 2: Impedance Check Control 寄存器 2：阻抗检查控制
Zcheck select [5:0]
Zcheck
DAC 电源
Zcheck
DAC power
Zcheck load Zcheck 负载
Zcheck scale [1:0] Zcheck 比例[1:0]
Zcheck en
Zcheck en: Setting this bit to one activates impedance testing mode, and connects the on-chip waveform generator to the amplifier selected by the Zcheck select variable. See the "Electrode Impedance Test" section for details. 将此位设置为 1 会激活阻抗测试模式，并将芯片上的波形发生器连接到由 Zcheck 选择变量选择的放大器。有关详细信息，请参阅“电极阻抗测试”部分。
Zcheck scale [1:0]: This variable selects the series capacitor used to convert the voltage waveform generated by the on-chip DAC into an AC current waveform that stimulates a selected electrode for impedance testing: . See the "On-Chip AC Current Waveform Generator" section for more information. Zcheck 比例[1:0]：此变量选择用于将芯片上 DAC 生成的电压波形转换为用于阻抗测试的交流电流波形的串联电容器： 。有关更多信息，请参阅“芯片上交流电流波形发生器”部分。
Zcheck load: Setting this bit to one adds a capacitor load to the impedance checking network. This mode is only used for chip testing at Intan Technologies. This bit should always be set to zero for normal operation. Zcheck 负载：将此位设置为 1 会向阻抗检查网络添加电容负载。此模式仅用于 Intan Technologies 的芯片测试。对于正常操作，此位应始终设置为零。
Zcheck DAC power: Setting this bit to one activates the on-chip digital-to-analog converter (DAC) used to generate waveforms for electrode impedance measurement. If impedance testing is not being performed, this bit can be set to zero to reduce current consumption (from VDD to GND) by . See the "On-Chip AC Current Waveform Generator" section for more information. Zcheck DAC 电源：将此位设置为 1 会激活芯片上的数字模拟转换器（DAC），用于生成电极阻抗测量的波形。如果不进行阻抗测试，可以将此位设置为 0，以减少电流消耗（从 VDD 到 GND） 。有关更多信息，请参阅“芯片上的交流电流波形发生器”部分。
Zcheck select [5:0]: This variable selects the electrode to be connected to the on-chip impedance testing circuitry if Zcheck en is set to one. In the RHS2116 16-channel chip, the two MSBs of this six-bit register is ignored. See the "Electrode Impedance Test" section for details. Zcheck select [5:0]: 如果 Zcheck en 被设置为一，此变量选择要连接到芯片上阻抗测试电路的电极。在 RHS2116 16 通道芯片中，此六位寄存器的两个最高有效位被忽略。详细信息请参阅“电极阻抗测试”部分。
Register 3: Impedance Check DAC 寄存器 3：阻抗检查 DAC
Zcheck DAC [7:0]
Zcheck DAC [7:0]: This variable sets the output voltage of an 8-bit DAC used to generate waveforms for impedance checking. This variable must be updated at regular intervals to create the desired waveform. Note that this DAC must be enabled by setting Zcheck DAC power in Register 2. If impedance testing is not in progress, the value of this register should remain unchanged to minimize noise (although writing the same value to the register is acceptable). See the "On-Chip AC Current Waveform Generator" section for more information. Zcheck DAC [7:0]: 这个变量设置用于生成阻抗检测波形的 8 位 DAC 的输出电压。必须定期更新此变量，以创建所需的波形。请注意，必须通过在寄存器 2 中设置 Zcheck DAC 电源来启用此 DAC。如果阻抗测试未在进行中，则此寄存器的值应保持不变，以减少噪音（尽管将相同的值写入寄存器是可以接受的）。有关更多信息，请参阅“芯片内 AC 电流波形发生器”部分。
RH1 sel1 [5:0], RH1 sel2 [4:0], RH2 sel1 [5:0], and RH2 sel2 [4:0]: These variables set the upper cutoff frequency of the biopotential amplifiers. A table in this datasheet provides appropriate register values for setting the upper cutoff frequency in the range of 100 Hz to 20 kHz . RH1 sel1 [5:0], RH1 sel2 [4:0], RH2 sel1 [5:0], 和 RH2 sel2 [4:0]：这些变量设置生物电放大器的上限截止频率。本数据表中的一张表格提供了在 100 Hz 至 20 kHz 范围内设置上限截止频率的适当寄存器值。
RL_A sel1 [6:0], RL_A sel2 [5:0], and RL_A sel3: These variables set the "A version" of the lower cutoff frequency of the biopotential amplifiers. A table in this datasheet provides appropriate register values for setting the lower cutoff frequency in the range of 0.1 Hz to 1 kHz . The amp fL select variable in Register 12 allows users to rapidly switch amplifiers between two different lower cutoff frequencies as a means for rapidly recovering from stimulation artifacts. RL_A sel1 [6:0]，RL_A sel2 [5:0]和 RL_A sel3：这些变量设置生物电放大器的下限截止频率的“A 版本”。本数据表中的一张表提供了在 0.1 Hz 至 1 kHz 范围内设置下限截止频率的适当寄存器值。寄存器 12 中的 amp fL 选择变量允许用户快速在两个不同的下限截止频率之间切换放大器，作为快速从刺激伪影中恢复的手段。
RL_B sel1 [6:0], RL_B sel2 [5:0], and RL_B sel3: These variables set the "B version" of the lower cutoff frequency of the biopotential amplifiers. A table in this datasheet provides appropriate register values for setting the lower cutoff frequency in the range of 0.1 Hz to 1 kHz . The amp fL select variable in Register 12 allows users to rapidly switch amplifiers between two different lower cutoff frequencies as a means for rapidly recovering from stimulation artifacts. RL_B sel1 [6:0], RL_B sel2 [5:0] 和 RL_B sel3：这些变量设置生物电放大器的下限截止频率的“B 版本”。本数据表中的一张表格提供了在 0.1 Hz 至 1 kHz 范围内设置下限截止频率的适当寄存器值。寄存器 12 中的 amp fL select 变量允许用户快速在两个不同的下限截止频率之间切换放大器，作为快速从刺激伪影中恢复的手段。
Register 8: Individual AC Amplifier Power 寄存器 8：个人交流放大器电源
AC amp power [15:0] AC 安培功率[15:0]
AC amp power [15:0]: Setting these bits to zero powers down individual AC-coupled high-gain amplifiers, saving power if there are channels that don't need to be observed. Each amplifier consumes power in proportion to its upper cutoff frequency. Current consumption is approximately per AC amplifier, from VDD to GND. Under normal operation, these bits should be set to one. AC 放大器功率[15:0]：将这些位设置为零会关闭单个 AC 耦合高增益放大器，如果有不需要观察的通道，则可以节省电源。每个放大器的功耗与其上限截止频率成比例。每个 AC 放大器的电流消耗约为 ，从 VDD 到 GND。在正常操作下，这些位应设置为 1。
Register 9: reserved for future expansion 寄存器 9：保留用于未来扩展
Register 10: Amplifier Fast Settle (TRIGGERED REGISTER) 寄存器 10：放大器快速稳定（触发寄存器）
amp fast settle [15:0] amp 快速结算[15:0]
amp fast settle [15:0]: Setting any of these bits to one closes a switch in an AC high-gain amplifier that drives its analog output to the baseline "zero" level. This can be used to quickly recover from large transient events (e.g., stimulation) that may drive the amplifiers to their rails. The switch should be closed for a certain amount of time to settle the amplifiers (see "Fast Settle Function" section for details) and then this register should be reset to zero to resume normal amplifier operation. Register 10 is a triggered amp fast settle [15:0]：将这些位中的任何一个设置为 1 会关闭交流高增益放大器中的开关，将其模拟输出驱动到基准“零”电平。这可用于快速恢复大型瞬态事件（例如，刺激）可能将放大器驱动到其轨道的情况。应关闭开关一段时间以稳定放大器（有关详细信息，请参见“快速稳定功能”部分），然后应将此寄存器重置为零以恢复正常放大器操作。寄存器 10 是一个触发器。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the U flag must be asserted to update the active value of this register (and all other triggered registers on the chip). 寄存器，意味着其值必须首先通过写命令编程到芯片上的缓冲区中，然后必须断言 U 标志以更新该寄存器的活动值（以及芯片上的所有其他触发寄存器）。
Register 11: reserved for future expansion 寄存器 11：保留供将来扩展使用
amp fL select [15:0]: These bits select between two different lower cutoff frequencies for each high-gain amplifier. If a particular bit is set to one, the corresponding amplifier has a lower cutoff frequency set by the RL_A setting in Register 6 . If the bit is set to zero, the amplifier has a lower cutoff frequency set by the RL_B setting in Register 7 . The ability to switch rapidly between two lower cutoff frequencies can be used to reduce the amplifier recovery time after stimulation artifacts. For example, under normal operation a user may wish to use a very low cutoff frequency (e.g., ) to observe low-frequency signals like local field potentials (LFPs). The consequence of setting a very lot cutoff frequency is a slow recovery time with a time constant of . A higher low-frequency cutoff (e.g., 250 Hz ) may be used for brief periods during and/or following stimulation pulses to reduce this amplifier recovery time constant. See the "Amplifier Stimulus Artifact Recovery" section for more details. Register 12 is a triggered register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the flag must be asserted to update the active value of this register (and all other triggered registers on the chip). amp fL select [15:0]：这些位选择每个 高增益放大器的两个不同的下限截止频率。如果特定位设置为一，则相应的放大器具有由寄存器 6 中的 RL_A 设置设置的较低截止频率。如果该位设置为零，则放大器具有由寄存器 7 中的 RL_B 设置设置的较低截止频率。在两个较低截止频率之间快速切换的能力可用于减少刺激伪迹后的放大器恢复时间。例如，在正常操作下，用户可能希望使用非常低的截止频率（例如， ）来观察低频信号，如局部场电位（LFPs）。设置非常低的截止频率的后果是恢复时间较慢，时间常数为 。可以在刺激脉冲期间和/或之后的短暂时期内使用更高的低频截止频率（例如，250 Hz）来减少这种放大器恢复时间常数。有关更多详细信息，请参阅“放大器刺激伪迹恢复”部分。 寄存器 12 是一个触发寄存器，这意味着其值必须首先通过写命令编程到芯片上的缓冲区中，然后必须断言 标志以更新该寄存器的活动值（以及芯片上的所有其他触发寄存器）。
Registers 13-31: reserved for future expansion 寄存器 13-31：保留用于未来扩展
stim enable A [15:0] and stim enable B [15:0]: These 32 bits must be set to particular "magic numbers" to enable the on-chip stimulators. If these exact values are not programmed, all stimulators are disabled. This prevents stimulators from being active when the chip is first powered up when all registers contain random data . To enable stimulation, stim enable must be set to binary 1010101010101010 (hex AAAA; decimal 43690 ) and stim enable B must be set to binary 0000000011111111 (hex 00FF; decimal 255). Note that the stim_en pin must also be pulled high (to VDD) for the on-chip stimulators to be enabled. When an RHS2116 chip is first powered up, at least one of these registers should be cleared to zero to ensure that stimulation is disabled. After all the stimulation registers have been written to and the triggered registers updated, then the proper values can be written to these two registers to enable stimulation. 刺激使能 A [15:0] 和刺激使能 B [15:0]：这 32 位必须设置为特定的“魔术数字”才能启用芯片上的刺激器。如果未编程这些确切值，则所有刺激器将被禁用。这可以防止在芯片首次上电时，当所有寄存器包含随机数据时刺激器处于活动状态。要启用刺激，刺激使能必须设置为二进制 1010101010101010（十六进制 AAAA；十进制 43690），刺激使能 B 必须设置为二进制 0000000011111111（十六进制 00FF；十进制 255）。请注意，刺激使能引脚也必须拉高（至 VDD）才能启用芯片上的刺激器。当 RHS2116 芯片首次上电时，至少应将这些寄存器中的一个清零以确保刺激被禁用。在所有刺激寄存器被写入并触发寄存器更新后，然后可以将适当的值写入这两个寄存器以启用刺激。
The chance of stimulation being enabled on power-up is not completely eliminated but is reduced to , or approximately one in 4.3 billion. If this risk is too high, an external device can be used to hold stim_en low (at GND) until all on-chip registers have been properly initialized. 开机时启用刺激的机会并未完全消除，但降低到 ，大约为 43 亿分之一。如果这个风险太高，可以使用外部设备将 stim_en 保持低电平（接地），直到所有芯片上的寄存器都已正确初始化。
Register 34: Stimulation Current Step Size 寄存器 34：刺激电流步长
step sel1 [6:0], step sel2 [5:0], and step sel3 [1:0]: This variable sets the step size of the 8-bit current-output DACs in each onchip stimulator. A table earlier in the datasheet provides appropriate register values for setting the stimulation step size in the range of step (for a full-scale range of ) to (for a full-scale range of ). This register is typically set once shortly after a chip is powered up, and then the stimulation current magnitudes on each channel are set to multiples of this current using Registers 64-79 and 96-111. 步骤 sel1 [6:0]，步骤 sel2 [5:0]和步骤 sel3 [1:0]：此变量设置每个片上刺激器中 8 位电流输出 DAC 的步长。数据表中提供了适当的寄存器值，用于设置刺激步长范围从 步（全幅范围为 ）到 步（全幅范围为 ）。此寄存器通常在芯片上电后不久设置一次，然后使用寄存器 64-79 和 96-111 将每个通道上的刺激电流幅度设置为此电流的倍数。
stim Pbias [3:0] and stim Nbias [3:0]: These variables configure internal bias voltages that optimize the compliance range of the stimulator circuits. The optimum values for these variables are a function of stimulation step size (set in Register 34) and are listed in a table earlier in the datasheet. This register is typically set once shortly after the chip is powered up. 刺激 P 偏置[3:0]和刺激 N 偏置[3:0]：这些变量配置内部偏置电压，优化刺激器电路的兼容范围。这些变量的最佳值是刺激步长（在寄存器 34 中设置）的函数，并在数据表中的早期列出。该寄存器通常在芯片上电后不久设置一次。
Register 36: Current-Limited Charge Recovery Target Voltage 寄存器 36：电流限制充电恢复目标电压
charge recovery DAC 充电恢复 DAC
charge recovery DAC [7:0]: This variable sets the output voltage of an 8 -bit DAC used to generate a voltage in the range of -1.225 V to +1.215 V that is used by the current-limited charge recovery circuits. When current-limited (CL) charge recovery is enabled, an electrode is pulled toward this voltage. When this register is set to 128, the target voltage is zero. The DAC step size is 9.57 mV . When the register is set to 0 , the target voltage reaches its minimum value of -1.225 V . When the register is 255 , the target voltage is at its maximum value of +1.215 V . See the "Current-Limited Charge Recovery Circuit" section for more details. 充电恢复 DAC [7:0]：此变量设置用于生成范围为 -1.225 V 到 +1.215 V 的电压的 8 位 DAC 的输出电压，该电压由限流充电恢复电路使用。当启用限流充电恢复 (CL) 时，电极会被拉向该电压。当此寄存器设置为 128 时，目标电压为零。DAC 步长为 9.57 毫伏。当寄存器设置为 0 时，目标电压达到其最小值 -1.225 V。当寄存器设置为 255 时，目标电压达到其最大值 +1.215 V。有关更多详细信息，请参阅“限流充电恢复电路”部分。
Register 37: Charge Recovery Current Limit 寄存器 37：充电恢复电流限制
sel1
Imax sel1 [6:0], Imax sel2 [5:0], and Imax sel3 [1:0]: These variables set the maximum current supplied (per channel) by the current-limited charge recovery circuit in each channel. When current-limited (CL) charge recovery is enabled, an electrode is pulled toward the voltage set by Register 36 with a current limited to the maximum current set by these variables. A table earlier in the datasheet provides appropriate register values for setting this current. See the "Current-Limited Charge Recovery Circuit" section for more details. Imax sel1 [6:0]、Imax sel2 [5:0] 和 Imax sel3 [1:0]：这些变量设置了每个通道中电流限制充电恢复电路提供的最大电流（每通道）。当启用电流限制（CL）充电恢复时，电极被拉向由寄存器 36 设置的电压，并且电流被限制在这些变量设置的最大电流。数据表中的一个表提供了设置此电流的适当寄存器值。有关更多详细信息，请参阅数据表中的“电流限制充电恢复电路”部分。
Register 38: Individual DC Amplifier Power 寄存器 38：个人 DC 放大器电源
DC amp power [15:0] DC 安培功率[15:0]
DC amp power [15:0]: This register was originally included on the chip to provide a modest power savings in cases where the DC-coupled low-gain amplifiers were not used. However, a hardware bug in the chip counterintuitively causes current drawn from VDD to increase when these amplifiers are powered down. For each DC amplifier channel that is powered down, the current from VDD increases by 1.93 mA . It is therefore strongly recommended that Register 38 be set to all ones as soon as the chip is powered up. This enables all DC-coupled low-gain amplifiers and reduces power consumption DC 安培功率[15:0]：该寄存器最初包含在芯片上，以在未使用 DC 耦合低增益放大器的情况下提供适度的节能。然而，芯片中的硬件错误导致当这些放大器关闭电源时，从 VDD 抽取的电流反直觉地增加。每个关闭电源的 DC 放大器通道，从 VDD 抽取的电流增加 1.93 毫安。因此，强烈建议在芯片上电后立即将寄存器 38 设置为全 1。这样可以启用所有 DC 耦合低增益放大器并降低功耗。
Register 39: reserved for future expansion 寄存器 39：保留用于未来扩展
Register 40: Compliance Monitor (READ ONLY REGISTER WITH CLEAR) 寄存器 40：合规监视器（只读寄存器，带清除功能）
compliance monitor [15:0] 合规监控器 [15:0]
compliance monitor [15:0]: This is a read-only variable, but its contents can be cleared to zero by using the M flag during a CONVERT, READ, or WRITE command. Bits in this variable are set high when the corresponding stimulator exceeds its compliance voltage limit (either positive or negative) during stimulation and is unable to source or sink the requested current through an electrode. Typically this register is cleared prior to stimulation and checked periodically during or after stimulation to detect voltage compliance problems. See the "Compliance Monitor" section for more details. 合规监视器[15:0]：这是一个只读变量，但可以通过在执行 CONVERT、READ 或 WRITE 命令时使用 M 标志将其内容清零。当相应的刺激器在刺激过程中超过其合规电压限制（正或负）且无法通过电极提供或吸收请求的电流时，此变量中的位被设置为高电平。通常在刺激之前清除此寄存器，并在刺激期间或之后定期检查以检测电压合规问题。有关更多详细信息，请参阅“合规监视器”部分。
Register 41: reserved for future expansion 寄存器 41：保留用于未来扩展
Register 42: Stimulator On (TRIGGERED REGISTER) 寄存器 42：刺激器开启（触发寄存器）
on [15:0] 在 [15:0]
stim on [15:0]: Bits in this variable turn on current sources in corresponding stimulators. A bit value of one activates the current source; a bit value of zero turns off the current. Register 42 is a triggered register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the flag must be asserted to update the active value of this register (and all other triggered registers on the chip). 在[15:0]上的刺激：此变量中的位打开相应刺激器中的电流源。位值为 1 时激活电流源；位值为 0 时关闭电流。寄存器 42 是一个触发寄存器，这意味着必须首先使用 WRITE 命令将其值编程到芯片上的缓冲区中，然后必须断言 标志以更新该寄存器的活动值（以及芯片上的所有其他触发寄存器）。
Register 43: reserved for future expansion 寄存器 43：保留用于未来扩展
stim pol [15:0]: Bits in this variable set the polarity of current drive in corresponding stimulators. Setting a bit to zero produces negative current (i.e., cathodic current flowing into the chip that drives an electrode toward negative voltages). Setting a bit to one produces positive current (i.e., anodic current flowing out of the chip that drives an electrode toward positive voltages). Register 44 is a triggered register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the flag must be asserted to update the active value of this register (and all other triggered registers on the chip). stim pol [15:0]：此变量中的位设置相应刺激器中电流驱动的极性。将位设置为零会产生负电流（即，阴极电流流入驱动电极朝负电压方向）。将位设置为一会产生正电流（即，阳极电流从芯片流出，驱动电极朝正电压方向）。寄存器 44 是一个触发寄存器，这意味着必须首先使用 WRITE 命令将其值编程到芯片上的缓冲区中，然后必须断言 标志以更新此寄存器的活动值（以及芯片上的所有其他触发寄存器）。
Register 45: reserved for future expansion 寄存器 45：保留用于未来扩展
charge recovery switch [15:0]: Bits in this variable control on-chip transistor switches that connect a selected electrode to the common stim_GND pin. If stim_GND is tied to ground, these switches can be used to reset the potential of an electrode to ground and recover any residual charge resulting from mismatched biphasic stimulation. Setting a bit to one closes the corresponding switch. Under normal operation, these bits should be set to zero. Register 46 is a triggered register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the flag must be asserted to update the active value of this register (and all other triggered registers on the chip). See the "Charge Recovery Switch" section for more details. 充电恢复开关[15:0]：此变量中的位控制芯片上的晶体管开关，将选定的电极连接到公共 stim_GND 引脚。如果 stim_GND 接地，这些开关可用于将电极的电位重置为地面，并恢复由不匹配的双相刺激产生的任何残余电荷。将位设置为一会关闭相应的开关。在正常操作下，这些位应设置为零。寄存器 46 是一个触发寄存器，意味着其值必须首先通过 WRITE 命令编程到芯片上的缓冲区中，然后必须断言 标志以更新此寄存器的活动值（以及芯片上所有其他触发寄存器的值）。有关更多详细信息，请参阅“充电恢复开关”部分。
Register 47: reserved for future expansion 寄存器 47：保留用于未来扩展
CL charge recovery enable [15:0]: Bits in this variable connect a selected electrode to a current-limited driver that pulls the electrode to a voltage set by Register 36 with a maximum current set by Register 37. These drivers can be used to reset an electrode to a desired potential and recover any residual charge resulting from mismatched biphasic stimulation. Setting a bit to one connects an electrode to its current-limited driver. Under normal operation, these bits should be set to zero. Register 48 is a triggered register, meaning its value must first be programmed into an on-chip buffer using a WRITE command, and then the U flag must be asserted to update the active value of this register (and all other triggered registers on the chip). See the "CurrentLimited Charge Recovery Circuit" section for more details. CL 充电恢复使能[15:0]：此变量中的位将选定的电极连接到一个受限电流驱动器，该驱动器将电极拉到由寄存器 36 设置的电压，并且最大电流由寄存器 37 设置。这些驱动器可用于将电极重置为所需电位并恢复由不匹配的双相刺激产生的任何残余电荷。将位设置为 1 将电极连接到其受限电流驱动器。在正常操作下，这些位应设置为零。寄存器 48 是一个触发寄存器，这意味着其值必须首先通过 WRITE 命令编程到芯片上的缓冲区中，然后必须断言 U 标志以更新此寄存器的活动值（以及芯片上的所有其他触发寄存器）。有关更多详细信息，请参阅“受限电流充电恢复电路”部分。
Register 49: reserved for future expansion 寄存器 49：保留用于未来扩展
Register 50: Fault Current Detector (READ ONLY REGISTER) 寄存器 50：故障电流检测器（只读寄存器）
00000000000000
fault current detect 故障电流检测
fault current detect: This read-only bit is set to one by internal circuitry if the current through the fault current detector exceeds approximately in either direction. The exact threshold for fault current detection can vary between and from chip to chip. The fault current detector is typically wired in series with a common stimulation current return electrode (i.e., counter electrode), and this variable can be used to detect unintended current flow. Unlike compliance monitor in Register 40, the value of this variable is not latched; it reflects the real-time state of the current through the fault detector. See the "Fault Current Detector" section for more details. 故障电流检测：如果通过故障电流检测器的电流超过大约 ，则此只读位将由内部电路设置为 1。故障电流检测的确切阈值可以在芯片之间变化，通常在 和 之间。故障电流检测器通常与共同的刺激电流回归电极（即反电极）串联，此变量可用于检测意外电流流动。与寄存器 40 中的合规监视器不同，此变量的值不是锁存的；它反映了通过故障检测器的电流的实时状态。有关更多详细信息，请参阅“故障电流检测器”部分。
Registers 51-63: reserved for future expansion 寄存器 51-63：保留供将来扩展使用
Registers 64-79: Negative Stimulation Current Magnitude (TRIGGERED REGISTERS) 寄存器 64-79：负刺激电流幅度（触发寄存器）
negative current trim 负电流修剪
negative current magnitude [7:0] 负电流幅度 [7:0]
negative current magnitude [7:0]: This variable sets the magnitude of the negative current on a particular stimulator. Registers set negative current magnitudes on stimulation channels . The stimulation current step size is set by Register 34 . Registers 64-79 are triggered registers, meaning values must first be programmed into on-chip buffers using a WRITE command, and then the flag must be asserted to update the active value of these registers (and all other triggered registers on the chip). See the "Constant-Current Stimulator" section for more details. 负电流幅度[7:0]：此变量设置特定刺激器上负电流的幅度。 寄存器 设置刺激通道 上的负电流幅度。 刺激电流步进大小由寄存器 34 设置。 寄存器 64-79 是触发寄存器，意味着值必须首先通过 WRITE 命令编程到芯片缓冲区中，然后必须断言 标志以更新这些寄存器的活动值（以及芯片上的所有其他触发寄存器）。 有关更多详细信息，请参阅“恒定电流刺激器”部分。
negative current trim [7:0]: This variable can be used to trim the value of negative stimulation current over a range of approximately . This can be used to compensate for small variations in stimulation current across different stimulator channels. Normally this register should be set to a value of 128 . Values less than 128 will reduce the current by about step; values greater than 128 will increase the current by about step. 负电流修剪 [7:0]：此变量可用于修剪负刺激电流的值，范围约为 。这可用于补偿不同刺激器通道间刺激电流的小变化。通常应将此寄存器设置为值 128。小于 128 的值将减少电流约 步；大于 128 的值将增加电流约 步。
Registers 80-95: reserved for future expansion 寄存器 80-95：保留用于未来扩展
Registers 96-111: Positive Stimulation Current Magnitude (TRIGGERED REGISTERS) 寄存器 96-111：正刺激电流幅度（触发寄存器）
positive current trim [7:0] 正电流修剪 [7:0]
positive current magnitude [7:0] 正电流大小 [7:0]
positive current magnitude [7:0]: This variable sets the magnitude of the positive current on a particular stimulator. Registers set positive current magnitudes on stimulation channels . The stimulation current step size is set by Register 34. Registers are triggered registers, meaning values must first be programmed into on-chip buffers using a WRITE command, and then the flag must be asserted to update the active value of these registers (and all other triggered registers on the chip). See the "Constant-Current Stimulator" section for more details. 正电流幅度[7:0]：此变量设置特定刺激器上正电流的幅度。寄存器 设置刺激通道 上的正电流幅度。刺激电流步长由寄存器 34 设置。寄存器 是触发寄存器，意味着值必须首先通过写命令编程到芯片缓冲区中，然后必须断言 标志以更新这些寄存器的活动值（以及芯片上所有其他触发寄存器的值）。有关更多详细信息，请参阅“恒流刺激器”部分。
positive current trim [7:0]: This variable can be used to trim the value of positive stimulation current over a range of approximately . This can be used to compensate for small variations in stimulation current across different stimulator channels. Normally this register should be set to a value of 128 . Values less than 128 will reduce the current by about step; values greater than 128 will increase the current by about step. 正电流修剪 [7:0]：此变量可用于在大约 范围内修剪正刺激电流的值。这可用于补偿不同刺激器通道间刺激电流的小变化。通常，此寄存器应设置为 128。小于 128 的值将使电流减少约 步；大于 128 的值将使电流增加约 步。
Registers 112-250: reserved for future expansion 寄存器 112-250：保留用于未来扩展
Note: All registers labeled as "reserved for future expansion" can be ignored. There are no registers on the RHS2116 corresponding to these addresses. 注意：所有标记为“保留以供将来扩展”的寄存器可以忽略。在 RHS2116 上没有对应这些地址的寄存器。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
On-Chip Read-Only Registers 芯片上的只读寄存器
Each RHS2116 chip contains the following ROM registers that provide information on the identity and capabilities of the particular chip. 每个 RHS2116 芯片都包含以下 ROM 寄存器，提供有关特定芯片的身份和功能的信息。
Registers 251-253: Company Designation 寄存器 251-253：公司指定
Register 251: 注册 251:
01001001 (ASCII 'l') 01001001
01001110 (ASCII ' N ')
Register 252: 注册 252:
ASCII ' ') ASCII ' '
01000001 (ASCII 'A')
Register 253: 注册 253:
' N ') ' N '
00000000
The read-only registers 251-253 contain the characters INTAN in ASCII. The contents of these registers can be read to verify the fidelity of the SPI interface. 只读寄存器 251-253 包含 ASCII 中的字符 INTAN。这些寄存器的内容可以读取以验证 SPI 接口的准确性。
Register 254: Number of Channels and Die Revision 寄存器 254：通道数量和芯片修订
die revision [7:0] 修订 [7:0]
num of channels [7:0] 通道数量 [7:0]
die revision [7:0]: This read-only variable encodes a die revision number which is set by Intan Technologies to encode various versions of a chip. die revision [7:0]: 这个只读变量编码了一个芯片的不同版本，由 Intan Technologies 设置。
num of channels [7:0]: This read-only variable encodes the total number of amplifier/stimulation channels on the chip (i.e., 16). 通道数[7:0]：这个只读变量编码了芯片上放大器/刺激通道的总数（即 16）。
Register 255: Intan Technologies Chip ID 寄存器 255：Intan Technologies 芯片 ID
00000000
chip ID [7:0]: This read-only variable encodes a unique Intan Technologies ID number indicating the type of chip. The chip ID for the RHS2116 is 32. 芯片 ID [7:0]：此只读变量编码了一个唯一的 Intan Technologies ID 号码，指示芯片的类型。RHS2116 的芯片 ID 为 32。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Example Chip Initialization Procedure 示例芯片初始化过程
Following is a series of SPI commands that can be sent to the RHS2116 after power-up to initialize the chip for an application where all 16 channels will be sampled at a rate of , along with comments. The details of these commands can be modified to suit particular uses. Consult the register descriptions on the preceding pages for more information on each operation. 以下是一系列可以在上电后发送到 RHS2116 的 SPI 命令，以初始化芯片，用于所有 16 个通道以 的速率进行采样的应用，以及相关注释。这些命令的细节可以根据特定用途进行修改。有关每个操作的更多信息，请参考前面页面上的寄存器描述。
Write to registers , setting the positive stimulation current magnitudes to zero and the current
trims to the center point. (These commands do not take effect until the flag is asserted since
Registers are triggered registers.)
WRITE(32, 0xAAAA)
WRITE(33, 0x00FF)
现在所有的刺激器都已初始化并关闭，启用刺激（只要刺激器已启用
引脚被拉到 VDD)。
Now that all the stimulators are initialized and turned off, enable stimulation (as long as the stim_en
pin is pulled to VDD).
标志
flag
Dummy command with M flag set to clear the compliance monitor (Register 40). 设置 M 标志位的虚拟命令，用于清除合规性监视器（寄存器 40）。
The chip is now initialized. Note that it was not necessary to assert the flag during every WRITE issued to a triggered register. Since the stimulators were disabled for most of this sequence, it would be fine to simply assert the U flag immediately prior to enabling stimulation by writing to registers 32 and 33. 芯片现在已初始化。请注意，在向触发寄存器发出的每个写入操作期间不需要断言 标志。由于在大部分序列中刺激器被禁用，因此在通过写入寄存器 32 和 33 启用刺激之前简单地断言 U 标志即可。
Additional commands could include a series of READ commands to verify the contents of all RAM registers. Prior to executing the commands listed above, a series of READ commands to ROM registers could be issued to verify the integrity of the SPI interface and adjust the timing of MISO sampling, for example. This may be essential if the round-trip SPI bus delay is not known (e.g., due to the use of variable-length interface cables). 额外的命令可能包括一系列的读取命令，以验证所有 RAM 寄存器的内容。在执行上述列出的命令之前，可以发出一系列读取 ROM 寄存器的命令，以验证 SPI 接口的完整性并调整 MISO 采样的时序，例如。如果往返 SPI 总线延迟未知（例如，由于使用可变长度接口电缆），这可能是必要的。
Following is a series of 20 commands that could be repeated in an infinite loop to sample all 16 amplifiers on the chip and update the stimulators at the amplifier sampling rate: 以下是一系列可以在无限循环中重复的 20 个命令，以采样芯片上的所有 16 个放大器并以放大器采样速率更新刺激器：
SPI command SPI 命令
Comment 评论
CONVERT(0) 转换(0)
Perform ADC conversions on the AC and DC amplifiers in all 16 channels. 在所有 16 个通道上对交流和直流放大器执行 ADC 转换。
and/or 12), or managing charge recovery (Register 46 and/or 48).
WRITE(?, ?)
写入(?, ?)
WRITE(?, ?)
WRITE(?, ?)
Update polarity on all stimulators. 更新所有刺激器的极性。
WRITE(44, ?) 写(44, ?)
Turn stimulators on or off, and trigger all changes from the last four WRITE commands. 打开或关闭刺激器，并触发自上次四个写命令以来的所有更改。
WRITE(42, ?)
U 标志
WRITE(42, ?)
U flag
The SPI commands should be sent at a rate that sets the overall per-channel sampling rate to the desired frequency. If the sampling rate is set to then the stimulators may be updated once every . Note that if the amplifiers are not sampled and all command slots are used to control the stimulators then stimulation can be controlled with a much finer time scale. Other methods of interleaving the stimulation-related WRITE commands with ADC-related CONVERT commands are possible and may be better suited for particular applications. SPI 命令应以一种速率发送，该速率将整体每通道采样率设置为所需频率。如果采样率设置为 ，则刺激器可能每 更新一次。请注意，如果放大器未被采样，并且所有命令槽用于控制刺激器，则刺激可以以更精细的时间尺度进行控制。还可以使用其他方法将与刺激相关的写命令与 ADC 相关的转换命令交错，这可能更适合特定应用。
Package Dimensions 包装尺寸
All dimensions are in millimeters. 所有尺寸均为毫米。
Printed Circuit Board Layout 印刷电路板布局
44-Pin QFN Package 44 引脚 QFN 封装
Note: The center pad of the QFN is internally connected to VSTIM-. The center pad on the circuit board should tied to the negative stimulation power supply. 注意：QFN 的中心垫片内部连接到 VSTIM-。电路板上的中心垫片应该连接到负刺激电源。
Pricing Information 定价信息
See www.intantech.com for current pricing. All price information is subject to change without notice. Quantities may be limited. All orders are subject to current pricing at time of acceptance by Intan Technologies. Additional charges may apply for international purchases and shipping. 查看www.intantech.com获取当前价格。所有价格信息可能会在不经通知的情况下更改。数量可能有限。所有订单在 Intan Technologies 接受时将按照当前价格计算。国际购买和运输可能会产生额外费用。
Contact Information 联系信息
This datasheet is meant to acquaint engineers and scientists with the general characteristics of the RHS2116 digital electrophysiology stimulator/amplifier chip developed at Intan Technologies. We value feedback from potential end users. 本资料表旨在让工程师和科学家了解 Intan Technologies 开发的 RHS2116 数字电生理刺激器/放大器芯片的一般特性。我们重视潜在最终用户的反馈。
For more information, contact Intan Technologies at: 有关更多信息，请联系 Intan Technologies：
Information furnished by Intan Technologies is believed to be accurate and reliable. However, no responsibility is assumed by Intan Technologies for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. Intan Technologies assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Intan Technologies components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. Intan Technologies 提供的信息被认为是准确可靠的。然而，Intan Technologies 对其使用不承担任何责任，也不对可能由此使用导致的专利侵权或其他第三方权利侵犯承担责任。规格如有变更，恕不另行通知。Intan Technologies 不对应用程序协助或客户产品设计承担责任。客户应对其使用 Intan Technologies 组件的产品和应用程序负责。为减少与客户产品和应用程序相关的风险，客户应提供足够的设计和操作保障措施。
Intan Technologies' products are not authorized for use as critical components in life support devices or systems. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Intan Technologies 的产品未经授权用作生命支持设备或系统中的关键组件。关键组件是生命支持设备或系统的任何组件，其未能正常工作可能合理地预期会导致生命支持设备或系统的故障，或影响其安全性或有效性。
RHS2116 Digital Electrophysiology Stimulator/Amplifier Chip RHS2116 数字电生理刺激器/放大器芯片
Document Revision History 文档修订历史
20 January 2016: 2016 年 1 月 20 日:
Original document released. 原始文件发布。
18 January 2018: 2018 年 1 月 18 日:
Changed recommended value of MUX bias (in Register 0) for ADC sampling rates above from 7 to 5 (see table, page 15). 将 ADC 采样率高于 的 MUX 偏置（在寄存器 0 中）的推荐值从 7 更改为 5（请参见表格，第 15 页）。
2 February 2018: 2018 年 2 月 2 日:
Added warning against leaving VSTIM+ and VSTIM- unconnected (see pages 4 and 23). 增加警告，不要让 VSTIM+和 VSTIM-未连接（请参阅第 4 页和第 23 页）。
Added warning not to use VSTIM power supplies exceeding 14V total (e.g., ) to avoid failures of anodic current generators after many stimulation pulse cycles (page 15). 添加警告，不要使用超过 14V 总电压的 VSTIM 电源（例如， ），以避免在许多刺激脉冲周期后阳极电流发生器故障（第 15 页）。
