NOTES:  注意：

1. RAS features may not be supported on all SKUs of a processor type.
   处理器类型的所有 SKU 可能不支持 RAS 功能。
2. A two socket workstation SKU supports a standard RAS SKU.
   一个双插槽工作站 SKU 支持标准的 RAS SKU。

11.2.1 Error Detection and Correction
11.2.1 错误检测和纠正

• Uncorrected No Action (UCNA) - Uncorrecteable data is logged in the MCA bank with a unique signature ( ). The error containment bit (also known as poison bit) is attached to the bad data and forwarded to the requesting agent. Such an error classification can trigger a CSMI in the eMCA gen2 mode.
  未校正无操作（UCNA）- 无法校正的数据记录在具有唯一签名（ ）的 MCA 存储器中。错误包含位（也称为毒位）附加到错误数据并转发给请求代理。这种错误分类可以在 eMCA gen2 模式下触发 CSMI。
• Software Recoverable Action Optional (SRAO) - There is no SRAO error type support on the platform. SRAO type events is reverted to UCNA. The OS/software action remains the same for error types that used to signal SRAO and now signaling UCNA.
  软件可恢复操作可选（SRAO）- 平台不支持 SRAO 错误类型。SRAO 类型事件被还原为 UCNA。对于以前用于表示 SRAO 并且现在表示 UCNA 的错误类型，OS/软件操作保持不变。
• Software Recoverable Action Required (SRAR) - Bad data or instruction in the core execution path can result in an SRAR error in the MCA bank status with unique signature ( ). For example, Data Cache Unit ( ) load/ store and Instruction Fetch Unit (IFU) load operations on poisoned data. Such error classification can trigger MSMI in eMCA gen2.
  软件可恢复操作必需（SRAR）- 核心执行路径中的错误数据或指令可能导致 MCA 存储器状态中具有唯一签名（ ）的 SRAR 错误。例如，对毒数据进行的数据缓存单元（ ）加载/存储和指令获取单元（IFU）加载操作。这种错误分类可以在 eMCA gen2 中触发 MSMI。

• Machine check architecture: MCA
  机器检查架构：MCA
• Advance error reporting (exclude UCR): AER
  高级错误报告（不包括 UCR）：AER
• Detected but uncorrectable error: DUE
  检测到但无法纠正的错误: DUE
• Uncorrected recoverable: UCR
  未纠正的可恢复错误: UCR
• Uncorrected no action required IA32_MCi_STATUS; ( : UCNA
  未纠正的无需采取行动的错误 IA32_MCi_STATUS; ( : UCNA
• SRAO IA32_MCi_STATUS; /not supported in this generation processors: SRAO
  SRAO IA32_MCi_STATUS; /此代处理器不支持: SRAO
• Software recoverable action required IA32_MCi_STATUS; ( , ): SRAR
  软件可恢复操作所需 IA32_MCi_STATUS; ( , ): SRAR

NOTES: 注释:

1. Assumes the legacy IA-32 MCA mode. Error reporting includes both error logging and signaling.
   假定传统的 IA-32 MCA 模式。错误报告包括错误日志记录和信号。
2. Defined as advanced error detection and correction (AEDC).
   定义为高级错误检测和纠正（AEDC）。
3. Log and signal memory data read errors. Shadow registers for UEFI-FW use.
   记录和信号内存数据读取错误。为 UEFI-FW 使用的影子寄存器。
4. PCU logs the corrected error for the platform debug purpose, but does not signal CMCI.
   PCU 记录已更正的错误，用于平台调试目的，但不会发出 CMCI 信号。
5. Log and signal normal data read and patrol scrub data read errors.
   记录并发出正常数据读取和巡逻擦除数据读取错误信号。
6. Address Path Parity Protection (APPP)
   地址路径奇偶校验保护（APPP）

11.2.2 Advanced Error Detection and Correction - AEDC
11.2.2 高级错误检测和纠正 - AEDC

11.2.3 Error Reporting (MCA, AER) - Core, Uncore and IIO
11.2.3 错误报告（MCA，AER）- 核心，非核心和 IIO

1. MCA-based Error Reporting: A mechanism to capture and log the first fault in case of an uncorrected error and first or last fault in case of a corrected error. This includes all modules within the processor - core, uncore, and IIO (via IOMCA). See Machine Check Architecture-Based Error Reporting on page 229 for further details.
   基于 MCA 的错误报告：一种机制，用于在发生未纠正错误时捕获和记录第一个故障，在发生已纠正错误时捕获第一个或最后一个故障。这包括处理器内的所有模块 - 核心、非核心和 IIO（通过 IOMCA）。有关更多详细信息，请参阅第 229 页的基于机器检查架构的错误报告。
2. Integrated Error Handler (IEH) 2.0, based Error Reporting: The processor implements a unified and hierarchical error handler called Integrated Error Handler (IEH). It incorporates the global IEH located in the UBOX and satellite IEH located inthe various IIO sub-modules, for example, PCI Express root ports, traffic switch, IRP, IIO core, Intel -d, and DSA. As per the PCI Express Specification, it includes an optional extended capability called PCIe Advanced Error Reporting (PCIe AER) that provides more robust error reporting than the standard PCI Express error reporting mechanism. See the PCI Express Error Reporting on page 247 for further details. The IEH Rev. 2.0 brings to IEH domain error reporting of IIO stack's internal functional units.
   集成错误处理程序（IEH）2.0，基于错误报告：处理器实现了一个统一和分层的错误处理程序，称为集成错误处理程序（IEH）。它包括位于 UBOX 中的全局 IEH 和位于各种 IIO 子模块中的卫星 IEH，例如，PCI Express 根端口、流量交换机、IRP、IIO 核心、Intel -d 和 DSA。根据 PCI Express 规范，它包括一个名为 PCIe 高级错误报告（PCIe AER）的可选扩展功能，提供比标准 PCI Express 错误报告机制更强大的错误报告。有关更多详细信息，请参阅第 247 页的 PCI Express 错误报告。IEH Rev. 2.0 将 IIO 堆栈的内部功能单元的错误报告引入到 IEH 领域。
3. Inte UPI Error Reporting: Intel UPI error logging and signaling capability. See Intel UPI link Sub system RAS features.
   Intel UPI 错误报告：Intel UPI 错误记录和信令功能。请参阅 Intel UPI 链路子系统 RAS 功能。
4. Integrated Voltage Regulator (IVR) Error Reporting: IVR error logging and signaling capability. See the Integrated Voltage Regulator (IVR) Error Reporting on page 239 for further details.
   集成电压调节器（IVR）错误报告：IVR 错误记录和信令功能。有关更多详细信息，请参阅第 239 页上的集成电压调节器（IVR）错误报告。
5. Memory Corrected Error Reporting: Memory corrected error logging and signaling. See the Memory Corrected Error Reporting on page 240 for further details.
   内存校正错误报告：内存校正错误记录和信令。有关更多详细信息，请参阅第 240 页上的内存校正错误报告。

1. Error logging 错误日志记录
2. Error signaling 错误信号传递

NOTES 笔记

1. Assumes the legacy IA-32 MCA mode of signaling.
   假定信号传输的是传统的 IA-32 MCA 模式。
2. In addition to MCERR signaling, the processor asserts the CATERR_N pin low for 16 BCLKs.
   除了 MCERR 信号传输外，处理器还会在 16 个 BCLK 时钟周期内将 CATERR_N 引脚置为低电平。
3. In addition to IERR signaling, the processor asserts the CATERR_N pin persistently low until reset.
   除了 IERR 信号传输外，处理器会持续将 CATERR_N 引脚置为低电平，直到复位。

11.2.4 Machine Check Architecture-Based Error Reporting
11.2.4 机器检查架构基础错误报告

NOTE 注意

11.2.4.1 Enhanced Cache Error Reporting
11.2.4.1 增强缓存错误报告

11.2.4.2 Machine Check Architecture Based Corrected Error Signaling
11.2.4.2 机器检查架构基于纠正错误信号

NOTES 注意事项

1. The information is preliminary and may change during the design phase of the processor. Consult your local Intel representative prior to finalizing your design.
   该信息为初步信息，可能会在处理器设计阶段发生变化。在最终确定设计之前，请咨询您当地的英特尔代表。
2. Supports CMCI on an uncorrected error only when the corrupt data containment mode is enabled.
   仅当启用了损坏数据包含模式时，才支持 CMCI 处理未校正的错误。
3. is broadcast to the only thread within the core and not to other cores and sockets in the system. If a corrected error is detected outside of cores (that is, within the uncore), then the CMCI is signaled to all the logical threads within the socket. In either case, CMCI is not signaled to other sockets in a multi-socket system.
   被广播到核心内的唯一线程，而不是系统中的其他核心和插槽。如果在核心之外（即在非核心内）检测到校正错误，则向套接字内的所有逻辑线程发出 CMCI 信号。在任何情况下，CMCI 不会向多插槽系统中的其他插槽发出信号。

11.2.4.3 Machine Check Architecture Based Uncorrected Recoverable (UCR)
11.2.4.3 基于机器检查架构的不可纠正恢复性（UCR）错误

11.2.4.4 Machine Check Architecture Based Uncorrected (Fatal and Catastrophic) Error Signaling
11.2.4.4 基于机器检查架构的不可纠正（致命和灾难性）错误信令

• MCERR - Machine check architecture is enabled by setting CR4.MCE. MCERR is signaled to all cores in the socket and the CATERR_N pin will also be asserted.
  MCERR - 通过设置 CR4.MCE 启用机器检查体系结构。MCERR 信号发送到插座中的所有内核，并且 CATERR_N 引脚也将被断言。
• IERR - Refers to a catastrophic error, the processor core may not be able to execute reliably and may not fully process an INT18 handler flow. The following are some possible cases of such catastrophic errors:
  IERR - 指的是灾难性错误，处理器核心可能无法可靠执行，也可能无法完全处理 INT18 处理程序流。以下是一些可能发生此类灾难性错误的情况：
• Retirement watchdog time-out from the core
  核心退休监控超时
• MCERR when CR4.MCE is not set to 1 in the core
  当核心中 CR4.MCE 未设置为 1 时出现 MCERR
• Power Control Unit (PCU) errors
  电源控制单元（PCU）错误
• Factory-configuration download failures
  工厂配置下载失败

11.2.4.5 Machine Check Architecture Based External Error Signaling
11.2.4.5 机器检查架构基于外部错误信号

NOTE 注意

11.2.4.6 MCA Bank Error Reporting Modes
11.2.4.6 MCA 银行错误报告模式

1. Legacy IA-32 MCA mode
   传统的 IA-32 MCA 模式
2. Corrupt Data Containment (CDC) (also known as poison mode)
   损坏数据封装（CDC）（也称为毒模式）
3. Corrupt data containment + viral mode
   损坏数据封装 + 病毒模式

11.2.5 Integrated Error Handler (IEH) Based Error Reporting
11.2.5 集成错误处理程序（IEH）基于错误报告

11.2.5.1 IEH - Functional Description
11.2.5.1 IEH - 功能描述

11.2.5.2 IEH - Error Detection, Correction, and Reporting
11.2.5.2 IEH - 错误检测、纠正和报告

1. The CPU implements a global IEH, which is the central resource for logging and escalation errors. In addition to the global IEH, the CPU implements multiple satellite IEHs. In such implementations, global IEH and the satellite IEHs are connected to form an IEH hierarchy as shown in the figure above.
   CPU 实现了一个全局 IEH，这是记录和升级错误的中央资源。除了全局 IEH 外，CPU 还实现了多个卫星 IEH。在这种实现中，全局 IEH 和卫星 IEH 连接在一起，形成如上图所示的 IEH 层次结构。
2. Every IEH in a processor presents itself as a PCIe device (with BDF) to the software.
   处理器中的每个 IEH 都会向软件呈现为一个 PCIe 设备（带有 BDF）。
3. A unique device ID is assigned to IEH - global IEH ( ), satellite IEH (DID and revision ID is zero (RID for both.
   为全球 IEH（ ）和卫星 IEH（DID ）分配了唯一的设备 ID，修订 ID 对于两者都是零（RID ）。
4. Error detection and header logging is done for the first uncorrectable error (fatal or non-fatal).
   对于第一个不可纠正的错误（致命或非致命），进行错误检测和标题记录。
5. Allows flexible mapping of the detected errors to different error severity.
   允许将检测到的错误灵活映射到不同的错误严重性。
6. Allows different customers to have flexible options for various kinds of signaling SMI/NMI, ERROR_N[2:0] pins, MSI/INTx, and/or IOMCA. The global IEH sends error severity and Bus/Func/Dev information to the IOMCA.
   允许不同的客户端对各种类型的信令 SMI/NMI、ERROR_N[2:0] 引脚、MSI/INTx 和/或 IOMCA 进行灵活的选项。全局 IEH 将错误严重性和总线/功能/设备信息发送到 IOMCA。
7. Incorporates PCI Express specifications based advanced error reporting with the following key features:
   结合基于 PCI Express 规范的高级错误报告，具有以下关键特性：

8. If no satellite IEHs are present, then all the devices in the processor forward error information to the global IEH over sideband.
   如果没有卫星 IEH 存在，则处理器中的所有设备将通过旁路将错误信息转发到全局 IEH。
9. The satellite IEH supports PCIe, Do_Serr, Correctable_AER, and Uncorrectable_AER.
   卫星 IEH 支持 PCIe、Do_Serr、Correctable_AER 和 Uncorrectable_AER。

11.2.6 Intel VT-d Translation Engine Error Reporting
11.2.6 Intel VT-d 翻译引擎错误报告

11.2.7 Intel UPI Error Reporting
11.2.7 Intel UPI 错误报告

11.2.7.1 Intel UPI Corrected Error Reporting
11.2.7.1 Intel UPI 纠正错误报告

11.2.7.2 Intel UPI Uncorrected Fatal Error Reporting
11.2.7.2 Intel UPI 未校正致命错误报告

11.2.8 Integrated Voltage Regulator (IVR) Error Reporting
11.2.8 集成电压调节器（IVR）错误报告

• Boot IVR Fault: The Boot IVR is removed from the processor. The boot logic is now powered from the motherboard VR.
  引导 IVR 故障：引导 IVR 已从处理器中移除。现在引导逻辑由主板 VR 供电。
• Core IVR Fault: A core IVR fault is asserted by an IERR on the CATERR_N pin, and it is possible to perform a FRB with the failing core disabled. Core IVR faults are logged to the CORE_FIVR_ERR_LOG CSR. This register contains a bit for each processor core at a bit position corresponding to the core's logical ID. Any bit set to "1" indicates an IVR fault has been detected for that core. When a warm reset is performed after a core IVR fault, the processor disables any core with an IVR fault indicated in CORE_FIVR_ERR_LOG. The RESOLVED_CORES CSR will be updated to indicate the failing core has been disabled.
  核心 IVR 故障：CATERR_N 引脚上的 IERR 断言了核心 IVR 故障，并且可以在故障核心禁用的情况下执行 FRB。核心 IVR 故障被记录到 CORE_FIVR_ERR_LOG CSR 中。该寄存器包含一个位，对应于核心逻辑 ID 的位位置。任何设置为“1”的位表示已检测到该核心的 IVR 故障。在核心 IVR 故障后执行热复位时，处理器将禁用 CORE_FIVR_ERR_LOG 中指示有 IVR 故障的任何核心。RESOLVED_CORES CSR 将被更新以指示故障核心已被禁用。
• Uncore IVR Fault: An uncore IVR fault is asserted by an IERR on the CATERR_N pin. A BMC monitoring CATERR_N can detect this failure and determine the specific cause of the IERR over PECI. Uncore IVR faults are logged to the UNCORE_FIVR_ERR_LOG CSR. Any non-zero value in that CSR indicates an uncore IVR fault has been detected. Once the BMC determines a specific socket has asserted IERR as a result of an uncore IVR fault, the BMC may initiate socket-level Fault Resilient Booting (FRB) procedures.
  非核心 IVR 故障：CATERR_N 引脚上的 IERR 断言了非核心 IVR 故障。监视 CATERR_N 的 BMC 可以检测到此故障，并通过 PECI 确定 IERR 的具体原因。非核心 IVR 故障被记录到 UNCORE_FIVR_ERR_LOG CSR 中。该 CSR 中的任何非零值表示已检测到非核心 IVR 故障。一旦 BMC 确定特定插座由于非核心 IVR 故障而断言 IERR，BMC 可能会启动插座级别的故障恢复引导（FRB）过程。

11.2.9 Memory Corrected Error Reporting
11.2.9 内存校正错误报告

NOTE 注意

11.2.10 Error Reporting Via the IOMCA
11.2.10 通过 IOMCA 进行错误报告

11.2.10.1 Functional Description
11.2.10.1 功能描述

11.2.10.2 Error Signaling
11.2.10.2 错误信号

11.2.11 First Corrected Error (FCERR) Mode
11.2.11 第一个已更正错误 (FCERR) 模式

1. The Retry_rd_err_log registers can be configured to not overwrite the corrected error through the NOOVER bit in the CSR.
   通过 CSR 中的 NOOVER 位，可以配置 Retry_rd_err_log 寄存器不覆盖已纠正的错误。
2. A latched corrected error does not impact the corrected error counters operation.
   锁存的已纠正错误不会影响已纠正错误计数器的操作。

11.2.12 Error Reporting Through MCA 2.0 (EMCA Gen 2)
11.2.12 错误报告通过 MCA 2.0 (EMCA Gen 2)

1. Most of the uncorrected errors (UCE) would require routing to NMI, the NMI handler may lose fault containment. Additionally, NMI precludes error recovery in cases where such UCE may be recoverable.
   大多数未纠正的错误（UCE）需要路由到 NMI，NMI 处理程序可能会丢失故障隔离。此外，在这种 UCE 可能是可恢复的情况下，NMI 排除了错误恢复的可能性。
2. UCNA error reporting via the SCI may not be fast enough.
   通过 SCI 进行的 UCNA 错误报告可能不够快。
3. Some error logs are blocked within UEFI-FW/FW level access. It constrains OSbased error handling capability. For example, some error logs or registers are recorded in the CSR or MSR shadow registers that may not be fully accessed by the OS/VMM level.
   一些错误日志在 UEFI-FW/FW 级别访问中被阻止。这限制了基于 OS 的错误处理能力。例如，一些错误日志或寄存器记录在 CSR 或 MSR 影子寄存器中，可能无法被 OS/VMM 级别完全访问。

1. Allows the SMM code to intercept MCERR/CMCI.
   允许 SMM 代码拦截 MCERR/CMCI。
2. Allows the SMM code to write the MCA Status/Add/Misc. registers(Advanced RAS only).
   允许 SMM 代码写入 MCA 状态/添加/杂项寄存器（仅适用于高级 RAS）。
3. Allows the SMM code to invoke the Int18 handler for the original MCERR condition.
   允许 SMM 代码调用原始 MCERR 条件的 Int18 处理程序。
4. Allows the DSM based pointer for enhanced error logs.
   允许基于 DSM 的指针用于增强错误日志。
5. Additional IA32_MCG_CAP bit for EMCA support
   为 EMCA 支持添加额外的 IA32_MCG_CAP 位。

• Provides an opportunity for the platform firmware to deliver richer error logs to higher level software at the time of signaling. Additional error information is delivered to the system software through the ACPI DSM and Enhanced MCA L1 Directory data structure synchronous with MCE or CMCI.
  提供了一个机会，使平台固件能够在信号传递时向更高级别软件提供更丰富的错误日志。通过 ACPI DSM 和增强 MCA L1 目录数据结构，附加的错误信息与 MCE 或 CMCI 同步地传递给系统软件。
• Provides an opportunity for the platform firmware to log all errors for their own diagnostic purposes.
  为平台固件提供了一个机会，记录所有错误以供诊断目的。
• Advanced RAS provides an additional capability for platform SMM firmware error recovery from uncorrected errors enabled (in addition to the opportunity already available in the hardware and OS/VMM level). It also provides the ability for SMM to write non-zero values into the MCi_Status, MCi_Addr and MCi_Misc registers.
  高级 RAS 为平台 SMM 固件提供了额外的能力，用于从未纠正的错误中进行错误恢复（除了硬件和 OS/VMM 级别已经可用的机会之外）。它还提供了 SMM 将非零值写入 MCi_Status、MCi_Addr 和 MCi_Misc 寄存器的能力。

• EMCA Gen 2 MCA capability bit is set in the global IA32_MCG_CAP register (bit 25) to indicate that individual MCA banks may have EMCA Gen 2 capability.
  在全局 IA32_MCG_CAP 寄存器中设置 EMCA Gen 2 MCA 能力位（位 25），以指示单个 MCA 银行可能具有 EMCA Gen 2 能力。
• A read-only SMM visible MSR (SMM_MCA_CAP) provides a bit/bank indication whether the corresponding bank supports EMCA Gen 2 capabilities.
  一个只读的 SMM 可见的 MSR（SMM_MCA_CAP）提供了一个位/银行指示，指示相应的银行是否支持 EMCA Gen 2 的功能。
• EMCA Gen 2 control bits 32 and 34 in each IA32_MCi_CTL2 register. These bits are programmable by UEFI FW and are not visible to the SW/OS/VMM. Therefore, reading bits 32 and 34 inthe IA32_MCi_CTL2 register by SW/OS/VMM will always return zeroes and writing a non-zero value will result in #GP fault.
  每个 IA32_MCi_CTL2 寄存器中的 EMCA Gen 2 控制位 32 和 34。这些位可由 UEFI 固件进行编程，对于 SW/OS/VMM 不可见。因此，通过 SW/OS/VMM 读取 IA32_MCi_CTL2 寄存器中的位 32 和 34 将始终返回零，并写入非零值将导致 #GP 错误。

• CORE_SMI_ERR_SRC and UNCORE_SMI_ERR_SRCcidentify the sources of the triggered event. See the Granite Rapids Processor Registers Specification for details of each MSR. There may be more than one MCA bank that signaled the SMI.
  CORE_SMI_ERR_SRC 和 UNCORE_SMI_ERR_SRCc 识别触发事件的来源。有关每个 MSR 的详细信息，请参阅 Granite Rapids 处理器寄存器规范。可能有多个 MCA 银行发出了 SMI 信号。