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Stimulus-Artifact Elimination in a Multi-Electrode System
多电极系统中的刺激伪影消除

Abstract:

To fully exploit the recording capabilities provided by current and future generations of multi-electrode arrays, some means to eliminate the residual charge and subseque...View more

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Abstract: 摘要：

To fully exploit the recording capabilities provided by current and future generations of multi-electrode arrays, some means to eliminate the residual charge and subsequent artifacts generated by stimulation protocols is required. Custom electronics can be used to achieve such goals, and by making them scalable, a large number of electrodes can be accessed in an experiment. In this work, we present a system built around a custom 16-channel IC that can stimulate and record, within 3 ms of the stimulus, on the stimulating channel, and within 500 mus on adjacent channels. This effectiveness is achieved by directly discharging the electrode through a novel feedback scheme, and by shaping such feedback to optimize electrode behavior. We characterize the different features of the system that makes such performance possible and present biological data that show the system in operation. To enable this characterization, we present a framework for measuring, classifying, and understanding the multiple sources of stimulus artifacts. This framework facilitates comparisons between artifact elimination methodologies and enables future artifact studies.
为了充分利用当前和未来多电极阵列的记录能力，需要某种方法来消除刺激协议产生的残余电荷和随后的伪影。可以使用定制电子设备来实现这些目标，并通过使其具有可扩展性，在实验中可以访问大量电极。在这项工作中，我们展示了一个围绕定制的 16 通道集成电路构建的系统，该系统可以在刺激后 3 毫秒内在刺激通道上进行刺激和记录，并在邻近通道上在 500 微秒内进行记录。这种效果是通过一种新颖的反馈方案直接放电电极，并通过优化电极行为来调整这种反馈来实现的。我们对系统的不同特性进行了表征，使其具备这样的性能，并展示了显示系统运行的生物数据。为了实现这一表征，我们提出了一个用于测量、分类和理解多种刺激伪影来源的框架。该框架有助于伪影消除方法之间的比较，并为未来的伪影研究提供了支持。

Published in: IEEE Transactions on Biomedical Circuits and Systems ( Volume: 2, Issue: 1, March 2008)
发表于：IEEE 生物医学电路与系统汇刊（卷：2，期：1，2008 年 3 月）

Page(s): 10 - 21 页码：10 - 21

Date of Publication: March 2008
出版日期：2008 年 3 月

ISSN Information: ISSN 信息:

PubMed ID: 23852629

DOI: 10.1109/TBCAS.2008.918285IF: 5.1 Q1
DOI: 10.1109/TBCAS.2008.918285IF: 5.1 Q1 影响因子: 5.1 Q1

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Contents 目录

SECTION I. 第一部分

Introduction 介绍

Extracellular electrodes are a common tool for the recording and stimulation of electrically active tissue, with applications that go beyond the laboratory into medical implantable devices from pacemakers to deep brain stimulators. Biological neural tissue, and especially mammalian brains, possesses very large neural densities. To extract meaningful information from these networks, large electrode counts are required. In general the need to gain access to large neural populations has made multi-electrode arrays ubiquitous in neural research fields [1]–[3]. Such is the case for some of the ambitious brain–computer interfacing efforts for prosthetic applications [4], [5], in vivo applications [6]–[8], and in vitro applications such as our Micro Neural Interfacing System (μNIS) effort in the development of 3-D in vitro neural models [9]–[11].
细胞外电极是记录和刺激电活性组织的常用工具，其应用不仅限于实验室，还扩展到从起搏器到脑深部刺激器的医用植入设备。生物神经组织，尤其是哺乳动物大脑，具有非常高的神经密度。为了从这些网络中提取有意义的信息，需要大量的电极。一般来说，获取大型神经群体的需求使多电极阵列在神经研究领域变得无处不在。这种情况在一些用于假肢应用的雄心勃勃的脑机接口研究中也是如此，用于体内应用以及体外应用，如我们的微神经接口系统（Micro Neural Interfacing System，NIS）在 3D 体外神经模型开发中的应用。

Microscale technologies have facilitated the commercialization of multi-electrode arrays (MEAs) that incorporate hundreds of electrodes [12]. Most existing commercial systems [Multi-Channel Systems (MCS), Plexon, Cyberkinetics, etc.], however, still use discrete components for the ancillary amplification and interfacing circuitry; this choice makes the transition to larger electrode counts cumbersome and costly. Several companies and researchers are addressing this problem by developing integrated circuits (ICs) with relatively large channel counts; these ICs reduce costs and facilitate significant size reductions for the interfacing hardware [8], [13]–[19].
微尺度技术促进了包含数百个电极的多电极阵列（MEA）的商业化。然而，大多数现有的商业系统（Multi-Channel Systems (MCS)、Plexon、Cyberkinetics 等）仍然使用离散组件进行辅助放大和接口电路；这种选择使得向更大电极数量的过渡变得繁琐且昂贵。为解决这一问题，几家公司和研究人员正在开发具有相对大量通道的集成电路（IC）；这些 IC 降低了成本，并显著减小了接口硬件的尺寸。

Another problem, which has troubled electrophysiologists since early stimulation experiments, is the introduction of stimulation artifacts that obscure any neural activity near the stimulation site for tens or hundreds of milliseconds [20]. The stored electrode charge, which ultimately generates the artifact, introduces problems for long-term stimulation protocols, as it could cause ion migration or general recording system saturation. Although several investigators have tried to cancel the artifact after it has occurred [21], [22], and some groups have tried to eliminate it altogether [23], [24], there is little understanding of the artifact process and properties.
另一个自早期刺激实验以来一直困扰电生理学家的问题是刺激伪影的引入，这会在刺激部位附近数十或数百毫秒内掩盖任何神经活动 [20] 。最终生成伪影的存储电极电荷为长期刺激协议引入了问题，因为它可能导致离子迁移或记录系统的整体饱和。尽管几位研究人员试图在伪影发生后取消它 [21] ， [22] ，一些研究组试图完全消除它 [23] ， [24] ，但对伪影过程和性质的理解仍然很少。

In the present work we describe and characterize a stimulation, recording, and artifact elimination system (Fig. 1) developed around our custom ICs. Our artifact elimination system is built around a second-generation IC (Fig. 2) that introduces improvements in noise performance and stimulation circuitry with respect to the one described in [15]. This system was developed as part of a larger collaboration for the development of in-vitro 3-D neural systems under a Bioengineering Research Partnership grant.
在本工作中，我们描述并表征了围绕我们定制的集成电路（ Fig. 1 ）开发的刺激、记录和伪影消除系统。我们的伪影消除系统基于第二代集成电路（ Fig. 2 ），相较于 [15] 中描述的系统，它在噪声性能和刺激电路方面引入了改进。该系统是作为生物工程研究合作伙伴计划下开发的体外三维神经系统更大合作的一部分而开发的。

Fig. 1. - Biological interfacing system. The MEA is connected by means of an MCS preamplifier plate (being used passively as an interface). See Fig. 6 for a high-level schematic of the stimulation board. In the IC testing setup, Matlab and other instrumentation are used instead of the MCS hardware and software.

Fig. 1. 图 1.

Biological interfacing system. The MEA is connected by means of an MCS preamplifier plate (being used passively as an interface). See Fig. 6 for a high-level schematic of the stimulation board. In the IC testing setup, Matlab and other instrumentation are used instead of the MCS hardware and software.
生物界面系统。MEA 通过 MCS 前置放大器板连接（被动用作接口）。高层次的刺激板原理图见 Fig. 6 。在 IC 测试设置中，使用 Matlab 和其他仪器代替 MCS 硬件和软件。

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$Fig. 2. - Photomicrograph of a section of the IC showing 3 of its 16 channels and their associated support circuitry. The largest visible structures are the 16.3 pF input capacitors. Note that less than 25% of the available IC area (of 2 mm $\,\times\,$2 mm) is currently being used.$

Fig. 2. 图 2.

Photomicrograph of a section of the IC showing 3 of its 16 channels and their associated support circuitry. The largest visible structures are the 16.3 pF input capacitors. Note that less than 25% of the available IC area (of 2 mm ×2 mm) is currently being used.
光学显微照片显示集成电路的一部分，其中包含 16 个通道中的 3 个及其相关的支持电路。最大可见结构是 16.3 pF 的输入电容。注意，目前仅使用了可用集成电路面积（2 毫米 × 2 毫米）不到 25%的区域。

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SECTION II. 第二节

Stimulation Artifacts 刺激伪影

Although further investigation is required to completely describe the stimulation artifact, we will present an overview of the principal factors that are relevant to this work. We focus on the use of a linear RC model of the electrode as a first-order approximation to the problem. In order to help standardize the study of stimulation artifacts and the factors that influence them, we provide our definitions while differentiating among the multiple possible artifact sources.
虽然需要进一步调查才能完全描述刺激伪影，但我们将概述与这项工作相关的主要因素。我们重点介绍将电极的线性 RC 模型作为问题的一阶近似。为了帮助标准化对刺激伪影及其影响因素的研究，我们在区分多种可能的伪影来源的同时提供我们的定义。

A. Artifact Origin A. 文物来源

The stimulation artifact is a direct consequence of the accumulated charge in the electrode–electrolyte interface during stimulation and of the effect that this charge has on the signal-chain filters and other elements after stimulation [25]. The problem is one of relative scales: stimulation signals are on the order of hundreds of millivolts, while recorded signals are on the order of tens of microvolts (which requires noise levels on the order of a few microvolts). Assuming that charge balancing is made part of the stimulation protocol, very small mismatches of 1% or less, which are common and acceptable in traditional circuit and analog signal processing designs, generate artifacts that would saturate the signal acquisition chain in extracellular recordings. The problem is further complicated by the redox reactions that take place at the electrode–electrolyte interface and make charge balancing difficult to accomplish. If no attempt at charge balancing is made, such saturation would be even more pronounced and longer lasting.
刺激伪迹是电极-电解质界面在刺激过程中累积电荷的直接后果，以及这种电荷在刺激后的信号链过滤器和其他元件上的影响。问题在于相对规模：刺激信号在数百毫伏的范围内，而记录信号在数十微伏的范围内（这需要噪声水平在几微伏的范围内）。假设在刺激协议中包含了电荷平衡，那么在传统电路和模拟信号处理设计中常见且可接受的 1%或更小的微小不匹配会产生伪迹，从而使细胞外记录中的信号采集链饱和。这个问题因电极-电解质界面发生的氧化还原反应而变得更加复杂，使电荷平衡难以实现。如果不尝试进行电荷平衡，那么这种饱和现象将更加明显且持续时间更长。

$Fig. 3. - IC discharge circuitry, notice that the main amplifier is part of the discharge loop and it is responsible for storing the electrode dc voltage. ${G_{{\rm m}_{\rm disch}}}$ is the transconductance (bias) of the discharge amplifier, ${G_{{\rm m}_{{ \rm f}}}}$ the transconductance (bias) of the feedback amplifier (which sets the highpass pole frequency), $R_{\rm e}$ and $C_{\rm e}$ are the equivalent electrode resistance and capacitance, ${R_{\rm S}}$ the spreading resistance, and ${v_{\rm e}}$ the electrochemical potential.$

Fig. 3. 图 3.

IC discharge circuitry, notice that the main amplifier is part of the discharge loop and it is responsible for storing the electrode dc voltage. Gmdisch is the transconductance (bias) of the discharge amplifier, Gmf the transconductance (bias) of the feedback amplifier (which sets the highpass pole frequency), Re and Ce are the equivalent electrode resistance and capacitance, RS the spreading resistance, and ve the electrochemical potential.
IC 放电电路，请注意主放大器是放电回路的一部分，它负责存储电极直流电压。 Gmdisch 是放电放大器的跨导（偏置）， Gmf 是反馈放大器的跨导（偏置）（它设定了高通极点频率）， Re 和 Ce 是等效电极电阻和电容， RS 是扩散电阻， ve 是电化学电位。

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To allow the recording of signals after stimulation, the charge on the stimulating electrode has to be dissipated to a level that allows for the normal operation of the amplification circuitry. For typical stimulation protocols, in which a residual voltage of 200 mV or more can be left in the electrode, to completely eliminate the artifact (i.e., to bring the residual voltage down to the electrode noise level) the electrode charge has to be dissipated to one part in 100 000 or better. To be able to recover the signal, with a typical signal amplification chain that would saturate at about 2 mV, the residual electrode charge has to be dissipated to one part in a hundred or better. Using the linear electrode model shown in Fig. 3 [26] and the exponential decay of the electrode charge that such a model predicts, we need to let five time constants of the electrode elapse to recover the signal; to eliminate the artifact (i.e., dissipate the charge to one part in 100 000), at least eleven time constants would have to elapse. For a 40

m platinum black extracellular electrode in an open circuit (i.e., connected only to high impedance recording circuitry), with a time constant (

ReCe

in Fig. 3) of 10ms, this can be from 50 to 110 ms. Clearly, these times are too long to enable the measurement of direct responses to stimulation; furthermore, unbalanced stimulation protocols can extend the artifact duration into the tens of seconds.
为了在刺激后允许信号的记录，刺激电极上的电荷必须被消散到允许放大电路正常运行的水平。对于典型的刺激协议，其中电极中可能残留 200 mV 或更多的电压，为了完全消除伪影（即将残留电压降至电极噪声水平），电极电荷必须被消散到十万分之一或更低。为了能够恢复信号，对于典型的信号放大链会在大约 2 mV 饱和，残留电极电荷必须被消散到百分之一或更低。使用 Fig. 3 [26] 中显示的线性电极模型和该模型预测的电极电荷的指数衰减，我们需要让电极的五个时间常数过去以恢复信号；为了消除伪影（即将电荷消散到十万分之一），至少需要经过十一时间常数。对于一个 40

m 的铂黑细胞外电极在开路中（即。仅连接到高阻抗记录电路时，时间常数为 10 毫秒（

ReCe

在 Fig. 3 ），这可以从 50 毫秒到 110 毫秒。显然，这些时间过长，无法测量对刺激的直接反应；此外，不平衡的刺激方案可能会将伪影持续时间延长到几十秒。

A way to reduce the artifact duration would be to reduce the electrode discharge time constant, which can be achieved by connecting the electrode to its poststimulation stabilization voltage through a low impedance path. Such a connection would reduce the time constant from the 10 ms of our previous example to approximately 200 μs (RSCe in Fig. 3), a 50-fold reduction. Such reduction would translate into artifacts that enter the linear range of the recording circuitry in 1 ms and an artifact that enters the noise band in 2.2 ms; durations that are commensurate to the expected neural response times. Because the electrode poststimulation voltage is not necessarily known in advance, the electrode prestimulation voltage can be used as a reasonable approximation.
减少伪影持续时间的一种方法是减少电极放电时间常数，这可以通过通过低阻抗路径将电极连接到其刺激后稳定电压来实现。这种连接会将时间常数从我们之前例子中的 10 毫秒减少到大约 200 微秒，减少了 50 倍。这种减少将使伪影在 1 毫秒内进入记录电路的线性范围，并在 2.2 毫秒内进入噪声带；这些持续时间与预期的神经反应时间相称。由于电极的刺激后电压不一定提前知道，因此电极的刺激前电压可以用作合理的近似值。

The long-lasting artifact dependencies and nonlinear processes that result from redox reactions at the electrode–electrolyte interface are not captured by the linear electrode model; the interaction of these factors with the stimulation signal would be seen as temporary changes in the linearized electrode characteristics which could translate into additional artifact problems. Although more elaborate electrode models are readily available [27], [28], the linear model is sufficient to approximate most of the artifact behavior and, because of our use of continuous feedback, the behavior of the circuitry itself [25].
由于电极-电解质界面的氧化还原反应导致的持久性伪影依赖性和非线性过程，线性电极模型无法捕捉到这些现象；这些因素与刺激信号的相互作用会表现为线性化电极特性的暂时变化，这可能会转化为额外的伪影问题。尽管更复杂的电极模型随时可用 [27] ， [28] ，但线性模型足以近似大多数伪影行为，并且由于我们使用连续反馈，电路本身的行为 [25] 。

It is worth pointing out that most existing designs attempt to cancel the artifact from the signal chain after it has been produced (the main exception being [23]). Our design seeks to eliminate the artifact from the electrode itself. Additionally, our design, by placing the electrode in a feedback loop and allowing for the continuous variation of system parameters, should be able to compensate for factors (e.g., nonlinearities in the electrode) that the existing, feed-forward, designs are not able to address.
值得指出的是，大多数现有设计试图在伪影产生后从信号链中消除它（主要例外是 [23] ）。我们的设计旨在从电极本身消除伪影。此外，我们的设计通过将电极置于反馈回路中并允许系统参数的连续变化，应该能够补偿现有前馈设计无法解决的因素（例如电极中的非线性）。

B. Artifact Duration B. 工件持续时间

Given the nature of the discharge behavior, it is not really possible to specify objectively the point at which the artifact has dissipated because some long-lasting baseline shifts might be introduced; these shifts are at least partially due to electrode nonlinearities and can vary with the electrochemical environment and the stimulation history. Requiring the remaining artifact voltage to become comparable to the recording noise level after stimulation would be overly conservative for most applications and could introduce data artifacts due to dependance on the slow components of the phenomena that we are trying to measure.
鉴于放电行为的性质，实际上不可能客观地指定工件消散的确切时间点，因为可能会引入一些长期存在的基线漂移；这些漂移至少部分是由于电极的非线性引起的，并且会随着电化学环境和刺激历史而变化。要求在刺激后剩余的工件电压与记录噪声水平相当对于大多数应用来说过于保守，并且可能会由于我们试图测量的现象的慢成分而引入数据工件。

With regard to the recording range of the system (or, more restrictively, the linear range of the recording system) we can classify stimulation artifacts as nonsaturating or saturating. As long as the signal chain (i.e., all amplifiers and other elements in the recording path) is not saturated or overly distorted, the artifact can be eliminated using signal processing methods (SALPA [29], filtering, etc.). Such processing would be required before postprocessing algorithms, such as spike detection or spike sorting, can be applied to the signal. If the signal chain saturates, any signal present in that interval is lost and no amount of signal processing will be able to recover it, this saturating artifact, is what must be eliminated or at least reduced as much as possible. This saturating artifact is what traditionally makes recording impossible for tens or hundreds of milliseconds after stimulation.
关于系统的记录范围（或者更严格地说，记录系统的线性范围），我们可以将刺激伪影分类为非饱和或饱和。只要信号链（即记录路径中的所有放大器和其他元件）没有饱和或过度失真，就可以使用信号处理方法（SALPA [29] ，过滤等）来消除伪影。在应用诸如尖峰检测或尖峰分类等后处理算法之前，需要进行这样的处理。如果信号链饱和，任何存在于该时间间隔内的信号都将丢失，任何信号处理都无法恢复它，这种饱和伪影是必须消除或至少尽可能减少的。正是这种饱和伪影，传统上使得在刺激后几十或几百毫秒内的记录变得不可能。

To be able to make the distinction between nonsaturating and saturating stimulation artifacts, the whole signal chain must be taken into account; gains, filters, amplifiers, digital converter resolution, and all voltage ranges have to be considered (which will be different for each system and setup). Given typical resolutions and extracellular signal magnitudes for MEAs, ranges of approximately 2 mV are common. For the purpose of this paper, we chose to define artifact duration as the time from the end of stimulation to the time that the recording system returns to within 200 μV of the electrode voltage before stimulation. Although this value is a poor choice in terms of promoting our technology, such conservative threshold allows for a direct comparison between very different systems; and it enables a signal to be observed, without any additional processing, on top of the remaining artifact.
为了能够区分非饱和和饱和的刺激伪影，必须考虑整个信号链；增益、滤波器、放大器、数字转换器分辨率和所有电压范围都必须考虑（每个系统和设置会有所不同）。考虑到 MEA 的典型分辨率和细胞外信号幅度，大约 2 mV 的范围是常见的。为了本文的目的，我们选择将伪影持续时间定义为从刺激结束到记录系统恢复到刺激前电极电压的 200 μV 以内的时间。尽管这个值在推广我们的技术方面并不是一个好的选择，这样保守的阈值允许在非常不同的系统之间进行直接比较；并且它使得信号可以在剩余的伪影之上被观察到，而无需任何额外的处理。

C. Artifacts Resulting From Circuit Effects
C. 由于电路效应产生的伪影

Although the primary cause of stimulation artifacts is the charge stored in the electrode, the artifact can be aggravated by effects from the intervening circuitry. These effects are generally avoidable through careful circuit design and layout. Here we highlight how our system deals with circuit effects.
尽管刺激伪影的主要原因是电极中存储的电荷，干扰电路的影响也会加重伪影。这些影响通常可以通过精心的电路设计和布局来避免。在这里，我们重点介绍了我们的系统如何处理电路效应。

1. DC Rejection Passband 1. 直流抑制通带

Among the circuit effects, the highpass characteristics of the dc rejection filters in the recording circuitry can be the largest contributors to the stimulation artifact. When the system returns to recording mode, the transition caused by the stimulation-induced electrode offsets (and other offsets) will excite such filters. This voltage step can generate long-lasting and large magnitude effects. The best way to avoid this problem is to eliminate the charge-induced offset, before the signal reaches the filters in the recording path; this approach, however, is not always possible or convenient. An alternative is to use first order high pass elements and the highest highpass frequency acceptable for the application (which restricts the duration of such effects). Satisfying the conflicting requirements of signal bandwidth and artifact reduction can lead to undesirable compromises; we have avoided this tradeoff by varying the filter poles during artifact elimination (see Section III-D).
在电路效应中，记录电路中的直流抑制滤波器的高通特性可能是刺激伪影的最大贡献者。当系统返回到记录模式时，由刺激引起的电极偏移（及其他偏移）引起的转换会激发这些滤波器。这个电压阶跃会产生持久且幅度大的效应。避免此问题的最佳方法是在信号到达记录路径中的滤波器之前消除电荷引起的偏移；然而，这种方法并不总是可能或方便的。另一种方法是使用一阶高通元件和应用中可接受的最高高通频率（这限制了此类效应的持续时间）。满足信号带宽和伪影减少的冲突要求可能导致不理想的妥协；我们通过在伪影消除过程中改变滤波器极点来避免这种权衡（参见 Section III-D ）。

2. Charge Injection 2. 电荷注入

Many early artifact suppression schemes were hampered by switching element charge injection [30], which is magnified by the required amplifier sensitivity. To reduce some of these effects, some designers amplify and limit the signal before introducing switching elements, thus limiting the introduced transients (e.g., the MCS MEA1060-BC preamplifiers and [23]). Our designs avoid this problem altogether by making all charge injection paths into common mode current bias paths [15]; that way, the existing common mode attenuation of differential amplifiers and the low impedance of the involved nodes drastically reduce any effects due to charge injection.
许多早期的伪影抑制方案受到开关元件电荷注入的阻碍，这种现象因所需放大器的灵敏度而放大。为了减少其中一些影响，一些设计师在引入开关元件之前对信号进行放大和限制，从而限制引入的瞬态（例如，MCS MEA1060-BC 前置放大器等）。我们的设计完全避免了这个问题，通过将所有电荷注入路径变为共模电流偏置路径；这样，差分放大器的现有共模衰减和相关节点的低阻抗大大减少了由于电荷注入引起的任何影响。

3. Circuit Mismatch 3. 电路不匹配

If we dynamically insert and remove elements from the signal path, or actively modify the characteristics of the elements themselves, any common-mode mismatch problem will cause transients on element switching. In our own design, due to the extremely low biases required, changing the highpass filter cutoff frequency introduces a mismatch transient that is a function of the filter's bias currents. The same is true for the interaction of the discharge path bias current with the electrode impedance and the remaining electrode charge. These mismatches can cause transients which might look similar to those generated by charge injection. A time-consuming circuitry redesign will inevitably face diminishing returns as such mismatches would be unavoidable without additional offset trimming [31] and it is physically impossible to alter the electrode discharge path interaction. Slowly changing any variable that is known to induce mismatch-related artifacts provides an alternative to reduce the transients caused by these phenomena. Our current firmware implementation can make use of this technique for the discharge path current.
如果我们动态地在信号路径中插入和移除元件，或者主动修改元件自身的特性，任何共模失配问题都会在元件切换时引起瞬态。在我们自己的设计中，由于需要极低的偏置，改变高通滤波器的截止频率会引入一个与滤波器偏置电流有关的失配瞬态。同样，放电路径偏置电流与电极阻抗和剩余电极电荷的相互作用也会如此。这些失配会引起类似于电荷注入产生的瞬态。一个耗时的电路重设计将不可避免地面临收益递减的问题，因为在没有额外的偏移调整的情况下，这种失配是不可避免的，并且在物理上不可能改变电极放电路径的相互作用。缓慢改变任何已知会引起失配相关伪影的变量提供了一种减少这些现象引起的瞬态的替代方法。我们当前的固件实现可以利用这一技术来处理放电路径电流。

4. Crosstalk 串扰

In any system with multiple channels in close proximity, signals can interfere with each other, a phenomenon known as crosstalk, signal coupling, or feed-through, depending on context. In a mixed-mode system (analog and digital), or in other systems in which large magnitude signals are present alongside small signals and amplification elements, the crosstalk problem can become more severe. For example, stimulation signals due to their large magnitude can introduce crosstalk into adjacent channels. This effect can be reduced through careful layout techniques or by adding design elements to increase the electrical separation between signals. Although our system can reduce external coupling to recording channels by providing a low-impedance path during stimulation, our current design has some layout oversights that introduce additional crosstalk problems (see Section V-A.3 and Fig. 15).
在任何具有多个相邻通道的系统中，信号之间会发生干扰，这种现象在不同的上下文中被称为串扰、信号耦合或馈通。在混合模式系统（模拟和数字）中，或者在存在大幅度信号和小信号以及放大元件的其他系统中，串扰问题可能会变得更加严重。例如，由于其大幅度，刺激信号可能会对相邻通道引入串扰。可以通过仔细的布局技术或添加设计元素以增加信号之间的电气隔离来减少这种效应。尽管我们的系统可以通过在刺激期间提供低阻抗路径来减少外部耦合到记录通道，但我们当前的设计存在一些布局上的疏忽，导致了额外的串扰问题（参见 Section V-A.3 和 Fig. 15 ）。

SECTION III. 第三节

IC Design 集成电路设计

Table I Main Changes to IC Specifications From Those of [15]
表 I 与文献[15]相比的 IC 规格主要变化

Table - Main Changes to IC Specifications From Those of [15]

$Fig. 4. - Equivalent discharge circuitry disregarding the frequency response and saturation characteristics of the amplifiers. $\mathhat{v}_{{\rm e}}$ is the lowpass estimate of the electrochemical potential, and ${R_{\rm f}} = ({1}/{G_{{ \rm m}_{\rm f}}})$ allows the tuning of the dc-blocking frequency.$

Fig. 4. 图 4.

Equivalent discharge circuitry disregarding the frequency response and saturation characteristics of the amplifiers. v^e is the lowpass estimate of the electrochemical potential, and Rf=(1/Gmf) allows the tuning of the dc-blocking frequency.
等效放电电路不考虑放大器的频率响应和饱和特性。 v^e 是电化学势的低通估计， Rf=(1/Gmf) 允许调节直流阻断频率。

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The focus of this paper is on the design of the system built around our second generation 16 channel stimulation, artifact elimination, and recording IC and the evaluation of the system for its intended biological application. Most of the details of the design of the IC have been presented previously [15], the main design changes can be seen in Table I. In this section, we highlight the improvements with respect to the previous design and expand on details that are relevant to this work.
本文的重点是围绕我们的第二代 16 通道刺激、伪影消除和记录 IC 设计的系统及其在预期生物应用中的评估。有关 IC 设计的大部分细节已在先前的文献中介绍过 [15] ，主要的设计变化可以在 Table I 中看到。在本节中，我们强调了相对于先前设计的改进，并扩展了与本工作相关的细节。

A. Artifact Elimination A. 消除伪影

The artifact elimination circuitry was described previously [15]; for ease of reference we reproduce the circuitry during the discharge phase in Fig. 3, and an equivalent circuit model (valid for most of the discharge when the circuitry is out of saturation) can be seen in Fig. 4. As the equivalent model indicates, and given the subthreshold circuit elements, the discharge phase is roughly equivalent to connecting the electrode, through a controllable resistor given by

R d i s c h \approx 1 A V G m d i s c h = U T A V I d i s c h \approx 26 m V 200 I d i s c h (1)

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to the prestimulation average electrode dc voltage

(AV=200

is the main amplifier gain and

UT≈26

mV is the thermal voltage). With a maximum discharge current of approximately 100

A, the minimum

Rdisch

will be on the order of 1.5

. From this circuit, and assuming polarizable electrodes for which

Re≫RS

, it can be shown that the discharge phase will have a time constant on the order of

(RS+Rdisch)×Ce

. With this equivalent circuit, for the electrode capacitance to discharge from

VCe0

—the electrode voltage at the end of stimulation—to a level of

VCed

—either inside recording range or any other arbitrary level—it will take

t d i s c h \approx (R S + R d i s c h) C e \times ln (V C e 0 V C e d) . (2)

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With this linear model, a 220 mV residual voltage in

will take ten time constants to discharge to 10

V. A similar equation describes the discharge time for an open electrode; in this case, the time constant becomes approximately

Re×Ce

, which in general can be two or more orders of magnitude longer than the one allowed by our circuitry.
伪影消除电路之前已描述过 [15] ；为了便于参考，我们在 Fig. 3 中重现了放电阶段的电路，并且在 Fig. 4 中可以看到一个等效电路模型（在电路未饱和的大部分放电期间有效）。如等效模型所示，考虑到亚阈值电路元件，放电阶段大致相当于通过

R d i s c h \approx 1 A V G m d i s c h = U T A V I d i s c h \approx 26 m V 200 I d i s c h (1)

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给定的可控电阻将电极连接到预刺激平均电极直流电压

(AV=200

是主放大器增益，

UT≈26

mV 是热电压）。最大放电电流约为 100

A，最小

Rdisch

将约为 1.5

。从这个电路，并假设

Re≫RS

的极化电极，可以证明放电阶段的时间常数约为

(RS+Rdisch)×Ce

。根据该等效电路，电极电容从

VCe0

（刺激结束时的电极电压）放电到

VCed

（在记录范围内或任何其他任意水平）需要

t d i s c h \approx (R S + R d i s c h) C e \times ln (V C e 0 V C e d) . (2)

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。根据该线性模型，

中的 220 mV 残余电压将需要十个时间常数放电到 10

V。类似的方程描述了开放电极的放电时间；在这种情况下，时间常数大约为

Re×Ce

，通常比我们电路允许的时间常数长两个或更多数量级。

Keep in mind that, besides a dependency on the involved ionic species and concentrations, RS is inversely proportional to the electrode geometrical area while Re and Ce depend on the active electrode surface area and material [28]. Therefore, all these factors will be dependent on the specific electrode and electrode conditions. Given the above, every electrode will have its own artifact characteristics, even more so if we consider the many time variant, nonlinear, and stochastic effects brought about by surface interactions with ionic species.
请记住，除了依赖所涉及的离子种类和浓度外， RS 还与电极的几何面积成反比，而 Re 和 Ce 则依赖于活性电极的表面积和材料 [28] 。因此，所有这些因素都将取决于特定的电极和电极条件。鉴于上述情况，每个电极都会有其自身的伪影特征，尤其是如果我们考虑到表面与离子种类相互作用所带来的许多时变、非线性和随机效应。

We can see from the equivalent circuit of Fig. 4 that Re, RS, and Rdisch constitute a voltage divider for the charge remaining in the electrode capacitance (Ce). As Rdisch depends on the discharge current (Idisch) through (1), if the electrode capacitance (Ce) is not fully discharged, any changes on the discharge current will cause a voltage transition at the input of the amplifier. To reduce this effect, the system firmware was designed to follow a parameterized discharge curve that guarantees that at the end of the transition the discharge amplifier bias current temporal derivative, and thus the discharge impedance derivative, is zero (∂Idisch/∂t=0→∂Rdisch/∂t=0). The firmware thus implements two sets of discharge phases joined by such smooth transition.
从 Fig. 4 的等效电路中可以看出， Re, 、 RS 和 Rdisch 构成了电极电容 (Ce) 中剩余电荷的分压器。由于 Rdisch 取决于通过 (1) 的放电电流 (Idisch) ，如果电极电容 (Ce) 没有完全放电，任何放电电流的变化都会在放大器输入端引起电压过渡。为了减少这种影响，系统固件设计了一个参数化的放电曲线，确保在过渡结束时，放电放大器偏置电流的时间导数以及放电阻抗的导数为零 (∂Idisch/∂t=0→∂Rdisch/∂t=0) 。因此，固件实现了由这种平滑过渡连接的两组放电阶段。

B. Stimulation Buffer B. 刺激缓冲液

The stimulation buffer, presented previously [15], had a significant current limitation due to its bias network. The biasing complexities of the circuit and the operating range of the design prompted us to simplify the circuitry (allowing for additional functionality). The new stimulator (Fig. 5) is a simple operational transconductance amplifier (OTA) in a follower configuration in which input signals and bias currents are switched between stimulation levels. This configuration allows for the application of an arbitrary externally generated stimulation waveform or for the use of current stimulation under some bias and electrode conditions (if the OTA's inputs differ by more than approximately 100 mV, it would behave as a constant current source). This circuitry can provide close to 100 μA on a ±1V stimulus, which is more than enough for most cell-culture MEA applications [32]. The stimulation voltage, and ultimately the stimulation current for a given electrode impedance, is limited by the IC supply, which is of ±1.65 V for the 0.35-μm TSMC IC technology used.
先前介绍的刺激缓冲液 [15] 由于其偏置网络存在显著的电流限制。电路的偏置复杂性和设计的操作范围促使我们简化电路（以增加功能）。新的刺激器（ Fig. 5 ）是一个简单的跟随器配置的运算跨导放大器（OTA），其中输入信号和偏置电流在刺激水平之间切换。这种配置允许应用任意外部生成的刺激波形或在某些偏置和电极条件下使用电流刺激（如果 OTA 的输入差异超过约 100 mV，它将表现为恒定电流源）。该电路可以在 ±1 V 刺激下提供接近 100 μ A 的电流，这对于大多数细胞培养 MEA 应用来说已经足够。刺激电压，以及最终给定电极阻抗的刺激电流，由 IC 供电限制，该供电为使用的 0.35- μ m TSMC IC 技术的 ± 1.65 V。

C. Recording Noise

Fig. 5.

Re-designed stimulation buffer. Note that it provides two different maximum currents depending on the stimulation phase input. The graph shows the use of the current adjustment feature on an MCS reference RC electrode.
重新设计的刺激缓冲液。请注意，它根据刺激相位输入提供两种不同的最大电流。图表显示了在 MCS 参考 RC 电极上使用电流调节功能。

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As reported in [15], the noise level of our previous design was larger than expected; furthermore, subsequent evaluation revealed that the design noise specifications had to be further reduced. To overcome this problem without greatly increasing the amplifier size (or a risky redesign), a simple solution was carried out, which implied an increase of the voltage gain of the recording amplifier to 200 (from 50) by increasing its input capacitance

(CI)

by a factor of four, and increasing its bias current by a factor of two. Both of which, by the relation [15, eq. (8)]

v 2 n i ¯ ¯ ¯ ¯ ¯ ¯ = ( C F + C I ) 2 C I 2 16 k T 3 g m (3 kHz - 30 H z) + C F C I 2 32 k T 6 π [f H P f H P + 30 H z - f H P f H P + 3 kHz] . (3)

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should reduce the overall noise by a factor of four. To accommodate such an increase in gain without affecting the amplifier bandwidth, we had to add an output buffer to each stage (following the design in Manetakis [33]), which due to its 6 dB loss reduced the overall IC gain to 100. This addition introduced some crosstalk that reduced the performance of adjacent channels, probably due to power supply coupling.

D. Pole Shifting D. 极移

Given that part of the stimulation artifact is due to the filter response of the recording circuitry, a recent work by DeMichele and Troyk [21] and some testing with our previous generation IC suggest the implementation of a temporary recording bandwidth modification, or pole shifting—that is, increasing the recording highpass pole in the stimulating channel to increase the recovery speed of the amplifiers. Given that we have dynamic control over the highpass pole of our main amplifier (through Gmf), a separate bias path can be used to selectively alter recovery speed. By adding three transistors in the bias branch of the feedback amplifier, and one additional control bit and bias input, we can increase the highpass poles only of selected channels. The firmware makes use of this feature by adding a set of pole shifting phases after the discharge phases.
鉴于部分刺激伪影是由于记录电路的滤波响应造成的，DeMichele 和 Troyk 最近的研究 [21] 以及我们上一代 IC 的一些测试表明，可以实施临时记录带宽修改或极点移动，即增加刺激通道中的记录高通极点以提高放大器的恢复速度。鉴于我们可以动态控制主放大器的高通极点（通过 Gmf) ，可以使用单独的偏置路径选择性地改变恢复速度。通过在反馈放大器的偏置支路中增加三个晶体管，以及一个额外的控制位和偏置输入，我们可以仅增加选定通道的高通极点。固件通过在放电阶段后添加一组极点移动阶段来利用这一特性。

E. IC Controls E. IC 控制

As a test design, the control of the multiple digital features of the IC was implemented through simple 16-bit latched shift registers, using one bit per channel. Each one of the five digital variables has its own dedicated shift-register, namely: Amplifier activation, pole shifting, stimulation buffer activation, stimulation phase, and discharge buffer activation.
作为测试设计，IC 的多个数字功能的控制是通过简单的 16 位锁存移位寄存器实现的，每个通道使用一位。每一个五个数字变量都有自己专用的移位寄存器，即：放大器激活、极点移位、刺激缓冲器激活、刺激相位和放电缓冲器激活。

Additionally, there are eight analog values to be controlled: highpass pole frequency, highpass pole shift frequency, stimulation high and low levels, stimulation high and low currents, discharge bias current, and amplifier reference level. Several of these analog input variables include resistive dividers that serve to increase the usable resolution of the external drive voltages while keeping the internal voltage inside a reasonable range. An external resistor, in combination with internal reference circuitry, sets the main amplifier bias current (25 μA).
另外，有八个模拟值需要控制：高通极点频率、高通极点移位频率、刺激高低水平、刺激高低电流、放电偏置电流和放大器参考电平。其中一些模拟输入变量包括电阻分压器，这些分压器在保持内部电压在合理范围内的同时，增加了外部驱动电压的可用分辨率。一个外部电阻与内部参考电路结合，设置主放大器偏置电流（25 μA）。

SECTION IV. 第四节

System Design 系统设计

The test system consists of a custom board, depicted in Fig. 6, with an isolated power supply for the circuitry, a PIC microcontroller (Microchip 18LF452) running at 30 MHz, twelve 12-bit digital to analog converter (DAC) channels (three Analog Devices DAC8420 ICs with four channels each), 32 discrete operational amplifiers (eight Texas Instruments LF347 with 2% 10KΩ and 270 Ω Bourns 4816P-1 feedback resistors for a gain of 38 v/v) to buffer and further amplify the recorded signal level, and two of our custom analog VLSI ICs. The ICs and the DACs share the same 7.5-MHz serial interface (SPI/Microwire) to the microcontroller, and the board communicates with the computer through an optically isolated RS-232 serial interface running at 115 200 bits/s. On the computer a custom Matlab (Mathworks) graphical user interface, or custom Matlab functions, are used to format and send configuration information to the board or to trigger a stimulus sequence. For the system tests, the board inputs are connected directly to a multi-electrode array; the amplified outputs are connected to an analog interface card (National Instruments 6035E), which also receives triggering signals from the board. For the biological tests the analog outputs from the board are sent to a MCS A/D board, and the inputs are connected in parallel with an MCS preamplifier box (MEA 1060) to a MEA with the neural cell culture, which allows the simultaneous measurement of signals through both systems.
测试系统由一个定制板组成，如 Fig. 6 所示，电路具有隔离电源，运行在 30 MHz 的 PIC 微控制器（Microchip 18LF452），十二个 12 位数字到模拟转换器（DAC）通道（三个 Analog Devices DAC8420 IC，每个有四个通道），32 个离散运算放大器（八个德州仪器 LF347，带有 2% 10K Ω 和 270 Ω Bourns 4816P-1 反馈电阻，增益为 38 v/v）用于缓冲和进一步放大记录的信号电平，以及两个我们定制的模拟 VLSI IC。IC 和 DAC 共享相同的 7.5 MHz 串行接口（SPI/Microwire）与微控制器连接，板通过光隔离的 RS-232 串行接口与计算机通信，速率为 115 200 bits/s。在计算机上，使用定制的 Matlab（Mathworks）图形用户界面或定制的 Matlab 函数来格式化并发送配置信息到板或触发刺激序列。对于系统测试，电路板输入直接连接到多电极阵列；放大后的输出连接到模拟接口卡（National Instruments 6035E），该卡还接收来自电路板的触发信号。对于生物测试，电路板的模拟输出被发送到 MCS A/D 板，输入与 MCS 前置放大器盒（MEA 1060）并联连接到带有神经细胞培养的 MEA，这允许通过两个系统同时测量信号。

The microcontroller firmware is programmed to sequence the signals for the ICs, so that the different biases are present, and the required circuit elements are turned on and off in the different recording, stimulation, and discharge phases. Switching in between phases can take 40 μs or less, depending on the number of signals to be changed and other firmware requirements. The overall timing resolution and jitter of the system is on the order of 600 ns or less, though the interface requirements restricts timing to 10 μs increments (firmware calibration constants are used to compensate for most delays). An additional optically isolated trigger input to the microcontroller can be used to start a stimulation sequence. The above system timing limitations are caused by our current choice of interface (both to the firmware and to the IC). Future implementations can eliminate all of these limitations by firmware modifications, the use of dedicated custom digital hardware, and ultimately by redesigning the IC digital interface.
微控制器固件被编程为对 IC 的信号进行排序，以便存在不同的偏置，并且在不同的记录、刺激和放电阶段中所需的电路元件被打开和关闭。阶段之间的切换可以在 40 微秒或更短的时间内完成，具体取决于需要更改的信号数量和其他固件要求。系统的整体时间分辨率和抖动在 600 纳秒或更少的范围内，尽管接口要求将时间限制为 10 微秒的增量（固件校准常数用于补偿大多数延迟）。微控制器的附加光隔离触发输入可用于启动刺激序列。上述系统时间限制是由我们当前选择的接口（包括固件和 IC 接口）引起的。未来的实现可以通过固件修改、使用专用定制数字硬件，最终通过重新设计 IC 数字接口来消除所有这些限制。

SECTION V. 第五节。

Results 结果

Fig. 6. - High-level system schematic. The board includes two of our VLSI ICs and additional interfacing circuitry. For most tests only the channels under consideration were connected to data acquisition hardware.

Fig. 6. 图 6.

High-level system schematic. The board includes two of our VLSI ICs and additional interfacing circuitry. For most tests only the channels under consideration were connected to data acquisition hardware.
高级系统示意图。该电路板包括两个我们的大规模集成电路（VLSI IC）和额外的接口电路。在大多数测试中，只有所考虑的通道连接到数据采集硬件。

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We have characterized the artifact elimination system, and demonstrated the validity of the custom aVLSI circuitry and its ancillary board in a real neural stimulation and recording application. As artifact elimination performance is the main distinguishing feature of this work, we have concentrated our efforts on evaluating this aspect of our design and methods (although, for completeness, we start this section with some basic amplifier characterization data).
我们已经描述了伪影消除系统，并在实际的神经刺激和记录应用中证明了定制 aVLSI 电路及其辅助板的有效性。由于伪影消除性能是本研究的主要特点，我们将重点放在评估设计和方法的这一方面（尽管为了完整性，我们在本节开始时提供了一些基本的放大器特性数据）。

A. IC Characterization A. IC 特性表征

To characterize the performance of the IC recording path, a Stanford Research Systems SR785 dynamic signal analyzer was successively connected to each channel under identical bias conditions, and the whole board gain, bandwidth and noise characteristics were measured in all 16 of the IC channels.
为了表征 IC 记录路径的性能，斯坦福研究系统 SR785 动态信号分析仪在相同偏置条件下依次连接到每个通道，并测量了所有 16 个 IC 通道的整个板增益、带宽和噪声特性。

1. Channel Uniformity 1. 渠道均匀性

In Fig. 7, the average response for a highpass filter setting of 10 Hz shows that at 500 Hz, an average gain of 3195, with a standard deviation of 26, was obtained (that is, 70 ±0.07 dB), with a flatness of ±0.5 dB in the 100 Hz–1 kHz range. The average lowpass cutoff for all 16 channels was 3348Hz, with a standard deviation of 80 Hz. Although no specific effort was placed into matching the different channels, these results highlight the advantages of a monolithic construction. Note, however, the high variance in the highpass poles of the different channels; such variance could be partially due to the extremely low bias currents that are being used in this filter stage (on the order of 1 fA), which are comparable to leakage currents in the circuitry. The fact that the variance appears constant in a logarithmic scale at different filter settings (σ=4 Hz at 10 Hz and σ=50 Hz at 100 Hz), however, suggests a mismatch in the bias circuitry of the filter amplifiers. Because this part of the design was mainly intended for dc rejection and in many of our experiments we filter downstream with a highpass filter at 200Hz, this effect is not problematic for our current application.
在 Fig. 7 ，高通滤波器设置为 10 Hz 的平均响应显示，在 500 Hz 时获得了 3195 的平均增益，标准偏差为 26（即 70 ± 0.07 dB），在 100 Hz 至 1 kHz 范围内平坦度为 ± 0.5 dB。所有 16 个通道的平均低通截止频率为 3348 Hz，标准偏差为 80 Hz。尽管没有特别努力匹配不同通道，这些结果突显了单片结构的优势。然而请注意，不同通道的高通极点存在较高的方差；这种方差可能部分归因于该滤波器级使用的极低偏置电流（约为 1 fA），这与电路中的漏电流相当。然而，方差在不同滤波器设置的对数刻度上表现出恒定性（ σ=4 Hz 在 10 Hz 和 σ=50 Hz 在 100 Hz），这表明滤波器放大器的偏置电路存在不匹配现象。由于这一部分的设计主要是为了直流抑制，并且在我们的许多实验中，我们在下游用 200Hz 的高通滤波器进行滤波，这种效应对我们当前的应用没有问题。

2. Input Referred Noise 2. 输入参考噪声

From Fig. 8, we can see that for a functional highpass setting of 10 Hz, the RMS noise in the 200Hz–3 kHz bandwidth of interest is of 3.0 μV (σ=1.28μV), which is lower than our previous IC (by 1.4 μV). Additionally, the noise dependance on the bandwidth of the amplifier was reduced with respect to that of [15]. Although the noise level is part of the design decision that seeks to develop the smallest reasonable IC implementation and the lowest bias currents, the noise is still larger than expected and the noise reduction is smaller than expected. A likely source of the extra noise is the output buffer coupled with low power supply rejection in the preamplifiers, but at this point we cannot discard the influence of other circuit elements (e.g., pad protection diodes, stimulation buffer, discharge amplifier, or 1/f noise in the feedback path or the main amplifier).
从 Fig. 8 ，我们可以看到，对于 10 Hz 的高通滤波设置，感兴趣的 200Hz–3 kHz 带宽内的 RMS 噪声为 3.0 μ V (σ=1.28μ V），这比我们之前的 IC 低 1.4 μ V。此外，与 [15] 相比，放大器带宽对噪声的依赖性也有所降低。尽管噪声水平是设计决策的一部分，旨在开发最小合理的 IC 实现和最低偏置电流，但噪声仍然大于预期，噪声减小也小于预期。额外噪声的可能来源是输出缓冲与前置放大器中较低的电源抑制，但目前我们不能排除其他电路元件（例如，焊盘保护二极管、刺激缓冲器、放电放大器或反馈路径或主放大器中的 1/f 噪声）的影响。

$Fig. 7. - Gain and bandwidth matching for the 16 recording channels in an IC at highpass pole settings of 10 and 100 Hz. The dark traces show the average transfer function with dashed lines that represent $\pm 1 \sigma$ from the mean, the light traces are the 16 individual channel responses.$

Fig. 7. 图 7。

Gain and bandwidth matching for the 16 recording channels in an IC at highpass pole settings of 10 and 100 Hz. The dark traces show the average transfer function with dashed lines that represent ±1σ from the mean, the light traces are the 16 individual channel responses.
在高通极点设置为 10 和 100 Hz 时，IC 中 16 个记录通道的增益和带宽匹配。深色曲线显示平均传递函数，虚线表示与平均值的 ±1σ ，浅色曲线为 16 个单独通道的响应。

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$Fig. 8. - Input referred noise of the 16 recording channels in the IC for a 10 Hz and a 100 Hz filter setting. The dark traces show the average noise density of all channels with the dashed lines representing ${+}1 \sigma$ from the mean, the light traces are the individual channel noise. The gray region is the frequency band for which the RMS noise values were calculated. (RMS noise values had $\sigma = 1.28\,\mu$V at a 10 Hz highpass and $\sigma = 1.22\,\mu$V at 100 Hz).$

Fig. 8. 图 8.

Input referred noise of the 16 recording channels in the IC for a 10 Hz and a 100 Hz filter setting. The dark traces show the average noise density of all channels with the dashed lines representing +1σ from the mean, the light traces are the individual channel noise. The gray region is the frequency band for which the RMS noise values were calculated. (RMS noise values had σ=1.28μV at a 10 Hz highpass and σ=1.22μV at 100 Hz).
输入提到 IC 中 16 个记录通道在 10 Hz 和 100 Hz 滤波器设置下的噪声。深色轨迹显示所有通道的平均噪声密度，虚线代表从均值 +1σ ，浅色轨迹是各个通道的噪声。灰色区域是计算 RMS 噪声值的频带。（在 10 Hz 高通滤波下 RMS 噪声值为 σ=1.28μ V，在 100 Hz 下为 σ=1.22μ V）。

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According to specifications, our noise is still three times that of the MCS MEA-1060 amplifier. To evaluate our noise figure, we compared our IC to the MEA-1060 connected to an active MEA under the same conditions and recording information from the same culture (see Section V-C.1). Defining SNR as peak recorded neural spike value divided by the RMS noise of the channel and averaging across 6 active electrode channels, we found that the MCS amplifier provided an SNR of 12.8 (σ=3.0), while our system one of 8.7 (σ=1.4). That is, in our particular experimental setting, our SNR is comparable to that of the MCS amplifier (approximately 3 dB worse), as a significant part of the noise comes from the electrode.
根据规格，我们的噪声仍然是 MCS MEA-1060 放大器的三倍。为了评估我们的噪声系数，我们将我们的 IC 与 MEA-1060 在相同条件下连接到一个活跃的 MEA 并记录同一培养物的信息进行了比较（见 Section V-C.1 ）。将 SNR 定义为记录的神经尖峰峰值除以通道的 RMS 噪声，并对 6 个活跃电极通道取平均值，我们发现 MCS 放大器提供的 SNR 为 12.8（ σ=3.0 ），而我们的系统为 8.7（ σ=1.4 ）。也就是说，在我们的特定实验环境中，我们的 SNR 与 MCS 放大器的 SNR 相当（大约差 3 dB），因为噪声的很大一部分来自电极。

3. Crosstalk 串扰

The present IC design has some layout oversights, mostly due to the addition of output buffers, that substantially increased the crosstalk in between channels in comparison with our previous-generation IC. Such crosstalk is particularly problematic during stimulation, given that it introduces artifacts in the recording path of adjacent nonstimulating channels. Although this is only noticeable thanks to our artifact removal architecture, we reduced this problem by modifying our stimulation protocol, turning off nonstimulating channels during the presence of the largest offending signals, namely stimulation and the initial phase of electrode discharge; we also have the possibility of activating the discharge circuitry on the recording electrodes during the stimulation phase.
目前的 IC 设计存在一些布局疏漏，主要是由于增加了输出缓冲器，与我们上一代 IC 相比，这大大增加了通道之间的串扰。这种串扰在刺激过程中尤其成问题，因为它在相邻的非刺激通道的记录路径中引入了伪影。尽管这仅仅是由于我们的伪影去除架构才得以察觉，但我们通过修改刺激协议来减少这个问题，在存在最大干扰信号（即刺激和电极放电的初始阶段）时关闭非刺激通道；我们还可以在刺激阶段激活记录电极上的放电电路。

B. Artifact Behavior B. 器物行为

To validate the circuitry, a 40 μm ×40 μm array (Ayanda Biosystems) was plated with platinum black to a uniform impedance of 20 kΩ at 1 kHz using the aparatus described in [34]. The array was submerged in Hank's balanced salt solution, 16 of its 60 electrodes were connected to our IC, and an additional ground wire electrode was placed in the media. In all the experiments in this section, a ±500-mV, 20-μA maximum stimulation current, 200 μs per phase, positive-first, biphasic voltage stimulus was used. Unless otherwise indicated, the highpass pole of the input stage was set to 200 Hz. Artifact data were captured at a constant stimulus repetition rate of 8 Hz, and at least 25 full stimulation–cancellation cycles preceded the captured data, which, as seen in Fig. 9, was roughly enough for the fastest components of the initial electrode ‘accommodation’ transients to die out (such transients are probably due to changes in the equilibrium between reduction and oxidation of chemical species at the electrode site [35]). The artifact magnitude and polarity were a consequence of the stimulus being used and the main amplifier's 180° phase shift. Additional discharge cycles in between measurement sequences were used to avoid excessive charge accumulation (and electrode damage) for suboptimal discharge parameters. After the accommodation period (25 stimulation–cancellation cycles), five additional stimulation cycles were captured and averaged to obtain a single trace. These data capture conditions insured that, after an initial transient that is dependent on previous electrode conditions, the traces would settle with relatively small variations (and slow time constants). We have observed the artifact continue to drift in different directions, in no discernible pattern, for more than 24 h, which implies an underlying stochastic process.
为了验证电路，一个 40 μ m × 40 μ m 的阵列（Ayanda Biosystems）被镀上铂黑，使其在 1 kHz 时具有 20 k Ω 的均匀阻抗，使用 [34] 中描述的设备。阵列被浸没在 Hank's 平衡盐溶液中，其 60 个电极中的 16 个连接到我们的 IC，另一个接地线电极放置在介质中。在本节的所有实验中，使用了 ± 500 mV、20 μ A 最大刺激电流、每相 200 μ s、正向优先的双相电压刺激。除非另有说明，输入级的高通极点设置为 200 Hz。伪影数据以 8 Hz 的恒定刺激重复率捕获，并且在捕获数据之前至少进行了 25 个完整的刺激-消除循环，如 Fig. 9 所示，这大致足以使初始电极“适应”瞬态的最快分量消失（这种瞬态可能是由于电极部位化学物质的还原和氧化平衡的变化 [35] ）。伪影的大小和极性是所用刺激和主放大器 180°相移的结果。为了避免在测量序列之间的额外放电循环中积累过多的电荷（以及电极损坏），使用了次优放电参数。在适应期（25 个刺激-消除循环）之后，捕获并平均了五个额外的刺激循环，以获得单个迹线。这些数据捕获条件确保，在最初的瞬态依赖于之前电极条件之后，迹线将以相对较小的变化（和缓慢的时间常数）稳定下来。我们观察到伪影在超过 24 小时内以无可辨识的模式继续向不同方向漂移，这意味着存在一个潜在的随机过程。

$Fig. 9. - Example of the output of the recording system after a ${\pm}$500 mV, 200 $\mu$s per phase stimulation and a 2-ms discharge (not enough to eliminate the artifact). In this figure, as in all subsequent figures, ${\rm time} = 0$ indicates the end of stimulation and the beginning of electrode discharge. The main amplifier is active at ${ t}> 0$ (and off during stimulation), the discharge amplifier is active only during the discharge period. This 25 trace recording is a transient behavior at the initiation of 8 Hz periodic stimulation (darker traces happened later in time). The artifact variability can be seen to converge towards a narrow range of values. The initial spike (as the main amplifier is turned on), and the relatively flat region that follows, is due to the activity of the discharge loop. In this case, the recording system saturates at approximately 2.25 mV. The inset shows the artifact duration depending on the chosen threshold (the shading corresponds to the thresholds indicated by dashed lines in the main figure). An artifact duration threshold (ADT) of 200 $\mu$V was chosen for this work.$

Fig. 9. 图 9.

Example of the output of the recording system after a ±500 mV, 200 μs per phase stimulation and a 2-ms discharge (not enough to eliminate the artifact). In this figure, as in all subsequent figures, time=0 indicates the end of stimulation and the beginning of electrode discharge. The main amplifier is active at t>0 (and off during stimulation), the discharge amplifier is active only during the discharge period. This 25 trace recording is a transient behavior at the initiation of 8 Hz periodic stimulation (darker traces happened later in time). The artifact variability can be seen to converge towards a narrow range of values. The initial spike (as the main amplifier is turned on), and the relatively flat region that follows, is due to the activity of the discharge loop. In this case, the recording system saturates at approximately 2.25 mV. The inset shows the artifact duration depending on the chosen threshold (the shading corresponds to the thresholds indicated by dashed lines in the main figure). An artifact duration threshold (ADT) of 200 μV was chosen for this work.
这是在每相 ± 500 mV、200 μ s 刺激和 2 ms 放电（不足以消除伪影）后的记录系统输出示例。在此图中，如所有后续图中一样， time=0 表示刺激结束和电极放电的开始。主放大器在 t>0 处处于活动状态（在刺激期间关闭），放电放大器仅在放电期间处于活动状态。这 25 条记录显示了 8 Hz 周期性刺激开始时的瞬态行为（较深的痕迹发生在较晚的时间）。可以看到伪影的变异性趋向于收敛到一个狭窄的值范围。初始尖峰（主放大器开启时）和随后的相对平坦区域是由于放电回路的活动所致。在这种情况下，记录系统在约 2.25 mV 处饱和。插图显示了伪影持续时间取决于所选阈值（阴影对应于主图中虚线所示的阈值）。本工作选择了 200 μ V 的伪影持续时间阈值（ADT）。

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It is worth noting that, as a consequence of the design, the actual discharge current will be determined by the charge and voltage of the electrode itself; that said, for all discharge settings in this paper, as we use a symmetric biphasic voltage stimulus, the current to the electrode will have three phases: 1) a “precharge” (anodic) phase in which the electrode voltage is raised, thus increasing the available current for the next phase; 2) a “stimulation” (cathodic) phase in which the transition to a negative voltage generates the stimulation current in the MEA [32], which charges the electrode to a negative voltage (such symmetry in voltage causes asymmetry in current and charge); and finally, 3) a decaying anodic discharge current to drive the electrode to its resting potential, which will be present in the media and could affect neural response [35]. It is important to keep in mind that for some stimulation protocols the constraints on discharge current might impose some additional performance limitations; likewise, the use of different stimulation protocols (e.g., charge-balanced current or voltage stimulation) will improve on the reported performance.
值得注意的是，由于设计的原因，实际放电电流将由电极本身的电荷和电压决定；也就是说，对于本文中的所有放电设置，由于我们使用对称的双相电压刺激，电极的电流将有三个阶段：1）“预充电”（阳极）阶段，在此阶段电极电压升高，从而增加下一个阶段的可用电流；2）“刺激”（阴极）阶段，在此阶段过渡到负电压在 MEA 中产生刺激电流，这会使电极充电到负电压（这种电压对称性导致电流和电荷不对称）；最后，3）衰减的阳极放电电流将电极驱动到其静息电位，这将在介质中存在并可能影响神经响应。需要记住的是，对于某些刺激协议，放电电流的限制可能会带来一些额外的性能限制；同样，使用不同的刺激协议（例如，电荷平衡电流或电压刺激）将改善报告的性能。

1. Artifact Duration 1. 器物持续时间

The recording range present in Fig. 9 (≈2.25 mV above the prestimulation baseline) is a consequence of our power supply, gain, digitizer, and offset settings, but the recording ranges can be deemed arbitrary for most purposes. As we have already mentioned, for consistency we chose 200 μV as our artifact duration threshold, and the artifact duration data reflect that choice. In cases where the artifact does not exceed the artifact duration threshold, the discharge time (during which no recording is possible) will be used instead.
Fig. 9 (≈ 2.25 mV 高于刺激前基线的记录范围是我们的电源、增益、数字化器和偏移设置的结果，但对于大多数目的来说，记录范围可以被视为任意的。正如我们已经提到的，为了一致性，我们选择了 200 μ V 作为伪影持续时间阈值，伪影持续时间数据反映了这一选择。在伪影未超过伪影持续时间阈值的情况下，将使用放电时间（在此期间无法进行记录）。

To show the meaning of the measures presented in subsequent figures, the data traces in Fig. 9 are presented alongside several artifact duration measurement thresholds, and the inset shows the effect of the choice of threshold on the final measurement. Note that the relation between the voltage threshold and the artifact duration is roughly linear, and that our choice of a lower threshold imposes a penalty of two to five milliseconds over a higher threshold that accounts for the recording range.
为了显示后续图中所示措施的意义， Fig. 9 中的数据轨迹与几个伪影持续时间测量阈值一起呈现，插图显示了阈值选择对最终测量的影响。请注意，电压阈值与伪影持续时间之间的关系大致呈线性，并且我们选择较低的阈值会比考虑记录范围的较高阈值多出两到五毫秒的惩罚。

2. Discharge Current and Time
2. 放电电流和时间

For clarity, and as a consequence of our design choices, we have divided the discharge process into two discharge periods. The initial one significantly lowers the charge of the electrode, while the second one allows us to better visualize the artifact. Fig. 10 shows the effect of the initial electrode discharge on the artifact duration. At the initiation of discharge, the main amplifier is turned on, and the large electrode offset drives it (and the discharge amplifier) out of its linear range (the initial spike seen in Fig. 9). During these few microseconds the equivalent circuit in Fig. 4 will not be valid, and the discharge rate will be directly proportional to the available discharge current (Idisch). It would seem that the larger the discharge current, the smaller the artifact duration, but larger currents also cause large transients at the end of discharge as, unless the electrode is fully discharged, the input of the amplifier will see a voltage step proportional to the change in voltage divider formed by Rdisch and RS.
为了清晰起见，并作为我们设计选择的结果，我们将放电过程分为两个放电阶段。初始阶段显著降低电极的电荷，而第二阶段则使我们能够更好地观察伪影。 Fig. 10 显示了初始电极放电对伪影持续时间的影响。在放电开始时，主放大器被打开，大电极偏移将其（以及放电放大器）驱动出其线性范围（ Fig. 9 中看到的初始尖峰）。在这几微秒内， Fig. 4 中的等效电路将无效，放电速率将与可用放电电流 (Idisch) 成正比。看起来放电电流越大，伪影持续时间越短，但较大的电流也会在放电结束时引起较大的瞬变，因为除非电极完全放电，否则放大器的输入将看到一个与 Rdisch 和 RS 形成的电压分压器变化成比例的电压阶跃。

$Fig. 10. - Artifact duration with respect to discharge current and discharge time. (a) Set of time traces of artifact data after a ${\pm}$0.5 V, 200 $\mu$s per phase stimulus (current limited to 20 $\mu$A), with a discharge current of 10 $\mu$A parameterized by discharge time (from 0 to 2 ms); the arrow indicates the direction of increasing discharge time. (b) Artifact duration with respect to discharge time parameterized by discharge current (section of logarithmically spaced data set with 20 current traces from 10 to 0.1 $\mu$A). (c) 3-D representation of the whole data set from (b). Note that the undisturbed artifact duration is ${\approx} $100 ms.$

Fig. 10. 图 10.

Artifact duration with respect to discharge current and discharge time. (a) Set of time traces of artifact data after a ±0.5 V, 200 μs per phase stimulus (current limited to 20 μA), with a discharge current of 10 μA parameterized by discharge time (from 0 to 2 ms); the arrow indicates the direction of increasing discharge time. (b) Artifact duration with respect to discharge time parameterized by discharge current (section of logarithmically spaced data set with 20 current traces from 10 to 0.1 μA). (c) 3-D representation of the whole data set from (b). Note that the undisturbed artifact duration is ≈100 ms.
与放电电流和放电时间相关的伪影持续时间。 (a) 施加 0.5 V, 200 s 每相位的刺激（电流限制为 20 A），放电电流为 10 A，按放电时间参数化（从 0 到 2 毫秒）的伪影数据时间轨迹集；箭头表示放电时间增加的方向。 (b) 按放电电流参数化的放电时间与伪影持续时间（具有 20 个电流轨迹的对数间隔数据集的部分，电流从 10 到 0.1 A）。 (c) (b) 中整个数据集的 3D 表示。注意，未受干扰的伪影持续时间为 100 毫秒。

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To avoid such transients, a second discharge phase at a lower discharge current can be used to reduce overall discharge time. Fig. 11 shows the effect of the second discharge phase after the application of a 500-μs, 10-μA initial discharge. As expected from (1) and (2), the artifact duration roughly saturates for larger currents as RS dominates the discharge time constant, though the actual data shows a minimum across time, as larger discharge currents are used. Among other smaller effects, the presence of such minimum will be due to a small offset between the poststimulation electrode resting voltage and the stored average electrode voltage, which causes a voltage step at the end of discharge. Once the electrode is “reasonably” discharged, we will face diminishing returns as recording cannot take place during the discharge period.
为了避免这种瞬变，可以使用较低放电电流的第二放电阶段来减少总体放电时间。 Fig. 11 显示了在应用 500- μ s、10- μ A 初始放电后的第二放电阶段的效果。如 (1) 和 (2) 所预期的那样，当 RS 主导放电时间常数时，工件持续时间大致趋于饱和，尽管实际数据显示随着使用更大的放电电流，时间上出现了一个最小值。除了其他较小的影响外，这种最小值的存在将归因于刺激后电极静息电压和存储的平均电极电压之间的小偏移，这在放电结束时会导致电压阶跃。一旦电极“合理地”放电，我们将面临收益递减，因为在放电期间无法进行记录。

$Fig. 11. - Artifact duration after an initial discharge period of 500 $\mu$s at 10 $\mu$A. (a) Set of time traces of artifact data with a discharge current of 10 $\mu$A parameterized by discharge time, the arrow indicates the direction of increasing discharge time. (b) Artifact duration with respect to discharge time parameterized by discharge current (logarithmically spaced, 20 current traces from 10 $\mu$A to 0.1 $\mu$A). The dashed line corresponds to a higher artifact threshold of 2 mV (the sloped region is the total discharge time as the artifact does not exceed the threshold). (c) 3-D representation of the data set from (b). Note that the artifact duration slightly worsens for larger discharge currents and times.$

Fig. 11. 图 11.

Artifact duration after an initial discharge period of 500 μs at 10 μA. (a) Set of time traces of artifact data with a discharge current of 10 μA parameterized by discharge time, the arrow indicates the direction of increasing discharge time. (b) Artifact duration with respect to discharge time parameterized by discharge current (logarithmically spaced, 20 current traces from 10 μA to 0.1 μA). The dashed line corresponds to a higher artifact threshold of 2 mV (the sloped region is the total discharge time as the artifact does not exceed the threshold). (c) 3-D representation of the data set from (b). Note that the artifact duration slightly worsens for larger discharge currents and times.
在初始放电期为 500 μ 秒，电流为 10 μ 安培后的伪影持续时间。(a) 伪影数据的时间轨迹集，放电电流为 10 μ 安培，以放电时间为参数，箭头表示放电时间增加的方向。(b) 以放电电流为参数（对数间隔，从 10 μ 安培到 0.1 μ 安培的 20 个电流轨迹）的放电时间与伪影持续时间的关系。虚线对应于 2 毫伏的较高伪影阈值（斜坡区域是总放电时间，因为伪影未超过阈值）。(c) (b)中数据集的 3D 表示。注意，对于较大的放电电流和时间，伪影持续时间略有恶化。

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3. Soft Switching 3. 软切换

As large transients can affect the filter and the electrode itself, we have the option of switching smoothly between discharge values. Fig. 12 shows the effect of a smooth curve that reaches the second discharge phase with a zero time derivative (a voltage parabola distorted by the exponential voltage-to-current relationship of the bias circuitry). Note that the artifact duration has been further reduced by approximately 1 ms even though overall discharge time remains the same, the average discharge impedance is higher, and the transition at the end of discharge remains unchanged. Although we are not sure of the mechanism for such artifact reduction—and we found it while implementing a way to continue discharging the electrode during recording—we have found some evidence that the fast transients affect the electrode itself rather than the recording path (see Section V-B.5).
由于较大的瞬态会影响滤波器和电极本身，我们可以选择在放电值之间平滑切换。 Fig. 12 显示了一条平滑曲线的效果，该曲线以零时间导数达到第二个放电阶段（由偏置电路的指数电压-电流关系扭曲的电压抛物线）。请注意，即使总放电时间保持不变，平均放电阻抗更高，并且放电结束时的过渡保持不变，伪影的持续时间也减少了大约 1 毫秒。虽然我们不确定这种伪影减少的机制，并且我们是在实现一种在记录期间继续放电电极的方法时发现的，但我们发现了一些证据表明快速瞬态影响的是电极本身，而不是记录路径（见 Section V-B.5 ）。

$Fig. 12. - Example of two artifacts with (black) and without (gray) a soft transition between the high and low discharge currents. The bottom plot shows ${R_{\rm disch}}$ for each curve; both start and stop at the same values and have a total discharge time of 3.5 ms. The initial peak saturates the amplifiers though the higher currents make it too fast to be captured at this sampling rate. The gray regions denote the areas in which the corresponding amplifiers are turned off. Note that the larger overall current (smaller overall ${R_{\rm disch}}$ value) performs worse than having a smooth transition.$

Fig. 12. 图 12.

Example of two artifacts with (black) and without (gray) a soft transition between the high and low discharge currents. The bottom plot shows Rdisch for each curve; both start and stop at the same values and have a total discharge time of 3.5 ms. The initial peak saturates the amplifiers though the higher currents make it too fast to be captured at this sampling rate. The gray regions denote the areas in which the corresponding amplifiers are turned off. Note that the larger overall current (smaller overall Rdisch value) performs worse than having a smooth transition.
两个工件的示例，一个具有（黑色）和一个不具有（灰色）高低放电电流之间的软过渡。底部图显示了每条曲线的 Rdisch ；两者的起始和停止值相同，总放电时间为 3.5 毫秒。初始峰值使放大器饱和，尽管较高的电流使其过快，无法在此采样率下捕获。灰色区域表示相应的放大器关闭的区域。请注意，总体电流较大（总体 Rdisch 值较小）比具有平滑过渡的情况表现更差。

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4. Pole Shifting 4. 极移

As was made clear by the design in [21], the frequency characteristics of the amplifier itself contribute to the artifact, so a way to further reduce the artifact duration is to modify the frequency response of the main amplifier for a short time period after discharge. Fig. 13 shows this effect. Due to the way the poles are controlled in our ICs (see Section II-C.3), this method will introduce some artifacts due to switching between offset levels (no soft switching has been implemented for this path yet). As long as the bandwidth is not considerably reduced, this mode of artifact reduction has the advantage that recording can take place during the period of pole shifting (as is also true, though harder to accomplish, for the second discharge phase), but we must keep in mind that the pole shift setting affects the recording chain itself and has no direct effect on the electrode.
如 [21] 的设计所明确指出的那样，放大器本身的频率特性会导致伪影，因此进一步减少伪影持续时间的方法是，在放电后的一段时间内修改主放大器的频率响应。 Fig. 13 显示了这一效果。由于我们 IC 中的极点控制方式（见 Section II-C.3 ），该方法会在偏移电平之间切换时引入一些伪影（此路径尚未实现软切换）。只要带宽没有显著减少，这种伪影减少模式的优点是极点转移期间可以进行记录（虽然在第二次放电阶段也是如此，但更难实现），但我们必须记住，极点转移设置会影响记录链本身，对电极没有直接影响。

$Fig. 13. - Artifact duration with respect to pole shift time and frequency after a discharge period of 1 ms at 5 $\mu$A, followed by 1.5 ms at 1 $\mu$A. The pole-shift effect is additive to the recording highpass frequency of 200 Hz (the frequencies shown are actual highpass values). (a) Set of time traces of artifact data with a pole shift frequency of 800 Hz parameterized by pole shift time, the arrow indicates the direction of increasing pole shift time. (b) Artifact duration with respect to pole shift time, parameterized by pole shift frequency. (c) 3-D representation of the data set from (b).$

Fig. 13. 图 13.

Artifact duration with respect to pole shift time and frequency after a discharge period of 1 ms at 5 μA, followed by 1.5 ms at 1 μA. The pole-shift effect is additive to the recording highpass frequency of 200 Hz (the frequencies shown are actual highpass values). (a) Set of time traces of artifact data with a pole shift frequency of 800 Hz parameterized by pole shift time, the arrow indicates the direction of increasing pole shift time. (b) Artifact duration with respect to pole shift time, parameterized by pole shift frequency. (c) 3-D representation of the data set from (b).
放电时间为 1 ms，电流为 5 μ A，随后 1.5 ms，电流为 1 μ A 的情况下，工件持续时间与极点偏移时间和频率的关系。极点偏移效应与 200 Hz 的录制高通频率叠加（显示的频率为实际高通值）。(a) 极点偏移频率为 800 Hz 的工件数据时间轨迹集，以极点偏移时间参数化，箭头表示极点偏移时间增加的方向。(b) 工件持续时间与极点偏移时间的关系，以极点偏移频率参数化。(c) 来自(b)的数据集的 3D 表示。

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5. Remaining Discharge 5. 剩余放电

In Fig. 13(a), we can see an apparently exponential decay after the main artifact—which is present, though not always evident, in the other figures—this decay has roughly a 4.4-ms time constant, which is slower than any time constant on the electronics path thus pointing to the electrode as the most likely source. All the curves reach the same exponential decay, which is to be expected as pole shifting only changes the recording path and not the electrode. From Fig. 12 a time constant of 4.8 ms can be extracted (which is within measurement error from the previous value), although interestingly the soft-switch curve is roughly 12 μV below the abrupt switching curve, which strongly suggests that the electrode itself is being affected by the speed of the transition.
在 Fig. 13(a) 中，我们可以看到在主要伪影之后显然呈指数衰减——这种伪影在其他图中也存在，尽管并不总是明显的——这种衰减大约有 4.4 毫秒的时间常数，这比电子路径上的任何时间常数都要慢，因此指向电极作为最可能的来源。所有曲线都达到相同的指数衰减，这是可以预期的，因为极点移动只改变记录路径而不改变电极。从 Fig. 12 中可以提取出 4.8 毫秒的时间常数（这在测量误差范围内与前一个值一致），尽管有趣的是，软切换曲线大约比突然切换曲线低 12 μ 伏，这强烈表明电极本身受到了转换速度的影响。

Extracting time constants from the data in the other discharge curves (Figs. 10 and 11), we find that their values are not consistent, ranging from 15 down to 5 ms (and many of the traces have sign-inversion which suggests over-discharge). These measurements highlight some of the limitations of the linear model, as such variation cannot be explained with constant capacitance and resistance values. Nonetheless, the time constants are in the right order of magnitude, as required by the RC model of the electrode (approximately 10 ms). Interestingly, there seems to be a relationship between how fast the remaining artifact decays and how fast the discharge is, so that an undischarged electrode would generate not only the longest but also the slowest decaying artifact.
从其他放电曲线（ Figs. 10 和 11 ）中提取时间常数，我们发现它们的值并不一致，范围从 15 毫秒到 5 毫秒（许多曲线都有符号反转，这表明过放电）。这些测量结果突显了线性模型的一些局限性，因为这种变化不能用恒定的电容和电阻值来解释。尽管如此，这些时间常数的数量级是正确的，符合电极的 RC 模型（大约 10 毫秒）。有趣的是，剩余伪影的衰减速度与放电速度之间似乎存在某种关系，因此，未放电的电极不仅会产生最长的伪影，还会产生衰减最慢的伪影。

C. Biological Tests C. 生物测试

1. Methods 1. 方法

Dissociated E18 hippocampal neurons (Brain Bits¹) were plated on an MEA (30 μm TiN electrodes with Si3N4 insulator, MCS, Reutlingen, Germany) with serum-free Neurobasal medium (Gibco) with 2% B27 (Gibco), 0.5mM L-glutamine (Gibco), 25 μM glutamate and 0.1% penicillin-streptomycin (Sigma-Aldrich). MEAs were incubated at 37°C, 5% CO₂, and 9% O₂, and biological experiments were done at the fourth week after the plating. The MEA was connected into the rest of the system as indicated in Section IV. All animal procedures were done in accordance with approved animal use protocols at the University of Illinois.
解离的 E18 海马神经元（Brain Bits ¹ ）被接种到 MEA（30 μ m TiN 电极，Si3N4 绝缘层，MCS，德国罗伊特林根）上，培养基为无血清的 Neurobasal 培养基（Gibco），其中含有 2% B27（Gibco）、0.5mM L-谷氨酰胺（Gibco）、25 μ M 谷氨酸和 0.1%青霉素-链霉素（Sigma-Aldrich）。MEA 在 37°C、5% CO ₂ 和 9% O ₂ 条件下孵育，生物实验在接种后第四周进行。MEA 按照 Section IV 中的说明连接到系统的其余部分。所有动物实验均按照伊利诺伊大学批准的动物使用协议进行。

2. Results 2. 结果

Cultured hippocampal neurons were spontaneously active, and synchronized bursting activity could be routinely recorded through our IC. As indicated in Section V-A.2 the quality of the neural recording was comparable to the commercial preamplifier system.
培养的海马神经元自发活跃，并且可以通过我们的 IC 常规记录同步爆发活动。如 Section V-A.2 所示，神经记录的质量可与商业前置放大器系统相媲美。

Fig. 14 shows the stimulation and recording from the IC. When biphasic voltage pulses (positive–negative, 100 or 500mV) were applied, artifact-free recordings were possible after 3 ∼4 ms (or 2 ∼3 ms if we include the 700-Hz highpass region). By increasing the stimulation intensity, stimulation-induced action potentials appeared around 4 ms. The transient around 3.5 ms is mostly due to the offset step when the highpass filter setting is changed.
Fig. 14 显示了来自 IC 的刺激和记录。当施加双相电压脉冲（正负 100 或 500mV）时，3 ∼4 毫秒后（如果包括 700Hz 高通区域则为 2 ∼3 毫秒）可以进行无伪影记录。通过增加刺激强度，刺激诱发的动作电位在 4 毫秒左右出现。大约 3.5 毫秒的瞬变主要是由于改变高通滤波器设置时的偏移步引起的。

$Fig. 14. - Recordings from the stimulating electrode with a discharge time (D) of 2 ms @ 50 $\mu$A, two pole-shift phases of 1 ms @ 2200 Hz (P1) and 0.5 ms @ 700 Hz (P2). Highpass filter setting: 200 Hz. Stimuli (S) were positive-first biphasic pulses (pulsewidth 200 $\mu$s for each phase) with an amplitude of 0.1 V (bottom trace) or 0.5 V (top trace). Note the recorded responses starting 4 ms after stimulation.$

Fig. 14. 图 14.

Recordings from the stimulating electrode with a discharge time (D) of 2 ms @ 50 μA, two pole-shift phases of 1 ms @ 2200 Hz (P1) and 0.5 ms @ 700 Hz (P2). Highpass filter setting: 200 Hz. Stimuli (S) were positive-first biphasic pulses (pulsewidth 200 μs for each phase) with an amplitude of 0.1 V (bottom trace) or 0.5 V (top trace). Note the recorded responses starting 4 ms after stimulation.
来自刺激电极的记录，放电时间（D）为 2 毫秒@50 μ A，两个极移相位分别为 1 毫秒@2200 Hz（P1）和 0.5 毫秒@700 Hz（P2）。高通滤波器设置：200 Hz。刺激（S）为正向双相脉冲（每个相位的脉宽为 200 μ s），幅度为 0.1 V（底部轨迹）或 0.5 V（顶部轨迹）。注意记录的响应在刺激后 4 毫秒开始。

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$Fig. 15. - Recordings through our system with a discharge time of 2 ms @ 50 $\mu$A, two pole-shift phases of 2 ms @ 2000 Hz and 0.5 ms @ 500 Hz. Highpass filter setting: 10 Hz. Acquired data were filtered by a digital 2nd order Butterworth highpass filter with a cutoff frequency of 200 Hz. The stimuli were positive-first biphasic pulses with 200 $\mu$s per phase, at ${\pm}$0.5 V. The circles denote additional crosstalk artifacts in the IC, the arrows show time-locked action potentials.$

Fig. 15. 图 15.

Recordings through our system with a discharge time of 2 ms @ 50 μA, two pole-shift phases of 2 ms @ 2000 Hz and 0.5 ms @ 500 Hz. Highpass filter setting: 10 Hz. Acquired data were filtered by a digital 2nd order Butterworth highpass filter with a cutoff frequency of 200 Hz. The stimuli were positive-first biphasic pulses with 200 μs per phase, at ±0.5 V. The circles denote additional crosstalk artifacts in the IC, the arrows show time-locked action potentials.
通过我们的系统记录，放电时间为 2 毫秒@ 50 μ A，两个极移相位为 2 毫秒@ 2000 Hz 和 0.5 毫秒@ 500 Hz。高通滤波器设置：10 Hz。获取的数据通过截止频率为 200 Hz 的二阶巴特沃斯数字高通滤波器进行滤波。刺激是正相位双相脉冲，每相位 200 μ s，电压 ± 0.5 V。圆圈表示 IC 中的额外串扰伪影，箭头显示锁时动作电位。

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Fig. 15 demonstrates the capability of simultaneous multichannel recording and stimulation solely executed by our system. The stimulating channel (the topmost trace) recovered from the stimulation artifact as early as 4 ms and recorded diffusive time-locked responses around 10 ms. Nonstimulating channels recovered much earlier from the stimulation artifact (within 500 μs) and recorded highly time-locked action potentials at 1.2, 2.0, and 4.8 ms (the second, third, and fourth traces, respectively).
Fig. 15 展示了我们系统同时进行多通道记录和刺激的能力。刺激通道（最上面的轨迹）在刺激伪影后早至 4 毫秒恢复，并在大约 10 毫秒记录到扩散的时间锁定反应。非刺激通道在刺激伪影后更早恢复（在 500 μ 秒内）并分别在 1.2、2.0 和 4.8 毫秒（第二、第三和第四条轨迹）记录到高度时间锁定的动作电位。

Although we have made no effort in reducing the artifact in adjacent channels, our previous generation IC was able to record in less than 1 ms, without blanking such channels, after the stimulation (which compares favorably to the adjacent channel performance, with blanking, of the MEA1060BC from MCS). This IC lost some of that capability due to the introduction of crosstalk (the effects of which can be seen in Fig. 15), as the crosstalk from the remaining artifact spike shifts the baseline of the recording channels for 4 ms after stimulation; and it would produce a large stimulation artifact if the channels had not been blanked.
尽管我们没有努力减少相邻通道中的伪影，我们的上一代集成电路在刺激后不到 1 毫秒的时间内就能够记录下来，而不会空白这些通道（相比之下，MCS 的 MEA1060BC 在空白情况下的相邻通道性能）。由于引入了串扰，这款集成电路失去了一些这样的能力（其效果可见于 Fig. 15 ），因为剩余伪影尖峰的串扰在刺激后 4 毫秒内使记录通道的基线发生偏移；如果没有空白通道，它会产生一个大的刺激伪影。

SECTION VI. 第六节

Discussion 讨论

We have presented a scalable system built around a custom 16-channel IC that can stimulate and record within 3 ms of the stimulus on the stimulating channel and within 500 μs on adjacent channels. We have also demonstrated some of the capabilities of our system for neural culture applications. Our system achieves artifact elimination by directly discharging the electrode through a novel feedback scheme, and by shaping such feedback to optimize electrode behavior; that is, we prevent the problem instead of fighting the consequences. This approach represents a break from existing artifact reduction schemes, in which accumulated electrode charge is not managed thus causing what some researchers call the dish saturation effect. This effect makes recording during fast stimulation, or even fast stimulation itself, impossible. An additional benefit of our approach is the increased lifetime of the electrodes, while undischarged electrodes would show variations on their characteristics after a few hours of bipolar stimulation, the use of our artifact elimination protocol allowed us to run the same electrodes continuously for weeks at a time without any appreciable degradation.
我们提出了一个可扩展的系统，该系统围绕一个定制的 16 通道集成电路构建，可以在刺激通道的刺激后 3 毫秒内以及相邻通道在 500 微秒内进行刺激和记录。我们还展示了我们的系统在神经培养应用中的一些能力。我们的系统通过一种新颖的反馈方案直接放电电极，并通过塑造这种反馈来优化电极行为来实现伪影消除；也就是说，我们预防问题而不是对抗后果。这种方法代表了与现有的伪影减少方案的一个突破，在现有方案中，积累的电极电荷没有得到管理，从而导致一些研究人员称之为培养皿饱和效应的现象。这种效应使得在快速刺激期间甚至快速刺激本身变得不可能。我们方法的另一个好处是电极寿命的增加，而未放电的电极在双极刺激几小时后会显示出其特性的变化，使用我们的伪影消除协议使我们能够连续数周运行相同的电极而没有任何明显的退化。

The main discharge speed limitation is given by the electrode impedance characteristics [as predicted by Section III-A and (2)]; within this limitation, however, our circuitry is able to reliably control the artifact on the stimulating electrode to the point that relatively simple signal processing (e.g., averaging and subtraction or simple filtering) can obtain responses within 3 ms or less. The addition of dynamic bandwidth control further facilitates the achievement of our artifact elimination goal. We have shown how each of the characteristics of the IC interplay with the artifact, and how each of the functions can be used to tune the desired response. Furthermore, we have shown that our design directly affects the electrode by removing the artifact at the source. This effect introduces other design possibilities, such as using the system as a stand-alone stimulator, or independently optimizing the recording and artifact elimination signal paths.
主要的放电速度限制由电极阻抗特性决定 [如 Section III-A 和 (2) 所预测的]；然而，在这一限制内，我们的电路能够可靠地控制刺激电极上的伪影，以至于相对简单的信号处理（例如，平均和减法或简单滤波）可以在 3 毫秒或更短的时间内获得响应。动态带宽控制的加入进一步促进了我们消除伪影目标的实现。我们展示了 IC 的每个特性如何与伪影相互作用，以及如何使用每个功能来调整所需的响应。此外，我们还展示了我们的设计如何通过在源头上消除伪影直接影响电极。这一效果引入了其他设计可能性，例如将系统用作独立的刺激器，或独立优化记录和伪影消除信号路径。

Although we have shown conservative results, and we have not undertaken a careful optimization of our system parameters, we fully expect that better performance will be possible by modifying some of our protocols. Furthermore, given the large number of factors involved, we have strived to provide as much information as possible about the conditions under which artifact elimination is achieved; and to be as precise as possible with our definitions and terminology thus enabling any future comparisons.
尽管我们展示了保守的结果，并且没有对系统参数进行仔细优化，但我们完全相信，通过修改我们的一些协议，可以实现更好的性能。此外，考虑到涉及的因素众多，我们努力尽可能多地提供有关消除伪影所需条件的信息；并尽可能精确地定义和术语，从而使未来的任何比较成为可能。

SECTION VII. 第七节

Future Directions 未来方向

The system is now in use by ourselves and our collaborators in two different laboratories, and the elimination of electrode charge has made possible fast sequential stimulation and recording of neural signals, something that was not possible with existing commercial and custom stimulators. We have shown one example of its use in this paper and we expect other examples to follow as part of additional research. Further work in artifact modeling and characterization is also under way.
该系统目前由我们自己和我们的合作者在两个不同的实验室中使用，电极电荷的消除使得快速的连续刺激和神经信号记录成为可能，这是现有的商业和定制刺激器所无法实现的。我们在本文中展示了一个使用示例，并期望在后续研究中出现其他示例。关于伪影建模和表征的进一步工作也在进行中。

Although our system has significantly reduced the artifact duration, we are exploring ways to further improve the performance of our circuitry for the stimulating electrode as well as in the adjacent channels. Through further improvements of our technology, we expect to enable the study of the direct neural responses which have been suggested by [36] and by Fig. 15. Besides correcting some of the shortcomings that have been introduced in the design of the current IC, one such improvement is the use of a negative resistance for Rdisch to directly reduce the electrode time constant by reducing the effect of Re. Even with such modifications, we are aware that the system would only be correcting for first order electrode effects; higher order modeling, and a better understanding of the underlying processes, will become necessary to achieve the performance that we seek.
尽管我们的系统显著减少了伪影持续时间，我们正在探索进一步提高刺激电极电路性能以及相邻通道性能的方法。通过进一步改进我们的技术，我们期望能够研究由 [36] 和 Fig. 15 提出的直接神经反应。除了纠正当前 IC 设计中引入的一些缺陷之外，其中一个改进是使用负电阻 Rdisch 通过减少 Re 的影响直接降低电极时间常数。即使有这样的修改，我们也意识到系统只会纠正一阶电极效应；为了实现我们所追求的性能，更高阶的建模和对底层过程的更好理解将变得必要。

We are in the process of implementing a new IC which will incorporate several improvements in terms of noise performance, bandwidth control, better matching, faster discharge circuitry, and more control for current stimulation. This IC will also incorporate better interfacing characteristics with the full system in mind.
我们正在实施一种新的集成电路（IC），它将在噪声性能、带宽控制、更好的匹配、更快的放电电路和电流刺激的更多控制方面进行多项改进。该 IC 还将结合更好的接口特性，以适应整个系统。

ACKNOWLEDGMENT 确认

The authors would like to thank N. Reddy for the data gathering and processing that made this paper possible; S. Buscemi, K. Gosrani, and S. Das for the layout and implementation of the system and support boards; and Dr. S. Potter (Georgia Institute of Technology, Atlanta) and his group for the multiple suggestions on dealing with electrode arrays. MOSIS provided the IC fabrication for this work.
作者感谢 N. Reddy 收集和处理数据，使本文成为可能；感谢 S. Buscemi、K. Gosrani 和 S. Das 对系统和支持板的布局和实现；感谢 S. Potter 博士（亚特兰大乔治亚理工学院）及其团队对电极阵列处理的多次建议。此外，感谢 MOSIS 提供了本工作的集成电路制造。

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Stimulus-Artifact Elimination in a Multi-Electrode System多电极系统中的刺激伪影消除

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Abstract: 摘要：

ISSN Information: ISSN 信息:

Introduction 介绍

Stimulation Artifacts 刺激伪影

A. Artifact Origin A. 文物来源

B. Artifact Duration B. 工件持续时间

C. Artifacts Resulting From Circuit EffectsC. 由于电路效应产生的伪影

1. DC Rejection Passband 1. 直流抑制通带

2. Charge Injection 2. 电荷注入

3. Circuit Mismatch 3. 电路不匹配

4. Crosstalk 串扰

IC Design 集成电路设计

A. Artifact Elimination A. 消除伪影

B. Stimulation Buffer B. 刺激缓冲液

C. Recording Noise

D. Pole Shifting D. 极移

E. IC Controls E. IC 控制

System Design 系统设计

Results 结果

A. IC Characterization A. IC 特性表征

1. Channel Uniformity 1. 渠道均匀性

2. Input Referred Noise 2. 输入参考噪声

3. Crosstalk 串扰

B. Artifact Behavior B. 器物行为

1. Artifact Duration 1. 器物持续时间

2. Discharge Current and Time2. 放电电流和时间

3. Soft Switching 3. 软切换

4. Pole Shifting 4. 极移

5. Remaining Discharge 5. 剩余放电

C. Biological Tests C. 生物测试

1. Methods 1. 方法

2. Results 2. 结果

Discussion 讨论

Future Directions 未来方向

ACKNOWLEDGMENT 确认

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Stimulus-Artifact Elimination in a Multi-Electrode System
多电极系统中的刺激伪影消除

C. Artifacts Resulting From Circuit Effects
C. 由于电路效应产生的伪影

2. Discharge Current and Time
2. 放电电流和时间