Version 2.0 Specification for D-PHY
23-Nov-2015
144 Mbps Megabits per second
145 MSB Most Significant Bit
146 PHY Physical Layer
147 PLL Phase-Locked Loop
148 PPI PHY-Protocol Interface
149 RF Radio Frequency
150 RX Receiver
151 SE Single-Ended
152 SoT Start of Transmission
153 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master
154 and Slave
155 TX Transmitter
156 UI Unit Interval, equal to the duration of any HS state on the Clock Lane
157 ULPS Ultra-Low Power State| | Version 2.0 | Specification for D-PHY |
| :--- | :--- | :--- |
| | 23-Nov-2015 | |
| 144 | Mbps | Megabits per second |
| 145 | MSB | Most Significant Bit |
| 146 | PHY | Physical Layer |
| 147 | PLL | Phase-Locked Loop |
| 148 | PPI | PHY-Protocol Interface |
| 149 | RF | Radio Frequency |
| 150 | RX | Receiver |
| 151 | SE | Single-Ended |
| 152 | SoT | Start of Transmission |
| 153 | TLIS | Transmission-Line Interconnect Structure: physical interconnect realization between Master |
| 154 | | and Slave |
| 155 | TX | Transmitter |
| 156 | UI | Unit Interval, equal to the duration of any HS state on the Clock Lane |
| 157 | ULPS | Ultra-Low Power State |
Lane
Interconnect Side| Lane |
| :--- |
| Interconnect Side |
高速能力
前進方向逃脫模式支援的功能
Forward
Direction Escape Mode Features Supported| Forward |
| :--- |
| Direction Escape Mode Features Supported |
反向方向逃逸模式支持的功能 ^(1){ }^{1}
Reverse
Direction Escape
Mode Features Supported ^(1)| Reverse |
| :--- |
| Direction Escape |
| Mode Features Supported ${ }^{1}$ |
CIL-
M - 主控 S - 從屬 X - 不在乎
M - Master
S - Slave
X - Don't Care| M - Master |
| :--- |
| S - Slave |
| X - Don't Care |
F - 僅前進 RR - 反向和前進 X - 不在乎 ^(2){ }^{2}
F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)| F - Forward Only |
| :--- |
| $R$ - Reverse and Forward |
| X - Don't Care ${ }^{2}$ |
A - 全部(包括 LPDT) E - 事件 觸發器和 ULPS 只有 X - 不在乎
A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care| A - All (including LPDT) |
| :--- |
| E - events Triggers and ULPS Only X - Don't Care |
A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock
N - 不適用
N - 不適用
Prefix "Lane
Interconnect Side" High-Speed Capabilities "Forward
Direction Escape Mode Features Supported" "Reverse
Direction Escape
Mode Features Supported ^(1)"
CIL- "M - Master
S - Slave
X - Don't Care" "F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)" "A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care" A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock N - Not Applicable N - Not Applicable| Prefix | Lane <br> Interconnect Side | High-Speed Capabilities | Forward <br> Direction Escape Mode Features Supported | Reverse <br> Direction Escape <br> Mode Features Supported ${ }^{1}$ |
| :---: | :---: | :---: | :---: | :---: |
| CIL- | M - Master <br> S - Slave <br> X - Don't Care | F - Forward Only <br> $R$ - Reverse and Forward <br> X - Don't Care ${ }^{2}$ | A - All (including LPDT) <br> E - events Triggers and ULPS Only X - Don't Care | ```A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care``` |
| | | C-Clock | N - Not Applicable | N - Not Applicable |
注意:
“任何”是由一個或多個函數的任意組合。
僅適用於數據通道,表示“F”或“R”。
推薦的 PHY 協議介面包含以位元組格式的數據輸入和數據輸出、輸入和/或輸出時鐘信號以及控制信號。控制信號包括請求、握手、測試設置和初始化。附錄 A 中描述了一個邏輯內部介面的提案。雖然這不是一個要求,但使用提議的 PPI 可能非常有用。對於 IC 的外部使用,實現可能會在相同的引腳上多路復用許多信號。然而,出於功率效率的原因,PPI 通常位於 IC 內部。
Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)| Supported Directions for Escape mode including LPDT |
| :--- |
| (Bi-directional, Forward Only or Reverse Only) |
rarr\rightarrow
larr\leftarrow
時鐘方向(根據定義從主設備到從設備,必須指向與“僅時鐘通道”箭頭相同的方向)
Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)| Clock Direction |
| :--- |
| (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
PPI:PHY-協議介面
This Other Options Meaning
C1CCCCCCC1 https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792 Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional)
C1[I-][In][IH]1 C1C[I-][I-]1 Clock Lane
longleftrightarrow longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only)
⊮ longrightarrow ⋙≪ "Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)"
rarr larr "Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)"
https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607 PPI: PHY-Protocol Interface| This | Other Options | Meaning |
| :---: | :---: | :---: |
| <smiles>C1CCCCCCC1</smiles> | ![](https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792) | Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) |
| <smiles>C1[I-][In][IH]1</smiles> | <smiles>C1C[I-][I-]1</smiles> | Clock Lane |
| $\longleftrightarrow$ | $\longrightarrow$ | Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) |
| $\nVdash \longrightarrow$ | $\ggg \ll$ | Supported Directions for Escape mode including LPDT <br> (Bi-directional, Forward Only or Reverse Only) |
| $\rightarrow$ | $\leftarrow$ | Clock Direction <br> (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
| ![](https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607) | | PPI: PHY-Protocol Interface |
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
驅動橋樑狀態 (LP-00) 於時間 THS-PREPARE
觀察從 LP-01 到 LP-00 的轉換,並在時間 TD-TERM-EN 之後啟用線路終止
Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN| Observes transition form LP-01 to LP-00 on the |
| :--- |
| Lines, enables Line Termination after time TD-TERM-EN |
Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THS-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
驅動器 HS-0 持續時間 THS-ZERO
開始尋找領導序列
在識別到領導序列 'O11101' 時進行同步
Synchronizes upon recognition of Leader Sequence
'O11101'| Synchronizes upon recognition of Leader Sequence |
| :--- |
| 'O11101' |
在上升時鐘邊緣
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Rqst state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time THS-PREPARE "Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously." "Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects"
Drives HS-0 for a time THS-ZERO Starts looking for Leader-Sequence
"Synchronizes upon recognition of Leader Sequence
'O11101'"
on a rising Clock edge | TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time THS-PREPARE | Observes transition form LP-01 to LP-00 on the <br> Lines, enables Line Termination after time TD-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. | Enables HS-RX and waits for timer THS-SETTLE to <br> expire in order to neglect transition effects |
| Drives HS-0 for a time THS-ZERO | Starts looking for Leader-Sequence |
| | Synchronizes upon recognition of Leader Sequence <br> 'O11101' |
| on a rising Clock edge | |
版權所有。
6.4.3 傳輸結束
TX 端
RX 端
完成有效載荷數據的傳輸
接收有效載荷數據
在最後一個有效載荷數據位之後立即切換差分狀態,並保持該狀態一段時間 THS-TRAIL
Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL| Toggles differential state immediately after last |
| :--- |
| payload data bit and keeps that state for a time |
| THS-TRAIL |
禁用 HS-TX,啟用 LP-TX,並驅動停止狀態 (LP-11) 持續時間 THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables the LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
檢測離開 LP-00 狀態並進入停止狀態 (LP-11) 的線路並禁用終止
Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination| Detects the Lines leaving LP-00 state and entering |
| :--- |
| Stop state (LP-11) and disables Termination |
忽略上個時期的 THS-SKIP 位元以隱藏過渡效果
Neglect bits of last period THS-SKIP to hide transition
effects| Neglect bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
檢測有效數據中的最後過渡,確定最後有效數據字節並跳過尾部序列
Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence| Detect last transition in valid Data, determine last |
| :--- |
| valid Data byte and skip trailer sequence |
TX Side RX Side
Completes Transmission of payload data Receives payload data
"Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL"
"Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination"
"Neglect bits of last period THS-SKIP to hide transition
effects"
"Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence"| TX Side | RX Side |
| :--- | :--- |
| Completes Transmission of payload data | Receives payload data |
| Toggles differential state immediately after last <br> payload data bit and keeps that state for a time <br> THS-TRAIL | |
| Disables the HS-TX, enables the LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines leaving LP-00 state and entering <br> Stop state (LP-11) and disables Termination |
| | Neglect bits of last period THS-SKIP to hide transition <br> effects |
| | Detect last transition in valid Data, determine last <br> valid Data byte and skip trailer sequence |
State "Line
Condition/State" Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr End of timed interval TLPX
TX-HS-Prpr Transmit LP-00 TX-HS-Go End of timed interval THS-PREPARE
TX-HS-Go Transmit HS-0 TX-HS-Sync End of timed interval THS-zERO
TX-HS-Sync "Transmit
sequence
HS-00011101" TX-HS-0 After Sync sequence if first payload data bit is 0
TX-HS-1 After Sync sequence if first payload data bit is 1
TX-HS-0 Transmit HS-0 TX-HS-0 Send another HS-0 bit after a HS-0 bit
TX-HS-1 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Transmit HS-1 TX-HS-0 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Send another HS-1 bit after a HS-1
Trail-HS-0 Last payload bit is HS-1, trailer sequence is HS-0
Trail-HS-0 Transmit HS-0 TX-Stop End of timed interval THS-TRAlL
Trail-HS-1 Transmit HS-1 TX-Stop End of timed interval THS-TRAlL
RX-Stop Receive LP-11 RX-HS-Rqst Line transition to LP-01
RX- HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval TLPX |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval THS-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-Sync | End of timed interval THS-zERO |
| TX-HS-Sync | Transmit <br> sequence <br> HS-00011101 | TX-HS-0 | After Sync sequence if first payload data bit is 0 |
| | | TX-HS-1 | After Sync sequence if first payload data bit is 1 |
| TX-HS-0 | Transmit HS-0 | TX-HS-0 | Send another HS-0 bit after a HS-0 bit |
| | | TX-HS-1 | Send a HS-1 bit after a HS-0 bit |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-1 bit after a HS-0 bit |
| | | TX-HS-1 | Send another HS-1 bit after a HS-1 |
| | | Trail-HS-0 | Last payload bit is HS-1, trailer sequence is HS-0 |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval THS-TRAlL |
| Trail-HS-1 | Transmit HS-1 | TX-Stop | End of timed interval THS-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX- HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
州
線條狀態
Line
Condition/State| Line |
| :---: |
| Condition/State |
Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data.| Proper match found (any single bit error allowed if |
| :--- |
| deskew calibration feature is not used) for Sync |
| sequence in HS stream, the following bits are |
| payload data. |
RX-HS-1
RX-HS-0
接收 HS-0
RX-HS-0
接收有效載荷數據位或尾部位
RX-HS-1
RX-HS-1
接收 HS-1
RX-HS-0
接收有效載荷數據位或尾部位
RX-HS-1
RX-Stop
線路過渡到 LP-11
State "Line
Condition/State" Exit State Exit Conditions
RX-HS- Prpr Receive LP-00 RX-HS-Term End of timed interval TD-TERM-EN
RX-HS-Term Receive LP-00 RX-HS-Sync End of timed interval THS-SETTLE
RX-HS-Sync "Receive HS
sequence
...00000011101" RX-HS-0 "Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data."
RX-HS-1
RX-HS-0 Receive HS-0 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-HS-1 Receive HS-1 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-Stop Line transition to LP-11| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS- Prpr | Receive LP-00 | RX-HS-Term | End of timed interval TD-TERM-EN |
| RX-HS-Term | Receive LP-00 | RX-HS-Sync | End of timed interval THS-SETTLE |
| RX-HS-Sync | Receive HS <br> sequence <br> ...00000011101 | RX-HS-0 | Proper match found (any single bit error allowed if <br> deskew calibration feature is not used) for Sync <br> sequence in HS stream, the following bits are <br> payload data. |
| | | RX-HS-1 | |
| RX-HS-0 | Receive HS-0 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| RX-HS-1 | Receive HS-1 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| | | RX-Stop | Line transition to LP-11 |
Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control.| Observes the transition from LP-10 to Bridge state |
| :--- |
| and waits for a time TAA-SURE. After correct |
| completion of this time-out this side knows it is in |
| control. |
停止駕駛線路,並使用其 LP-RX 觀察線路狀態,以便查看確認。
Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement.| Stops driving the Lines and observes the Line states |
| :--- |
| with its LP-RX in order to see an acknowledgement. |
驅動橋樑狀態 (LP-00) 持續時間 TTA-GET
驅動器 LP-10 持續時間 TLPX
觀察 LP-10 在線上,解釋為承認對方確實已經掌控。等待停止狀態完成周轉程序。
Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure.| Observes LP-10 on the Lines, interprets this as |
| :--- |
| acknowledge that the other side has indeed taken |
| control. Waits for Stop state to complete Turnaround |
| procedure. |
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Drives Stop state (LP-11) Observes Stop state
Drives LP-Rqst state (LP-10) for a time TLPX Observes transition from LP-11 to LP-10 states
Drives Bridge state (LP-00) for a time T TPX Observes transition from LP-10 to LP-00 states
Drives LP-10 for a time T TPX Observes transition from LP-00 to LP-10 states
Drives Bridge state (LP-00) for a time TTA-GO "Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control."
"Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement." Drives Bridge state (LP-00) for a period TTA-GET
Drives LP-10 for a period TLPX
"Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure." | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives LP-Rqst state (LP-10) for a time TLPX | Observes transition from LP-11 to LP-10 states |
| Drives Bridge state (LP-00) for a time T TPX | Observes transition from LP-10 to LP-00 states |
| Drives LP-10 for a time T TPX | Observes transition from LP-00 to LP-10 states |
| Drives Bridge state (LP-00) for a time TTA-GO | Observes the transition from LP-10 to Bridge state <br> and waits for a time TAA-SURE. After correct <br> completion of this time-out this side knows it is in <br> control. |
| Stops driving the Lines and observes the Line states <br> with its LP-RX in order to see an acknowledgement. | Drives Bridge state (LP-00) for a period TTA-GET |
| | Drives LP-10 for a period TLPX |
| Observes LP-10 on the Lines, interprets this as <br> acknowledge that the other side has indeed taken <br> control. Waits for Stop state to complete Turnaround <br> procedure. | |
初始 TX 端 = 最終 RX 端
初始 RX 端 = 最終 TX 端
觀察到轉換到停止狀態(LP-11)在
轉彎完成
確認,切換到正常的 LP 接收
模式並等待其他人的進一步行動
側面
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Observes transition to Stop state (LP-11) on the
Lines, interprets this as Turnaround completion
acknowledgement, switches to normal LP receive
mode and waits for further actions from the other
side | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Observes transition to Stop state (LP-11) on the | |
| Lines, interprets this as Turnaround completion | |
| acknowledgement, switches to normal LP receive | |
| mode and waits for further actions from the other | |
| side | |
Line
Condition/State| Line |
| :---: |
| Condition/State |
退出狀態
退出條件
任何 RX 狀態
任何收到的
RX-Stop
觀察 LP-11 在行上
TX-Stop
傳輸 LP-11
TX-LP-Rqst
根據周轉協議的要求
TX-LP-Rqst
傳輸 LP-10
TX-LP-產量
結束計時區間 TLPX
TX-LP-產量
傳輸 LP-00
TX-TA-Rqst
結束計時區間 TLPX
TX-TA-Rqst
傳輸 LP-10
TX-TA-Go
結束計時區間 TLPX
TX-TA-Go
傳輸 LP-00
RX-TA-Look
計時區間結束 TTA-GO
RX-TA-Look
接收 LP-00
RX-TA-Ack
線路過渡到 LP-10
RX-TA-Ack
接收 LP-10
RX-Stop
線路過渡到 LP-11
RX-Stop
接收 LP-11
RX-LP-Rqst
線路過渡到 LP-10
RX-LP-Rqst
接收 LP-10
RX-LP-Yield
線路過渡到 LP-00
RX-LP-Yield
接收 LP-00
RX-TA-Rqst
線路過渡到 LP-10
RX-TA-Rqst
接收 LP-10
RX-TA-Wait
線路過渡到 LP-00
RX-TA-Wait
接收 LP-00
TX-TA-Get
定時區間結束 TTA-SURE
TX-TA-Get
傳輸 LP-00
TX-TA-Ack
計時區間結束 TTA-GET
TX-TA-Ack
Transit LP-10
TX-Stop
結束計時區間 TLPX
State "Line
Condition/State" Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Turnaround
TX-LP-Rqst Transmit LP-10 TX-LP-Yield End of timed interval TLPX
TX-LP-Yield Transmit LP-00 TX-TA-Rqst End of timed interval TLPX
TX-TA-Rqst Transmit LP-10 TX-TA-Go End of timed interval TLPX
TX-TA-Go Transmit LP-00 RX-TA-Look End of timed interval TTA-GO
RX-TA-Look Receive LP-00 RX-TA-Ack Line transition to LP-10
RX-TA-Ack Receive LP-10 RX-Stop Line transition to LP-11
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-TA-Rqst Line transition to LP-10
RX-TA-Rqst Receive LP-10 RX-TA-Wait Line transition to LP-00
RX-TA-Wait Receive LP-00 TX-TA-Get End of timed interval TTA-SURE
TX-TA-Get Transmit LP-00 TX-TA-Ack End of timed interval TTA-GET
TX-TA-Ack Transit LP-10 TX-Stop End of timed interval TLPX| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Turnaround |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | End of timed interval TLPX |
| TX-LP-Yield | Transmit LP-00 | TX-TA-Rqst | End of timed interval TLPX |
| TX-TA-Rqst | Transmit LP-10 | TX-TA-Go | End of timed interval TLPX |
| TX-TA-Go | Transmit LP-00 | RX-TA-Look | End of timed interval TTA-GO |
| RX-TA-Look | Receive LP-00 | RX-TA-Ack | Line transition to LP-10 |
| RX-TA-Ack | Receive LP-10 | RX-Stop | Line transition to LP-11 |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-TA-Rqst | Line transition to LP-10 |
| RX-TA-Rqst | Receive LP-10 | RX-TA-Wait | Line transition to LP-00 |
| RX-TA-Wait | Receive LP-00 | TX-TA-Get | End of timed interval TTA-SURE |
| TX-TA-Get | Transmit LP-00 | TX-TA-Ack | End of timed interval TTA-GET |
| TX-TA-Ack | Transit LP-10 | TX-Stop | End of timed interval TLPX |
Entry Command Pattern (first
bit transmitted to last bit
transmitted)| Entry Command Pattern (first |
| :---: |
| bit transmitted to last bit |
| transmitted) |
低功耗數據傳輸
模式
11100001
超低功耗狀態
模式
00011110
Undefined-1
模式
10011111
Undefined-2
模式
11011110
重置觸發器
Reset-Trigger| Reset-Trigger |
| :--- |
觸發器
01100010
HS 測試模式的進入序列
觸發器
01011101
Unknown-4
觸發器
00100001
Unknown-5
觸發器
10100000
Escape Mode Action Command Type "Entry Command Pattern (first
bit transmitted to last bit
transmitted)"
Low-Power Data Transmission mode 11100001
Ultra-Low Power State mode 00011110
Undefined-1 mode 10011111
Undefined-2 mode 11011110
"Reset-Trigger" Trigger 01100010
Entry sequence for HS Test Mode Trigger 01011101
Unknown-4 Trigger 00100001
Unknown-5 Trigger 10100000| Escape Mode Action | Command Type | Entry Command Pattern (first <br> bit transmitted to last bit <br> transmitted) |
| :--- | :--- | :---: |
| Low-Power Data Transmission | mode | 11100001 |
| Ultra-Low Power State | mode | 00011110 |
| Undefined-1 | mode | 10011111 |
| Undefined-2 | mode | 11011110 |
| Reset-Trigger | Trigger | 01100010 |
| Entry sequence for HS Test Mode | Trigger | 01011101 |
| Unknown-4 | Trigger | 00100001 |
| Unknown-5 | Trigger | 10100000 |
如果在逃逸模式進入命令之後發送超低功耗狀態進入命令,則通道應進入超低功耗狀態(ULPS)。此命令應標記給接收方協議。在此狀態下,線路處於空間狀態(LP-00)。超低功耗狀態的退出是通過一個長度為 Twakeup 的 Mark-1 狀態,然後是停止狀態。附錄 A 描述了一個退出程序的示例以及控制在 Mark-1 狀態中花費時間長度的程序。
6.6.4 逃逸模式狀態機
逃脫模式操作的狀態機如圖 20 所示,並在表 9 中描述。
注意:水平對齊的狀態同時發生。
圖 20 逃脫模式狀態機
表 9 逃脫模式狀態機描述
州
線條狀態
退出狀態
退出條件
任何 RX 狀態
任何收到的
RX-Stop
觀察 LP-11 在行上
TX-Stop
傳輸 LP-11
TX-LP-Rqst
根據對 Esc 模式(PPI)協議的要求
TX-LP-Rqst
傳輸 LP-10
TX-LP-產量
在時間 T_("LPX ")\mathrm{T}_{\text {LPX }} 之後
TX-LP-產量
傳輸 LP-00
TX-Esc-Rqst
After time T TPX
TX-Esc-Rqst
傳輸 LP-01
TX-Esc-Go
在時間 T LPX^("a ")\mathrm{LPX}^{\text {a }} 之後
TX-Esc-Go
傳輸 LP-00
TX-Esc-Cond
After time T TPX
TX-Esc-Cmd
傳輸 8 位元(16 行狀態)單空格熱編碼的輸入命令序列
TX-Triggers
觸發命令後
TX-ULPS
超低功耗命令後
TX-LPDT
低功耗數據傳輸命令之後
After Low-Power Data
Transmission Command| After Low-Power Data |
| :--- |
| Transmission Command |
TX-Triggers
空白狀態或可選的虛擬位元組,用於生成時鐘
TX-Mark
根據協議(PPI)要求觸發狀態的退出
TX-ULPS
傳輸 LP-00
TX-Mark
根據協議(PPI)要求的 ULP 狀態結束
State Line Condition/State Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Esc mode (PPI)
TX-LP-Rqst Transmit LP-10 TX-LP-Yield After time T_("LPX ")
TX-LP-Yield Transmit LP-00 TX-Esc-Rqst After time T TPX
TX-Esc-Rqst Transmit LP-01 TX-Esc-Go After time T LPX^("a ")
TX-Esc-Go Transmit LP-00 TX-Esc-Cond After time T TPX
TX-Esc-Cmd Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command TX-Triggers After a Trigger Command
TX-ULPS After Ultra-Low Power Command
TX-LPDT "After Low-Power Data
Transmission Command"
TX-Triggers Space state or optional dummy bytes for the purpose of generating clocks TX-Mark Exit of the Trigger State on request of Protocol (PPI)
TX-ULPS Transmit LP-00 TX-Mark End of ULP State on request of Protocol (PPI)| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Esc mode (PPI) |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | After time $\mathrm{T}_{\text {LPX }}$ |
| TX-LP-Yield | Transmit LP-00 | TX-Esc-Rqst | After time T TPX |
| TX-Esc-Rqst | Transmit LP-01 | TX-Esc-Go | After time T $\mathrm{LPX}^{\text {a }}$ |
| TX-Esc-Go | Transmit LP-00 | TX-Esc-Cond | After time T TPX |
| TX-Esc-Cmd | Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | TX-Triggers | After a Trigger Command |
| | | TX-ULPS | After Ultra-Low Power Command |
| | | TX-LPDT | After Low-Power Data <br> Transmission Command |
| TX-Triggers | Space state or optional dummy bytes for the purpose of generating clocks | TX-Mark | Exit of the Trigger State on request of Protocol (PPI) |
| TX-ULPS | Transmit LP-00 | TX-Mark | End of ULP State on request of Protocol (PPI) |
State Line Condition/State Exit State Exit Conditions
TX-LPDT Transmit serialized, Spaced-One-Hot encoded payload data After last transmitted data bit
TX-Mark Mark-1 TX-Stop Next driven state after time T_("LPX "), or T_("WAKEUP ") if leaving ULP State
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-Esc-Rqst Line transition to LP-01
RX-Esc-Rqst Receive LP-01 RX-Esc-Go Line transition to LP-00
RX-Esc-Go Receive LP-00 RX-Esc-Cmd Line transition out of LP-00
RX-Esc-Cmd Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command RX-Wait After Trigger and Unrecognized Commands
RX-ULPS After Ultra-Low Power Command
RX-LPDT After Low-Power Data Transmission Command
RX-ULPS Receive LP-00 RX-Wait Line transition to LP-10
RX-LPDT Receive serial, Spaced-One-Hot encoded payload data RX-Stop Line transition to LP-11 (Last state should be a Mark-1)
RX-Wait Any, except LP-11 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| TX-LPDT | Transmit serialized, Spaced-One-Hot encoded payload data | | After last transmitted data bit |
| TX-Mark | Mark-1 | TX-Stop | Next driven state after time $\mathrm{T}_{\text {LPX }}$, or $\mathrm{T}_{\text {WAKEUP }}$ if leaving ULP State |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-Esc-Rqst | Line transition to LP-01 |
| RX-Esc-Rqst | Receive LP-01 | RX-Esc-Go | Line transition to LP-00 |
| RX-Esc-Go | Receive LP-00 | RX-Esc-Cmd | Line transition out of LP-00 |
| RX-Esc-Cmd | Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | RX-Wait | After Trigger and Unrecognized Commands |
| | | RX-ULPS | After Ultra-Low Power Command |
| | | RX-LPDT | After Low-Power Data Transmission Command |
| RX-ULPS | Receive LP-00 | RX-Wait | Line transition to LP-10 |
| RX-LPDT | Receive serial, Spaced-One-Hot encoded payload data | RX-Stop | Line transition to LP-11 (Last state should be a Mark-1) |
| RX-Wait | Any, except LP-11 | RX-Stop | Line transition to LP-11 |
Drives High-Speed Clock signal (Toggling
HS-0/HS-1)| Drives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
接收高速時鐘信號(切換 HS-0/HS-1)
Receives High-Speed Clock signal (Toggling
HS-0/HS-1)| Receives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
最後數據通道進入低功耗模式
持續驅動高速度時鐘信號一段時間 TcLK-Post,並以 HS-0 狀態結束
Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state| Continues to drives High-Speed Clock signal for a |
| :--- |
| period TcLK-Post and ends with HS-0 state |
檢測在時間 TcLK-MISs 內缺少時鐘轉換,禁用 HS-RX,然後等待轉換到停止狀態
Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state| Detects absence of Clock transitions within a time |
| :--- |
| TcLK-MISs, disables HS-RX then waits for a transition |
| to the Stop state |
驅動 HS-0 的時間 TcLK-TRAIL
禁用 HS-TX,啟用 LP-TX,並驅動停止狀態 (LP-11) 持續時間 THS-EXIT
Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
檢測到線路轉換到 LP-11,禁用 HS 終端,並進入停止狀態
Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state| Detects the Lines transitions to LP-11, disables HS |
| :--- |
| termination, and enters Stop state |
Master Side Slave Side
"Drives High-Speed Clock signal (Toggling
HS-0/HS-1)" "Receives High-Speed Clock signal (Toggling
HS-0/HS-1)"
Last Data Lane goes into Low-Power mode
"Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state" "Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state"
Drives HS-0 for a time TcLK-TRAIL
"Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state"
| Master Side | Slave Side |
| :--- | :--- |
| Drives High-Speed Clock signal (Toggling <br> HS-0/HS-1) | Receives High-Speed Clock signal (Toggling <br> HS-0/HS-1) |
| Last Data Lane goes into Low-Power mode | |
| Continues to drives High-Speed Clock signal for a <br> period TcLK-Post and ends with HS-0 state | Detects absence of Clock transitions within a time <br> TcLK-MISs, disables HS-RX then waits for a transition <br> to the Stop state |
| Drives HS-0 for a time TcLK-TRAIL | |
| Disables the HS-TX, enables LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines transitions to LP-11, disables HS <br> termination, and enters Stop state |
| | |
表 11 高速時鐘傳輸啟動程序
TX 端
RX 端
驅動器停止狀態 (LP-11)
觀察停止狀態
驅動 HS-Req 狀態 (LP-01) 於時間 TLPX
觀察從 LP-11 到 LP-01 的過渡情況
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
驅動橋接狀態 (LP-00) 持續時間 TcLK-PREPARE
觀察從 LP-01 到 LP-00 的轉換。啟用在時間 TcLK-TERM-EN 之後的線路終止。
Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN| Observes transition from LP-01 to LP-00 on the |
| :--- |
| Lines. Enables Line Termination after time |
| TcLK-TERM-EN |
同時啟用高速驅動器並禁用低功耗驅動器。驅動 HS-0 持續時間為 TCLK-ZERO。
Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO.| Enables High-Speed driver and disables Low-Power |
| :--- |
| drivers simultaneously. Drives HS-0 for a time |
| TCLK-ZERO. |
啟用 HS-RX 並等待計時器 TcLK-SETTLE 到期,以忽略過渡效應
Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer TcLK-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
接收 HS 信號
在任何數據通道啟動之前,驅動高頻時鐘信號的時間周期為 TcLK-PRE
Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up| Drives the High-Speed Clock signal for time period |
| :--- |
| TcLK-PRE before any Data Lane starts up |
接收高速時鐘信號
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Req state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time TcLK-PREPARE "Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO." "Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects"
Receives HS-signal
"Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up" Receives High-Speed Clock signal| TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Req state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time TcLK-PREPARE | Observes transition from LP-01 to LP-00 on the <br> Lines. Enables Line Termination after time <br> TcLK-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. Drives HS-0 for a time <br> TCLK-ZERO. | Enables HS-RX and waits for timer TcLK-SETTLE to <br> expire in order to neglect transition effects |
| | Receives HS-signal |
| Drives the High-Speed Clock signal for time period <br> TcLK-PRE before any Data Lane starts up | Receives High-Speed Clock signal |
時鐘通道狀態機如圖 22 所示,並在表 12 中描述。
注意:水平對齊的狀態同時發生。
圖 22 高速時鐘傳輸狀態機
表 12 高速時鐘傳輸狀態機的描述
州
線條狀態
退出狀態
退出條件
TX-Stop
傳輸 LP-11
TX-HS-Rqst
高速度傳輸協議的要求
On request of Protocol
for High-Speed
Transmission| On request of Protocol |
| :--- |
| for High-Speed |
| Transmission |
TX-HS-Rqst
傳輸 LP-01
TX-HS-Prpr
定時區間 TLPx 結束
End of timed interval
TLPx| End of timed interval |
| :--- |
| TLPx |
TX-HS-Prpr
傳輸 LP-00
TX-HS-Go
定時區間結束 TcLK-PREPARE
End of timed interval
TcLK-PREPARE| End of timed interval |
| :--- |
| TcLK-PREPARE |
TX-HS-Go
傳輸 HS-0
TX-HS-1
定時間隔結束 TcLK-ZERO
End of timed interval
TcLK-ZERO| End of timed interval |
| :--- |
| TcLK-ZERO |
TX-HS-0
傳輸 HS-0
TX-HS-1
在 HS-0 階段之後發送 HS-1 階段:DDR 時鐘
Send a HS-1 phase after
a HS-0 phase: DDR
Clock| Send a HS-1 phase after |
| :--- |
| a HS-0 phase: DDR |
| Clock |
TX-HS-1
傳輸 HS-1
TX-HS-0
在 HS-1 階段之後發送 HS-0 階段:DDR 時鐘
Send a HS-0 phase after
a HS-1 phase: DDR
Clock| Send a HS-0 phase after |
| :--- |
| a HS-1 phase: DDR |
| Clock |
Trail-HS-0
應要求將時鐘巷設置為低功耗模式
On request to put Clock
Lane in Low-Power| On request to put Clock |
| :--- |
| Lane in Low-Power |
Trail-HS-0
傳輸 HS-0
TX-Stop
定時間隔結束 TcLK-TRAlL
End of timed interval
TcLK-TRAlL| End of timed interval |
| :--- |
| TcLK-TRAlL |
RX-Stop
接收 LP-11
RX-HS-Rqst
線路過渡到 LP-01
Line transition to LP-01| Line transition to LP-01 |
| :--- |
RX-HS-Rqst
接收 LP-01
RX-HS-Prpr
線路過渡到 LP-00
RX-HS-Prpr
接收 LP-00
RX-HS-Term
定時區間結束 TcLK-TERM-EN
End of timed interval
TcLK-TERM-EN| End of timed interval |
| :--- |
| TcLK-TERM-EN |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol
for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr "End of timed interval
TLPx"
TX-HS-Prpr Transmit LP-00 TX-HS-Go "End of timed interval
TcLK-PREPARE"
TX-HS-Go Transmit HS-0 TX-HS-1 "End of timed interval
TcLK-ZERO"
TX-HS-0 Transmit HS-0 TX-HS-1 "Send a HS-1 phase after
a HS-0 phase: DDR
Clock"
TX-HS-1 Transmit HS-1 TX-HS-0 "Send a HS-0 phase after
a HS-1 phase: DDR
Clock"
Trail-HS-0 "On request to put Clock
Lane in Low-Power"
Trail-HS-0 Transmit HS-0 TX-Stop "End of timed interval
TcLK-TRAlL"
RX-Stop Receive LP-11 RX-HS-Rqst "Line transition to LP-01"
RX-HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00
RX-HS-Prpr Receive LP-00 RX-HS-Term "End of timed interval
TcLK-TERM-EN"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol <br> for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval <br> TLPx |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval <br> TcLK-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-1 | End of timed interval <br> TcLK-ZERO |
| TX-HS-0 | Transmit HS-0 | TX-HS-1 | Send a HS-1 phase after <br> a HS-0 phase: DDR <br> Clock |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-0 phase after <br> a HS-1 phase: DDR <br> Clock |
| | | Trail-HS-0 | On request to put Clock <br> Lane in Low-Power |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval <br> TcLK-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX-HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
| RX-HS-Prpr | Receive LP-00 | RX-HS-Term | End of timed interval <br> TcLK-TERM-EN |
州
線條狀態
退出狀態
退出條件
RX-HS-Term
接收 LP-00
RX-HS-Clk
定時間隔結束 TCLK-SETTLE
End of timed interval
TCLK-SETTLE| End of timed interval |
| :--- |
| TCLK-SETTLE |
Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions| Time-out TCLK-MISs on the |
| :--- |
| period on the Clock |
| Lane without Clock |
| signal transitions |
RX-HS-End
接收 HS-0
RX-HS-Stop
線路過渡到 LP-11
State Line Condition/State Exit State Exit Conditions
RX-HS-Term Receive LP-00 RX-HS-Clk "End of timed interval
TCLK-SETTLE"
RX-HS-Clk "Receive DDR-Q Clock
signal" RX-Clk-End "Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions"
RX-HS-End Receive HS-0 RX-HS-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS-Term | Receive LP-00 | RX-HS-Clk | End of timed interval <br> TCLK-SETTLE |
| RX-HS-Clk | Receive DDR-Q Clock <br> signal | RX-Clk-End | Time-out TCLK-MISs on the <br> period on the Clock <br> Lane without Clock <br> signal transitions |
| RX-HS-End | Receive HS-0 | RX-HS-Stop | Line transition to LP-11 |
On request of Protocol
for Ultra-Low Power
State| On request of Protocol |
| :--- |
| for Ultra-Low Power |
| State |
TX-ULPS-Rqst
傳輸 LP-10
TX-ULPS
結束計時區間 TLPX
End of timed interval
TLPX| End of timed interval |
| :--- |
| TLPX |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-ULPS-Rqst "On request of Protocol
for Ultra-Low Power
State"
TX-ULPS-Rqst Transmit LP-10 TX-ULPS "End of timed interval
TLPX"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-ULPS-Rqst | On request of Protocol <br> for Ultra-Low Power <br> State |
| TX-ULPS-Rqst | Transmit LP-10 | TX-ULPS | End of timed interval <br> TLPX |
州
線條狀態
退出狀態
退出條件
TX-ULPS
傳輸 LP-00
TX-ULPS-Exit
應協議要求離開超低功耗狀態
On request of Protocol
to leave Ultra-Low
Power State| On request of Protocol |
| :--- |
| to leave Ultra-Low |
| Power State |
TX-ULPS-Exit
傳輸 LP-10
TX-Stop
結束計時間隔 TwakEuP
End of timed interval
TwakEuP| End of timed interval |
| :--- |
| TwakEuP |
RX-Stop
接收 LP-11
RX-ULPS-Rqst
線路過渡到 LP-10
RX-ULPS-Rqst
接收 LP-10
RX-ULPS
線路過渡到 LP-00
RX-ULPS
接收 LP-00
RX-ULPS-Exit
線路過渡到 LP-10
RX-ULPS-Exit
接收 LP-10
RX-Stop
線路過渡到 LP-11
State Line Condition/State Exit State Exit Conditions
TX-ULPS Transmit LP-00 TX-ULPS-Exit "On request of Protocol
to leave Ultra-Low
Power State"
TX-ULPS-Exit Transmit LP-10 TX-Stop "End of timed interval
TwakEuP"
RX-Stop Receive LP-11 RX-ULPS-Rqst Line transition to LP-10
RX-ULPS-Rqst Receive LP-10 RX-ULPS Line transition to LP-00
RX-ULPS Receive LP-00 RX-ULPS-Exit Line transition to LP-10
RX-ULPS-Exit Receive LP-10 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-ULPS | Transmit LP-00 | TX-ULPS-Exit | On request of Protocol <br> to leave Ultra-Low <br> Power State |
| TX-ULPS-Exit | Transmit LP-10 | TX-Stop | End of timed interval <br> TwakEuP |
| RX-Stop | Receive LP-11 | RX-ULPS-Rqst | Line transition to LP-10 |
| RX-ULPS-Rqst | Receive LP-10 | RX-ULPS | Line transition to LP-00 |
| RX-ULPS | Receive LP-00 | RX-ULPS-Exit | Line transition to LP-10 |
| RX-ULPS-Exit | Receive LP-10 | RX-Stop | Line transition to LP-11 |
Parameter Description Min Typ Max Unit Notes
Tclk-miss Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. 60 ns 1,6,8
Tclk-Post Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of T_("HS-trall ") to the beginning of Tclk-trall. 60 ns + 52*UI ns 5
Tclu-pre Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 8 UI 5
Tclk-prepare Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 38 95 ns 5
Tclk-settle Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. 95 300 ns 6, 7
Tclk-term-en Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. "Time for Dn to reach
Vterm-en" 38 ns 6
Tclk-trall Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 60 ns 5
Tclk-Prepare + Tclk-Zero Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. 300 ns 5
Td-TERM-EN Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses V_(IL,MAX). Time for Dn to reach V_("term-en ") 35 ns +4 * U 6
Teot Transmitted time interval from the start of T_("HS-TRAIL ") or T_("CLK-TRALL "), to the start of the LP-11 state following a HS burst. 105 ns + n12UI 3,5
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Tclk-miss | Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. | | | 60 | ns | 1,6,8 |
| Tclk-Post | Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of $T_{\text {HS-trall }}$ to the beginning of Tclk-trall. | 60 ns + 52*UI | | | ns | 5 |
| Tclu-pre | Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. | 8 | | | UI | 5 |
| Tclk-prepare | Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. | 38 | | 95 | ns | 5 |
| Tclk-settle | Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. | 95 | | 300 | ns | 6, 7 |
| Tclk-term-en | Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. | Time for Dn to reach <br> Vterm-en | | 38 | ns | 6 |
| Tclk-trall | Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. | 60 | | | ns | 5 |
| Tclk-Prepare + Tclk-Zero | Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. | 300 | | | ns | 5 |
| Td-TERM-EN | Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses $V_{I L, M A X}$. | Time for Dn to reach $V_{\text {term-en }}$ | | 35 ns +4 * U | | 6 |
| Teot | Transmitted time interval from the start of $\mathrm{T}_{\text {HS-TRAIL }}$ or $\mathrm{T}_{\text {CLK-TRALL }}$, to the start of the LP-11 state following a HS burst. | | | 105 ns + n*12*UI | | 3,5 |
| THS-EXIT | Time that the transmitter drives LP-11 following a HS burst. | 100 | | | ns | 5 |
Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value.| Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. |
| :--- |
| The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. |
LPX(MASTER) 比例 ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ")^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}
2/3
3/2
Tta-get
在鏈路轉換期間,新的發射器在接受控制後驅動橋接狀態(LP-00)的時間。
5*TLPX
ns
5
Tta-go
發射器在鏈路回轉期間驅動橋接狀態(LP-00)後釋放控制的時間。
4*TLPX
ns
5
Tta-sure
在連接轉換期間,新發射器在 LP-10 狀態後等待的時間,然後再發送橋接狀態(LP-00)。
TLPX
2*TLPX
ns
5
Twakeup
發射器在進入停止狀態之前驅動 Mark-1 狀態的時間,以便啟動從 ULPS 的退出。
1
ms
5
Parameter Description Min Typ Max Unit Notes
Ths-Prepare Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission 40ns+4 * Ul 85 ns + 6* UI ns 5
Ths-PRepare + Ths-zero ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns 5
Ths-settle "Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value." 85ns+6 * Ul 145 ns + 10*UI ns 6
THS-SKIP Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 40 55 ns +4 * Ul ns 6
Ths-trall Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst "max(n**8^(**)UI,:}
{: 60(ns)+n^(**)4**UI)" ns 2,3,5
Tinit See Section 6.11. 100 us 5
TLPX Transmitted length of any Low-Power state period 50 ns 4,5
Ratio TLPX Ratio of LPX(MASTER) ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ") 2/3 3/2
Tta-get Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. 5*TLPX ns 5
Tta-go Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. 4*TLPX ns 5
Tta-sure Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. TLPX 2*TLPX ns 5
Twakeup Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. 1 ms 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Ths-Prepare | Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission | $40 \mathrm{~ns}+4$ * Ul | | 85 ns + 6* UI | ns | 5 |
| Ths-PRepare + Ths-zero | ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. | 145 ns + 10*UI | | | ns | 5 |
| Ths-settle | Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. <br> The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. | $85 \mathrm{~ns}+6$ * Ul | | 145 ns + 10*UI | ns | 6 |
| THS-SKIP | Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. | 40 | | 55 ns +4 * Ul | ns | 6 |
| Ths-trall | Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst | $\begin{gathered} \max \left(\mathrm{n*} 8^{*} \mathrm{UI},\right. \\ \left.60 \mathrm{~ns}+\mathrm{n}^{*} 4 * \mathrm{UI}\right) \end{gathered}$ | | | ns | 2,3,5 |
| Tinit | See Section 6.11. | 100 | | | us | 5 |
| TLPX | Transmitted length of any Low-Power state period | 50 | | | ns | 4,5 |
| Ratio TLPX | Ratio of LPX(MASTER) $^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}$ | 2/3 | | 3/2 | | |
| Tta-get | Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. | 5*TLPX | | | ns | 5 |
| Tta-go | Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. | 4*TLPX | | | ns | 5 |
| Tta-sure | Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. | TLPX | | 2*TLPX | ns | 5 |
| Twakeup | Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. | 1 | | | ms | 5 |
Any LP level
except Stop States
for periods >100us| Any LP level |
| :--- |
| except Stop States |
| for periods >100us |
主控初始化
啟動或協議請求
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
TX-Stop
根據協議,第一停止狀態的持續時間長於 TinIT,MASTER
A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol| A First Stop state |
| :--- |
| for a period longer |
| than TinIT,MASTER as |
| specified by the |
| Protocol |
任何以長初始化停止狀態結束的 LP 信號序列
Any LP signaling
sequence that
ends with a long
Initialization Stop
state| Any LP signaling |
| :--- |
| sequence that |
| ends with a long |
| Initialization Stop |
| state |
關閉從屬
關機
任何 LP 狀態
升級
任何
Slave Init
啟動或協議請求
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
RX-Stop
根據協議,在輸入端觀察停止狀態的時間為 TinIT,SLAVE
Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol| Observe Stop state |
| :--- |
| at the inputs for a |
| period TinIT,SLAVE as |
| specified by the |
| Protocol |
任何以第一個長初始化停止期間結束的 LP 信號序列
Any LP signaling
sequence which
ends with the first
long Initialization
Stop period| Any LP signaling |
| :--- |
| sequence which |
| ends with the first |
| long Initialization |
| Stop period |
State Entry Conditions Exit State Exit Conditions Line Levels
Master Off Power-down Master Initialization Power-up "Any LP level
except Stop States
for periods >100us"
Master Init "Power-up or
Protocol request" TX-Stop "A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol" "Any LP signaling
sequence that
ends with a long
Initialization Stop
state"
Slave Off Power-down Any LP state Power-up Any
Slave Init "Power-up or
Protocol request" RX-Stop "Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol" "Any LP signaling
sequence which
ends with the first
long Initialization
Stop period"| State | Entry Conditions | Exit State | Exit Conditions | Line Levels |
| :--- | :--- | :--- | :--- | :--- |
| Master Off | Power-down | Master Initialization | Power-up | Any LP level <br> except Stop States <br> for periods >100us |
| Master Init | Power-up or <br> Protocol request | TX-Stop | A First Stop state <br> for a period longer <br> than TinIT,MASTER as <br> specified by the <br> Protocol | Any LP signaling <br> sequence that <br> ends with a long <br> Initialization Stop <br> state |
| Slave Off | Power-down | Any LP state | Power-up | Any |
| Slave Init | Power-up or <br> Protocol request | RX-Stop | Observe Stop state <br> at the inputs for a <br> period TinIT,SLAVE as <br> specified by the <br> Protocol | Any LP signaling <br> sequence which <br> ends with the first <br> long Initialization <br> Stop period |
TX Side RX Side
Drives stop state (LP-11) Observes stop state
Drives HS-Rqst state (LP-01) for time TLPX Observes transition from LP-11 to LP-01 on the lines| TX Side | RX Side |
| :--- | :--- |
| Drives stop state (LP-11) | Observes stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the lines |
Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)| Observes transition from LP-01 to LP-00 on the |
| :--- |
| lines, and enables line termination after time |
| TD-TERMEN $^{\mid}$ |
Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THs-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
開始尋找領導序列
插入高速度同步序列以進行高速偏移校準:'11111111_11111111',從上升時鐘邊緣開始
Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge| Inserts the high-speed sync sequence for high- |
| :--- |
| speed skew-calibration: '11111111_11111111' |
| beginning on a rising clock edge |
在識別到領導序列時進行同步:'1111_1111'
Synchronizes upon recognition of leader sequence:
'1111_1111'| Synchronizes upon recognition of leader sequence: |
| :--- |
| '1111_1111' |
接收 '01010101' 數據
Receives '01010101' data| Receives '01010101' data |
| :--- |
繼續傳輸與時鐘通道相同的高速數據:'01010101'
Continues to transmit high speed data that is the
same as the clock lane: '01010101'| Continues to transmit high speed data that is the |
| :--- |
| same as the clock lane: '01010101' |
在時鐘和數據通道之間進行高速傾斜校準
Performs high-speed skew-calibration between clock
and data lanes| Performs high-speed skew-calibration between clock |
| :--- |
| and data lanes |
完成時鐘和數據通道之間的高速斜率校準
Finishes high-speed skew-calibration between clock
and data lanes| Finishes high-speed skew-calibration between clock |
| :--- |
| and data lanes |
TX Side RX Side
Drives bridge state (LP-00) for time THS-PREPARE "Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)"
"Simultaneously enables high-speed driver and
disables low-power drivers"
Drives HS-0 for a time THS-ZERO "Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects"
Starts looking for leader sequence
"Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge" "Synchronizes upon recognition of leader sequence:
'1111_1111'"
"Receives '01010101' data"
"Continues to transmit high speed data that is the
same as the clock lane: '01010101'" "Performs high-speed skew-calibration between clock
and data lanes"
"Finishes high-speed skew-calibration between clock
and data lanes"
| TX Side | RX Side |
| :--- | :--- |
| Drives bridge state (LP-00) for time THS-PREPARE | Observes transition from LP-01 to LP-00 on the <br> lines, and enables line termination after time <br> TD-TERMEN $^{\mid}$ |
| Simultaneously enables high-speed driver and <br> disables low-power drivers | |
| Drives HS-0 for a time THS-ZERO | Enables HS-RX and waits for timer THs-SETTLE to <br> expire in order to neglect transition effects |
| | Starts looking for leader sequence |
| Inserts the high-speed sync sequence for high- <br> speed skew-calibration: '11111111_11111111' <br> beginning on a rising clock edge | Synchronizes upon recognition of leader sequence: <br> '1111_1111' |
| | Receives '01010101' data |
| Continues to transmit high speed data that is the <br> same as the clock lane: '01010101' | Performs high-speed skew-calibration between clock <br> and data lanes |
| | Finishes high-speed skew-calibration between clock <br> and data lanes |
| | |
Neglects bits of last period THS-SKIP to hide transition
effects| Neglects bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
檢測有效數據的最後過渡,確定最後有效數據字節並跳過尾部序列
Detects last transition of valid data, determines last
valid data byte and skip trailer sequence| Detects last transition of valid data, determines last |
| :--- |
| valid data byte and skip trailer sequence |
開始尋找領導序列
TX Side RX Side
Completes transmission of '01010101' data Receives '01010101' data
"Toggles differential state immediately after last
payload data bit and holds that state for a time
THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXIT""Detects the lines leaving LP-00 state and entering
the stop state (LP-11), and disables termination"
"Neglects bits of last period THS-SKIP to hide transition
effects"
"Detects last transition of valid data, determines last
valid data byte and skip trailer sequence"
Starts looking for leader sequence| TX Side | RX Side |
| :--- | :--- |
| Completes transmission of '01010101' data | Receives '01010101' data |
| Toggles differential state immediately after last <br> payload data bit and holds that state for a time <br> THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXITDetects the lines leaving LP-00 state and entering <br> the stop state (LP-11), and disables termination | |
| | Neglects bits of last period THS-SKIP to hide transition <br> effects |
| | Detects last transition of valid data, determines last <br> valid data byte and skip trailer sequence |
| | Starts looking for leader sequence |
Time that the transmitter drives the skew-
calibration sync pattern, FFFFH| Time that the transmitter drives the skew- |
| :--- |
| calibration sync pattern, FFFFH |
16
UI
TSKEWCAL
發射器在初始偏斜校準模式下驅動偏斜校準模式的時間
Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the initial skew- |
| calibration mode |
100
mus\mu \mathrm{~s}
2^(15)2^{15}
UI
TSKEWCAL
TSKEWCAL| TSKEWCAL |
| :--- |
發射器在周期性偏斜校準模式下驅動偏斜校準模式的時間
Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the periodic skew- |
| calibration mode |
10
mus\mu \mathrm{~s}
UI
Parameter Description Min Typ Max Unit Notes
TSKEWCAL_SYNC "Time that the transmitter drives the skew-
calibration sync pattern, FFFFH" 16 UI
TSKEWCAL "Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode" 100 mus
2^(15) UI
"TSKEWCAL" "Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode" 10 mus
UI | Parameter | Description | Min | Typ | Max | Unit | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| TSKEWCAL_SYNC | Time that the transmitter drives the skew- <br> calibration sync pattern, FFFFH | | 16 | | UI | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the initial skew- <br> calibration mode | | | 100 | $\mu \mathrm{~s}$ | |
| | $2^{15}$ | | | UI | | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the periodic skew- <br> calibration mode | | | 10 | $\mu \mathrm{~s}$ | |
| | | | | UI | | |
Output impedance of LP
transmitter| Output impedance of LP |
| :--- |
| transmitter |
110
Omega\Omega
3,4
Parameter Description Min Nom Max Units Notes
VOH_(OH) Thevenin output high level 1.1 1.2 1.3 V 1
0.95 1.3 V 2
VOL Thevenin output low level -50 50 mV
ZoLP "Output impedance of LP
transmitter" 110 Omega 3,4| Parameter | Description | Min | Nom | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| $\mathrm{VOH}_{\mathrm{OH}}$ | Thevenin output high level | 1.1 | 1.2 | 1.3 | V | 1 |
| | | 0.95 | | 1.3 | V | 2 |
| VOL | Thevenin output low level | -50 | | 50 | mV | |
| ZoLP | Output impedance of LP <br> transmitter | 110 | | | $\Omega$ | 3,4 |
注意:
適用於支援的數據速率 <= 1.5\leq 1.5 Gbps。
適用於支援的數據速率 > 1.5>1.5 Gbps。
請參見圖 48 和圖 49。
雖然未指定 ZoLP 的最大值,但 LP 發射器的輸出阻抗應確保滿足 T_(RLP)//T_(FLP)T_{R L P} / T_{F L P} 規範。
表 23 LP 發射器交流規格
參數
描述
Min
Nom
Max
單位
筆記
TrLP/TfLP
15%-85% 上升時間和下降時間
25
ns
1
Treot
30%-85% 上升時間和下降時間
35
ns
5,6
TLP-PuLSE-TX
LP 獨佔或時鐘的脈衝寬度
Pulse width of the LP
exclusive-OR clock| Pulse width of the LP |
| :--- |
| exclusive-OR clock |
停止狀態後的第一個 LP 獨佔或運算時鐘脈衝或停止狀態之前的最後一個脈衝
First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state| First LP |
| :--- |
| exclusive-OR |
| clock pulse after |
| Stop state or last pulse before Stop state |
40
ns
4
所有其他脈衝
20
ns
4
TLP-PER-TX
LP 獨佔或時鐘的週期
90
ns
deltaV// bar(" tsR ")\delta \mathrm{V} / \overline{\text { tsR }}
Slew rate @ Cload = 0pF
500
mV/ns
1, 3, 7, 8
Slew rate @ Cload = 5pF
300
mV//ns\mathrm{mV/ns}
1, 3, 7, 8
Slew rate @ Cload = 20pF
250
mV//ns\mathrm{mV/ns}
1, 3, 7, 8
Slew rate @ ClOAd = 70pF
150
mV//ns\mathrm{mV} / \mathrm{ns}
1, 3, 7, 8
Slew rate @ Cload =0=0 到 70pF (僅下降沿)
30
mV//ns\mathrm{mV/ns}
1, 2, 3, 12
25
mV/ns
1, 3, 13, 16
Parameter Description Min Nom Max Units Notes
TrLP/TfLP 15%-85% rise time and fall time 25 ns 1
Treot 30%-85% rise time and fall time 35 ns 5,6
TLP-PuLSE-TX "Pulse width of the LP
exclusive-OR clock" "First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state" 40 ns 4
All other pulses 20 ns 4
TLP-PER-TX Period of the LP exclusive-OR clock 90 ns
deltaV// bar(" tsR ") Slew rate @ Cload = 0pF 500 mV/ns 1, 3, 7, 8
Slew rate @ Cload = 5pF 300 mV//ns 1, 3, 7, 8
Slew rate @ Cload = 20pF 250 mV//ns 1, 3, 7, 8
Slew rate @ ClOAd = 70pF 150 mV//ns 1, 3, 7, 8
Slew rate @ Cload =0 to 70pF (Falling Edge Only) 30 mV//ns 1, 2, 3, 12
25 mV/ns 1, 3, 13, 16| Parameter | Description | | Min | Nom | Max | Units | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| TrLP/TfLP | 15%-85% rise time and fall time | | | | 25 | ns | 1 |
| Treot | 30%-85% rise time and fall time | | | | 35 | ns | 5,6 |
| TLP-PuLSE-TX | Pulse width of the LP <br> exclusive-OR clock | First LP <br> exclusive-OR <br> clock pulse after <br> Stop state or last pulse before Stop state | 40 | | | ns | 4 |
| | | All other pulses | 20 | | | ns | 4 |
| TLP-PER-TX | Period of the LP exclusive-OR clock | | 90 | | | ns | |
| $\delta \mathrm{V} / \overline{\text { tsR }}$ | Slew rate @ Cload = 0pF | | | | 500 | mV/ns | 1, 3, 7, 8 |
| | Slew rate @ Cload = 5pF | | | | 300 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload = 20pF | | | | 250 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ ClOAd = 70pF | | | | 150 | $\mathrm{mV} / \mathrm{ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload $=0$ to 70pF (Falling Edge Only) | | 30 | | | $\mathrm{mV/ns}$ | 1, 2, 3, 12 |
| | | | 25 | | | mV/ns | 1, 3, 13, 16 |
本附錄僅供參考。遵循 D-PHY 規範不依賴於此處定義的 PPI 的任何部分。因此,本附錄避免使用規範性語言,並不使用“應該”和“必須”等詞語。相反,使用現在時語言來描述 PPI,使用“是”和“做”等詞語。讀者可能會發現,將本附錄視為示例實現的描述,而不是規範,會更有幫助。本附錄中描述的信號接口,即 PHY 協議接口(PPI)是可選的。然而,如果模塊包含 PPI 接口,則必須按照本附錄中所述實現它。
此 PPI 經過優化,用於控制 D-PHY 並傳輸和接收並行數據。此處描述的接口定義為片上連接,並未嘗試最小化信號數量或定義 PPI 信號的定時參數或電壓水平。
A. 1 信號描述
表 38 定義了 PPI 中使用的信號。對於具有多個數據通道的 PHY,每個通道使用一組 PPI 信號。每個信號被分配到六個類別之一:高速發送信號、高速接收信號、逃逸模式發送信號、逃逸模式接收信號、控制信號和錯誤信號。支持雙向逃逸模式的雙向高速數據通道幾乎包括表中列出的所有信號。單向通道或時鐘通道僅包括信號的子集。每個信號的方向標示為“I”或“O”。方向為“I”的信號是 PHY 輸入,來自協議驅動。方向為“O”的信號是 PHY 輸出,驅動到協議。對於這個邏輯接口,大多數時鐘被描述為在 PHY 外部生成,儘管任何特定的 PHY 可能以不同的方式實現時鐘電路。
協議和 D-PHY 將根據表 38 中描述的最適合操作的數據通道寬度進行選擇。總線寬度的選擇基於邏輯二進制輸入,如 TxDataWidthHS[1:0] 和 RxDataWidthHS[1:0] 中所解釋的。總線寬度可以根據操作要求在當前突發完成後進行修改。在一個 IC 中的發送功能的 PPI 數據通道寬度不必與另一個 IC 中的接收功能的 PPI 數據通道寬度相匹配。D-PHY 能夠傳輸和接收任何大於零的整數字數,無論 PPI Tx 和 Rx 數據通道的寬度如何。每組通過 PPI 傳輸的數據都伴隨著一組數據有效信號,以指示哪些字包含有效數據以進行傳輸,或哪些字包含實際從通道接收到的數據。
Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal.| Data Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
TxDDRCIkHS-Q
I
MCNN
Clock Lane 高速傳輸 DDR 時鐘。此信號用於生成通道互連的高速時鐘信號。TxDDRCIkHS-Q(正交)時鐘信號相對於 TxDDRCIkHS-I 時鐘信號相位偏移。
Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal.| Clock Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate.| High-Speed Transmit Word Clock. |
| :--- |
| This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: |
| - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. |
| - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. |
| - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Transmit Data bus Width Select. |
| :--- |
| Selects the bus width of TxDataHS: |
| - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. |
| - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] |
| - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] |
| - TxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit.| High-Speed Transmit Data bus width. |
| :--- |
| High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: |
| - 8-bit width - TxDataHS[7:0] |
| - 16-bit width - TxDataHS[15:0] |
| - 32-bit width - TxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
Symbol Dir Categories Description
High-Speed Transmit Signals
TxDDRCIkHS-I 1 "MXXX
MCNN" "Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal."
TxDDRCIkHS-Q I MCNN "Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal."
TxWordCIkHS 0 "MXXX
SRXX" "High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate."
TxDataWidthHS[1:0] I " MXXX
SRXX " "High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] I "MXXX
SRXX" "High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| High-Speed Transmit Signals | | | |
| TxDDRCIkHS-I | 1 | MXXX <br> MCNN | Data Lane High-Speed Transmit DDR Clock. <br> This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
| TxDDRCIkHS-Q | I | MCNN | Clock Lane High-Speed Transmit DDR Clock. <br> This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
| TxWordCIkHS | 0 | MXXX <br> SRXX | High-Speed Transmit Word Clock. <br> This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: <br> - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. <br> - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. <br> - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
| TxDataWidthHS[1:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SRXX } \end{aligned}$ | High-Speed Transmit Data bus Width Select. <br> Selects the bus width of TxDataHS: <br> - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. <br> - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] <br> - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] <br> - TxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] | I | MXXX <br> SRXX | High-Speed Transmit Data bus width. <br> High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: <br> - 8-bit width - TxDataHS[7:0] <br> - 16-bit width - TxDataHS[15:0] <br> - 32-bit width - TxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted.| High-Speed Transmit Word Data Valid. |
| :--- |
| When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: |
| - 8-bit width - TxWordValidHS[0] |
| - 16-bit width - TxWordValidHS[1:0] |
| - 32-bit width - TxWordValidHS[3:0] |
| The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: |
| - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted |
| - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted |
| - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted |
| - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low.| High-Speed Transmit Request and Data Valid. |
| :--- |
| A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. |
| For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. |
| For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. |
| TxRequestHS is only asserted while TxRequestEsc is low. |
TxReadyHS
O
MXXX
SRXX
MXXX
SRXX| MXXX |
| :--- |
| SRXX |
高速傳輸準備就緒。此高電平信號表示 TxDataHS 已被通道模組接受以進行串行傳輸。TxReadyHS 在 TxWordCIkHS 的上升沿有效。可選地,TxReadyHS 可在去偏校準期間使用,以指示 SoT 已結束且數據通道正在傳輸去偏突發(時鐘模式)。
High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern).| High-Speed Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. |
| Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
Symbol Dir Categories Description
"TxWordValidHS[0],
or
TxWordValidHS[1:0],
or
TxWordValidHS[3:0]" I "MXXX
SRXX" "High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted."
TxEqActiveHS I MXXX This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled.
TxEqLevelHS I MXXX This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( 3.5dB+//-1dB ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( 7dB+//-1dB ) is active.
TxRequestHS I "MXXX
SRXX
MCNN" "High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low."
TxReadyHS O "MXXX
SRXX" "High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern)."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxWordValidHS[0], <br> or <br> TxWordValidHS[1:0], <br> or <br> TxWordValidHS[3:0] | I | MXXX <br> SRXX | High-Speed Transmit Word Data Valid. <br> When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: <br> - 8-bit width - TxWordValidHS[0] <br> - 16-bit width - TxWordValidHS[1:0] <br> - 32-bit width - TxWordValidHS[3:0] <br> The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: <br> - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted <br> - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted <br> - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted <br> - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
| TxEqActiveHS | I | MXXX | This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled. |
| TxEqLevelHS | I | MXXX | This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( $3.5 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( $7 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. |
| TxRequestHS | I | MXXX <br> SRXX <br> MCNN | High-Speed Transmit Request and Data Valid. <br> A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. <br> For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. <br> For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. <br> TxRequestHS is only asserted while TxRequestEsc is low. |
| TxReadyHS | O | MXXX <br> SRXX | High-Speed Transmit Ready. <br> This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. <br> Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence.| High-Speed Transmit Skew Calibration. |
| :--- |
| This is an optional pin to initiate the periodic deskew burst at the transmitter. |
| A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. |
| A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate.| High-Speed Receive Word Clock. |
| :--- |
| This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: |
| - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. |
| - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. |
| - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Receive Data Width Select. |
| :--- |
| Selects the bus width of RxDataHS: |
| - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] |
| - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] |
| - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] |
| - RxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit.| High-Speed Receive Data. |
| :--- |
| High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: |
| - 8-bit width - RxDataHS[7:0] |
| - 16-bit width - RxDataHS[15:0] |
| - 32-bit width - RxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
Symbol Dir Categories Description
TxSkewCalHS I MXXX "High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence."
High-Speed Receive Signals
RxWordCIkHS 0 "MRXX
SXXX" "High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate."
RxDataWidthHS[1:0] I "MRXX
SXXX" "High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] 0 "MRXX
SXXX" "High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxSkewCalHS | I | MXXX | High-Speed Transmit Skew Calibration. <br> This is an optional pin to initiate the periodic deskew burst at the transmitter. <br> A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. <br> A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
| High-Speed Receive Signals | | | |
| RxWordCIkHS | 0 | MRXX <br> SXXX | High-Speed Receive Word Clock. <br> This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: <br> - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. <br> - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. <br> - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
| RxDataWidthHS[1:0] | I | MRXX <br> SXXX | High-Speed Receive Data Width Select. <br> Selects the bus width of RxDataHS: <br> - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] <br> - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] <br> - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] <br> - RxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] | 0 | MRXX <br> SXXX | High-Speed Receive Data. <br> High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: <br> - 8-bit width - RxDataHS[7:0] <br> - 16-bit width - RxDataHS[15:0] <br> - 32-bit width - RxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel.| High-Speed Receive Data Valid. |
| :--- |
| This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. |
| The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: |
| - 8-bit width - RxValidHS[0] |
| - 16-bit width - RxValidHS[1:0] |
| - 32-bit width - RxValidHS[3:0] |
| The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: |
| - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel |
| - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel |
| - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel |
| - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
RxActiveHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
高速接收啟用。此高信號表示車道模組正在積極接收來自車道互連的高速傳輸。
High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect.| High-Speed Reception Active. |
| :--- |
| This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted.| Receiver Synchronization Observed. |
| :--- |
| This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
RxCIkActiveHS
0
SCNN
接收器時鐘啟用。此非同步的高電平信號表示時鐘通道正在接收 DDR 時鐘信號。
Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal.| Receiver Clock Active. |
| :--- |
| This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low.| Receiver DDR Clock. |
| :--- |
| This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State.| High-Speed Receive Skew Calibration. |
| :--- |
| This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
Symbol Dir Categories Description
RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] O "MRXX
SXXX" "High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel."
RxActiveHS O "MRXX
SXXX" "High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect."
RxSyncHS 0 "MRXX
SXXX" "Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted."
RxCIkActiveHS 0 SCNN "Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal."
RxDDRCIkHS 0 SCNN "Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low."
RxSkewCalHS 0 SXXX "High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] | O | MRXX <br> SXXX | High-Speed Receive Data Valid. <br> This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. <br> The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: <br> - 8-bit width - RxValidHS[0] <br> - 16-bit width - RxValidHS[1:0] <br> - 32-bit width - RxValidHS[3:0] <br> The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: <br> - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel <br> - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel <br> - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel <br> - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
| RxActiveHS | O | MRXX <br> SXXX | High-Speed Reception Active. <br> This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
| RxSyncHS | 0 | MRXX <br> SXXX | Receiver Synchronization Observed. <br> This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
| RxCIkActiveHS | 0 | SCNN | Receiver Clock Active. <br> This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
| RxDDRCIkHS | 0 | SCNN | Receiver DDR Clock. <br> This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
| RxSkewCalHS | 0 | SXXX | High-Speed Receive Skew Calibration. <br> This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode.| Escape mode Transmit Clock. |
| :--- |
| This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
TxRequestEsc
I
{:[MXXX],[SXXY]:}\begin{aligned} & M X X X \\ & S X X Y \end{aligned}
Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low.| Escape mode Transmit Request. |
| :--- |
| This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted.| Escape mode Transmit Low-Power Data. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. |
| TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State.| Transmit ULP Exit Sequence. |
| :--- |
| This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. |
| The PHY later drives the Stop state (LP-11) when |
| TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. |
| This signal is ignored when the Lane is not in the ULP State. |
Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted.| Escape mode Transmit Ultra-Low Power State. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. |
| TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
Symbol Dir Categories Description
Escape Mode Transmit Signals
TxClkEsc I " MXXX
SXXY " "Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode."
TxRequestEsc I "MXXX
SXXY" "Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low."
TxLpdtEsc I "MXAX
SXXA" "Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted."
TxUlpsExit I "MXXX
SXXY
MCNN" "Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State."
TxUlpsEsc I "MXXX
SXXY" "Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Escape Mode Transmit Signals | | | |
| TxClkEsc | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Clock. <br> This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
| TxRequestEsc | I | $\begin{aligned} & M X X X \\ & S X X Y \end{aligned}$ | Escape mode Transmit Request. <br> This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
| TxLpdtEsc | I | MXAX <br> SXXA | Escape mode Transmit Low-Power Data. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. <br> TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
| TxUlpsExit | I | MXXX <br> SXXY <br> MCNN | Transmit ULP Exit Sequence. <br> This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. <br> The PHY later drives the Stop state (LP-11) when <br> TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. <br> This signal is ignored when the Lane is not in the ULP State. |
| TxUlpsEsc | I | MXXX <br> SXXY | Escape mode Transmit Ultra-Low Power State. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. <br> TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Transmit Trigger 0-3. |
| :--- |
| One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. |
| Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. |
| TxTriggerEsc[0] corresponds to Reset-Trigger. |
| TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| TxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc.| Escape mode Transmit Data. |
| :--- |
| This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge.| Escape mode Transmit Data Valid. |
| :--- |
| This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc.| Escape mode Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic.| Escape mode Receive Clock. |
| :--- |
| This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Low-Power Data Receive mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Ultra-Low Power (Receive) mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
Symbol Dir Categories Description
TxTriggerEsc[3:0] I " MXXX
SXXY " "Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger."
TxDataEsc[7:0] I "MXAX
SXXA" "Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc."
TxValidEsc I "MXAX
SXXA" "Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge."
TxReadyEsc O "MXAX
SXXA" "Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc."
Escape Mode Receive Signals
RxCIkEsc O MXXY SXXX "Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic."
RxLpdtEsc O MXXA SXAX "Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect."
RxUlpsEsc O "MXXY
SXXX" "Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxTriggerEsc[3:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Trigger 0-3. <br> One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. <br> Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. <br> TxTriggerEsc[0] corresponds to Reset-Trigger. <br> TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> TxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| TxDataEsc[7:0] | I | MXAX <br> SXXA | Escape mode Transmit Data. <br> This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
| TxValidEsc | I | MXAX <br> SXXA | Escape mode Transmit Data Valid. <br> This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
| TxReadyEsc | O | MXAX <br> SXXA | Escape mode Transmit Ready. <br> This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
| Escape Mode Receive Signals | | | |
| RxCIkEsc | O | MXXY SXXX | Escape mode Receive Clock. <br> This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
| RxLpdtEsc | O | MXXA SXAX | Escape Low-Power Data Receive mode. <br> This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
| RxUlpsEsc | O | MXXY <br> SXXX | Escape Ultra-Low Power (Receive) mode. <br> This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Receive Trigger 0-3. |
| :--- |
| These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. |
| RxTriggerEsc[0] corresponds to Reset-Trigger. |
| RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| RxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc.| Escape mode Receive Data. |
| :--- |
| This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data.| Escape mode Receive Data Valid. |
| :--- |
| This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored.| Turn Around Request. |
| :--- |
| This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input).| Transmit/Receive Direction. |
| :--- |
| This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module.| Disable Turn-around. |
| :--- |
| This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer.| Force Lane Module Into Receive mode / Wait for Stop state. |
| :--- |
| This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
Symbol Dir Categories Description
RxTriggerEsc[3:0] O "MXXY
SXXX" "Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger."
RxDataEsc[7:0] O "MXXA
SXAX" "Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc."
RxValidEsc O "MXXA
SXAX" "Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data."
Control Signals
TurnRequest I "XRXX
XFXY" "Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored."
Direction 0 " XRXX
XFXY " "Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input)."
TurnDisable I " XRXX
XFXY " "Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module."
ForceRxmode I "MRXX
MXXY
SXXX" "Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxTriggerEsc[3:0] | O | MXXY <br> SXXX | Escape mode Receive Trigger 0-3. <br> These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. <br> RxTriggerEsc[0] corresponds to Reset-Trigger. <br> RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> RxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| RxDataEsc[7:0] | O | MXXA <br> SXAX | Escape mode Receive Data. <br> This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
| RxValidEsc | O | MXXA <br> SXAX | Escape mode Receive Data Valid. <br> This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
| Control Signals | | | |
| TurnRequest | I | XRXX <br> XFXY | Turn Around Request. <br> This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
| Direction | 0 | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Transmit/Receive Direction. <br> This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
| TurnDisable | I | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Disable Turn-around. <br> This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
| ForceRxmode | I | MRXX <br> MXXY <br> SXXX | Force Lane Module Into Receive mode / Wait for Stop state. <br> This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
通道處於停止狀態。這個高電平信號表示通道模組,無論是發射器還是接收器,當前都處於停止狀態。請注意,這個信號與 PPI 介面中的任何時鐘都是非同步的。此外,協議可能會使用這個信號間接確定 PHY 線路電平是否處於 LP-11 狀態。
Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state.| Lane is in Stop state. |
| :--- |
| This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
啟用
I
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
啟用車道模組。此高電位信號強制車道模組脫離“關閉”狀態。當啟用信號為低時,所有線驅動器、接收器、終端和爭用檢測器都會關閉。此外,當啟用信號為低時,所有其他 PPI 輸入將被忽略,所有 PPI 輸出將被驅動到默認的非活動狀態。啟用信號是一個電平敏感信號,並不依賴於任何時鐘。
Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock.| Enable Lane Module. |
| :--- |
| This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted.| Transmit Ultra-Low Power State on Clock Lane. |
| :--- |
| This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect.| Receive Ultra-Low Power State on Clock Lane. |
| :--- |
| This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted.| ULP State (not) Active. |
| :--- |
| This active low signal is asserted to indicate that the Lane is in ULP state. |
| For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. |
| For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
Symbol Dir Categories Description
ForceTxStopmode I "MXXX
SRXX
SXXY" Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state.
Stopstate O "XXXX
XCNN" "Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state."
Enable I "XXXX
XCNN" "Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock."
TxUlpsClk I MCNN "Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted."
RxUlpsClkNot 0 SCNN "Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect."
UlpsActiveNot O "XXXX
XCNN" "ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| ForceTxStopmode | I | MXXX <br> SRXX <br> SXXY | Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state. |
| Stopstate | O | XXXX <br> XCNN | Lane is in Stop state. <br> This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
| Enable | I | XXXX <br> XCNN | Enable Lane Module. <br> This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
| TxUlpsClk | I | MCNN | Transmit Ultra-Low Power State on Clock Lane. <br> This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
| RxUlpsClkNot | 0 | SCNN | Receive Ultra-Low Power State on Clock Lane. <br> This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
| UlpsActiveNot | O | XXXX <br> XCNN | ULP State (not) Active. <br> This active low signal is asserted to indicate that the Lane is in ULP state. <br> For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. <br> For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
符號
Dir
類別
描述
錯誤信號
ErrSotHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
傳輸開始(SoT)錯誤。如果高速 SoT 領導序列損壞,但仍能實現適當的同步,則此主動高信號在 RxWordCIkHS 的一個週期內被斷言。這被視為領導序列中的“軟錯誤”,並且對有效載荷數據的信心降低。
Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced.| Start-of-Transmission (SoT) Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
ErrSotSyncHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
傳輸開始同步錯誤。如果高速 SoT 領導序列以無法預期正確同步的方式損壞,則此高電平信號在 RxWordCIkHS 的一個週期內被置為有效。
Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS.| Start-of-Transmission Synchronization Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state.| Escape Entry Error. |
| :--- |
| If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state.| Low-Power Data Transmission Synchronization Error. |
| :--- |
| If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state.| Control Error. |
| :--- |
| This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
ErrContentionLPO
O
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
LPO 競爭錯誤。當通道模組在嘗試將線路拉低時檢測到線路上的競爭情況時,會啟用此高電平信號。
LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low.| LPO Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
ErrContentionLP1
O
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
LP1 競爭錯誤。當通道模組在嘗試將線路拉高時檢測到線路上的競爭情況時,會啟用此高電平信號。
LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high.| LP1 Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Symbol Dir Categories Description
Error Signals
ErrSotHS O "MRXX
SXXX" "Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced."
ErrSotSyncHS O "MRXX
SXXX" "Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS."
ErrEsc O "MXXY
SXXX" "Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state."
ErrSyncEsc O "MXXA
SXAX" "Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state."
ErrControl O "MXXY
SXXX" "Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state."
ErrContentionLPO O "MXXX
SXXY" "LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low."
ErrContentionLP1 O "MXXX
SXXY" "LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Error Signals | | | |
| ErrSotHS | O | MRXX <br> SXXX | Start-of-Transmission (SoT) Error. <br> If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
| ErrSotSyncHS | O | MRXX <br> SXXX | Start-of-Transmission Synchronization Error. <br> If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
| ErrEsc | O | MXXY <br> SXXX | Escape Entry Error. <br> If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrSyncEsc | O | MXXA <br> SXAX | Low-Power Data Transmission Synchronization Error. <br> If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrControl | O | MXXY <br> SXXX | Control Error. <br> This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
| ErrContentionLPO | O | MXXX <br> SXXY | LPO Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
| ErrContentionLP1 | O | MXXX <br> SXXY | LP1 Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Parameter Description Min Units
TWAIT-OPTICAL Additional wait time for synchronization of the optical link 150,000 UI (lane data bit)| Parameter | Description | Min | Units |
| :---: | :---: | :---: | :---: |
| TWAIT-OPTICAL | Additional wait time for synchronization of the optical link | 150,000 | UI (lane data bit) |
Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| LPDT. |
| Active HIGH signal |
TxProMarkerHS
I
MXXX
(SRXX)
MXXX
(SRXX)| MXXX |
| :--- |
| (SRXX) |
功能手柄,用於在串行流中插入協議標記符號以進行 HS 傳輸。有效高信號
Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| HS transmission. |
| Active HIGH signal |
Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal| Functional handle for the protocol to hold on providing data to the PHY |
| :--- |
| without ending the HS transmission. In the case of a continued transmission |
| request without Valid data, the PHY coding layer inserts Idle symbols. |
| Active HIGH signal |
RxAlignErrorEsc
O
SXAX
(MXXA)
SXAX
(MXXA)| SXAX |
| :--- |
| (MXXA) |
標誌以指示在 LPDT 流中觀察到的逗號代碼未與假定的單詞邊界對齊。主動高信號(可選)
Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)| Flag to indicate that a Comma code has been observed in the LPDT stream |
| :--- |
| that was not aligned with the assumed word boundary. |
| Active HIGH signal (optional) |
Symbol Dir Categories Description
TxProMarkerEsc I "MXAX
(SXXA)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal"
TxProMarkerHS I "MXXX
(SRXX)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal"
TxValidHS I "MXXX
(SRXX)" "Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal"
RxAlignErrorEsc O "SXAX
(MXXA)" "Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)"| Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| TxProMarkerEsc | I | MXAX <br> (SXXA) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> LPDT. <br> Active HIGH signal |
| TxProMarkerHS | I | MXXX <br> (SRXX) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> HS transmission. <br> Active HIGH signal |
| TxValidHS | I | MXXX <br> (SRXX) | Functional handle for the protocol to hold on providing data to the PHY <br> without ending the HS transmission. In the case of a continued transmission <br> request without Valid data, the PHY coding layer inserts Idle symbols. <br> Active HIGH signal |
| RxAlignErrorEsc | O | SXAX <br> (MXXA) | Flag to indicate that a Comma code has been observed in the LPDT stream <br> that was not aligned with the assumed word boundary. <br> Active HIGH signal (optional) |
{:[" Flag to indicate that a Comma code has been observed during HS reception "],[" that was not aligned with the assumed word boundary. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received using LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received in HS mode. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Indication flag that Idle patterns are observed at the Lines during LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
(MRXX)
Symbol Dir Categories Description
RxAlignErrorHS O " SXXX
(MRXX) " " Flag to indicate that a Comma code has been observed during HS reception
that was not aligned with the assumed word boundary.
Active HIGH signal (optional) "
RxBadSymbolEsc O " SXAX
(MXXA) " " Flag to indicate that a non-existing symbol was received using LPDT.
Active HIGH signal (optional) "
RxBadSymbolHS O " SXXX
(MRXX) " " Flag to indicate that a non-existing symbol was received in HS mode.
Active HIGH signal (optional) "
RxEoTErrorEsc O " SXAX
(MXXA) " " Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleEsc O " SXXX
(MRXX) " " Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleHS O " SXAX
(MXXA) " " Indication flag that Idle patterns are observed at the Lines during LPDT.
Active HIGH signal (optional) "
(MRXX) | Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| RxAlignErrorHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxEoTErrorEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleEsc | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleHS | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| (MRXX) | | | |
Ahmed F. Aboulella, Mixel, Inc. Bhupendra Ahuja, NVIDIA Mario Ackers, Toshiba Corporation
喬凡尼·安傑洛,Freescale Semiconductor 拉達·阿圖庫拉,NVIDIA 張洪白,三星電子公司 安德魯·巴爾德曼,MIPI Alliance, Inc. 塞德里克·貝爾托洛姆,STMicroelectronics 傑里特·登·貝斯滕,NXP Semiconductor 伊格納修斯·貝扎姆,Arasan Chip Systems, Inc. 托馬斯·布隆,Silicon Line GmbH 馬克·布勞恩,摩托羅拉流動性,LLC 喬治·布羅克赫斯特,Mindspeed Technologies, Inc. 多米尼克·布魩內爾,STMicroelectronics 蒂埃里·坎皮切,LeCroy Corporation 瑪拉·卡瓦略,Synopsys, Inc. 郭欽·張,OmniVision Technologies, Inc. 關敏杰,Keysight Technologies Inc. 洛朗·克拉拉蒙,STMicroelectronics 基里爾·迪米特羅夫,SanDisk Corporation 基尤爾·迪萬,Tektronix, Inc. 丹·德雷珀,Mindspeed Technologies, Inc. 肯·德羅塔,英特爾公司 馬哈茂德·艾爾-巴納,Mixel, Inc. 邁克爾·弗萊舍-羅伊曼,Keysight Technologies Inc.
SeungLi Kim, 三星電子有限公司
Marcin Kowalewski, Synopsys, Inc.
Myoungbo Kwak, Samsung Electronics, Co.
Luke Lai, NVIDIA
托馬斯·朗格,東芝公司
劉偉強,ATI 科技公司
Ed Liu, NVIDIA
托馬斯·馬里克,比特眼數位測試解決方案有限公司
大衛·梅爾策,精工愛普生公司。
帕特里克·莫恩,德州儀器公司
馬庫斯·穆勒,諾基亞公司
拉吉·庫馬爾·納格帕爾,Synopsys, Inc.
中田晃、精工愛普生公司
Long Nguyen, Mixel, Inc.
Jim Ohannes, National Semiconductor
Upneet Pannu, NVIDIA
喬奧·佩雷拉,Synopsys, Inc.
哈羅德·佩里克,NXP 半導體
Tim Pontius, NXP Semiconductor
杜安·奎特,英特爾公司
Parthasarathy Raju, Tektronix, Inc
Juha Rakkola, Nokia Corporation
吉姆·里皮,IEEE-ISTO(員工)
拉文德拉·魯德拉拉朱,英特爾公司
Victor Sanchez-Rico, BitifEye Digital Test Solutions GmbH
Jose Sarmento, Synopsys, Inc.
Roland Scherzinger, Keysight Technologies Inc.
DC Sessions, NXP Semiconductor
Sridhar Shashidharan, Arasan Chip Systems, Inc.
Sergio Silva, Synopsys Inc 比爾·西姆斯,NVIDIA
Vikas Sinha, 德州儀器公司
Ian Jackson, Silicon Line GmbH Ahmed Shaban, Mixel, Inc.
詹姆斯·贾西,英特爾公司
Tatsuya Sugioka, Sony Corporation
Ashraf Takla, Mixel, Inc.
Aravind Vijayakumar, Cadence Design Systems, Inc.