解決爭用情況的程序。D-PHY 包含數種偵測 Link 爭用的機制。然而,某些爭用情況只能在較高層級偵測到,因此並未包含在本規格中。
確保不同 Lane Module 類型之間的連接操作正常。有多種不同的 Lane Module 類型,可最佳支援多種應用的不同功能需求。這表示除了一些基本功能之外,還可以包含或排除一些可選功能。本規格僅確保匹配的 Lane Module 類型之間的連接操作正確,也就是說:支援相同特性且功能互補的模組。如果車道的兩側並非相同類型,而這些車道應該可以正確運作,則車道模組的製造商應確保所提供的附加功能不會損壞運作。若能以其他獨立於 MIPI D-PHY 介面的方式停用附加功能,使 Lane 模組的行為與相同類型的 Lane 模組無異,則最易達到此目的。
IO 的 ESD 保護等級。所需的等級取決於特定的應用環境和產品類型。
精確的 Bit-Error-Rate (BER) 值。實現的 BER 的實際值取決於整體系統整合和環境的敵對程度。因此,不可能為 Link 的個別部分指定 BER。本規格允許實作的 BER 為 < 10^(-12)<10^{-12} 。
Version 2.0 Specification for D-PHY
23-Nov-2015
144 Mbps Megabits per second
145 MSB Most Significant Bit
146 PHY Physical Layer
147 PLL Phase-Locked Loop
148 PPI PHY-Protocol Interface
149 RF Radio Frequency
150 RX Receiver
151 SE Single-Ended
152 SoT Start of Transmission
153 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master
154 and Slave
155 TX Transmitter
156 UI Unit Interval, equal to the duration of any HS state on the Clock Lane
157 ULPS Ultra-Low Power State| | Version 2.0 | Specification for D-PHY |
| :--- | :--- | :--- |
| | 23-Nov-2015 | |
| 144 | Mbps | Megabits per second |
| 145 | MSB | Most Significant Bit |
| 146 | PHY | Physical Layer |
| 147 | PLL | Phase-Locked Loop |
| 148 | PPI | PHY-Protocol Interface |
| 149 | RF | Radio Frequency |
| 150 | RX | Receiver |
| 151 | SE | Single-Ended |
| 152 | SoT | Start of Transmission |
| 153 | TLIS | Transmission-Line Interconnect Structure: physical interconnect realization between Master |
| 154 | | and Slave |
| 155 | TX | Transmitter |
| 156 | UI | Unit Interval, equal to the duration of any HS state on the Clock Lane |
| 157 | ULPS | Ultra-Low Power State |
D-PHY 描述一種來源同步、高速、低耗電、低成本的 PHY,特別適用於行動應用。此 D-PHY 規格主要是針對相機與顯示應用程式與主機處理器的連接而撰寫。然而,它也可應用於許多其他應用。我們預期同類型的 PHY 也會用在雙重複合配置中,用於更一般的通訊網路互連。由於 Link 兩側之間的主從關係,因此 Link 的操作和可用資料速率是不對稱的。非對稱的設計大大降低了 Link 的複雜性。某些功能(如雙向、半雙工操作)是可選的。對於有非對稱資料流量需求的應用,以及回傳通道的獨立互連成本過高時,利用此功能會很有吸引力。雖然這項功能是可選的,但對於沒有回傳流量需求或想要應用物理上不同的回傳通訊通道的應用,它可以避免強制性的開銷成本。
4.1 PHY 功能摘要
D-PHY 提供 Master 和 Slave 之間的同步連線。實用的 PHY 組態包含一個時脈信號和一個或多個資料信號。時脈信號是單向的,從主端開始,到從端結束。資料信號可以是單向或雙向,視所選的選項而定。對於半雙工操作,反向頻寬是正向頻寬的四分之一。令牌傳遞用於控制 Link 的通訊方向。
Link 包括用於快速資料通訊的 High-Speed 信令模式和用於控制目的的 Low-Power 信令模式。低功率逃逸模式可選擇用於低速異步資料通訊。高速資料通訊以具有任意數量有效負載資料位元組的 burst 形式出現。
PHY 的每個資料通道使用兩條線,加上時脈通道的兩條線。這樣,最小的 PHY 配置就有四條線。在高速模式下,每條 Lane 都在兩側端接,並由低搖擺、差動訊號驅動。在低功耗模式下,所有線路都是單端操作且無端線。基於 EMI 的理由,此模式的驅動器應採用壓縮率控制和電流限制。
PHY 組態包含一個時脈 Lane 模組和一個或多個資料 Lane 模組。每個 PHY Lane 模組透過兩條線與 Lane 互連另一端的互補零件通訊。
每個 Lane 模組包含一個或多個同時使用兩條互連線的差動高速功能、一個或多個在每條互連線上單獨操作的單端低功耗功能,以及控制和介面邏輯。所有功能的概覽如圖 1 所示。高速信號的電壓擺幅較低,例如 200 mV,而低功率信號的電壓擺幅較大,例如 1.2V。高速功能用於高速資料傳輸。低功耗功能主要用於控制,但也有其他可選的使用情況。I/O 功能由 Lane Control and Interface Logic 區塊控制。此區塊與通訊協定連接,並決定 Lane 模組的全局操作。
高速功能包括差分傳送器 (HS-TX) 和差分接收器 (HS-RX)。
一個 Lane 模組可能包含 HS-TX、HS-RX 或兩者。在正常操作期間,單一 Lane 模組中的 HS-TX 和 HS-RX 絕不會同時啟用。啟用的高速功能應根據第 9.1.1 節和第 9.2.1 節的定義,終止其一端的 Lane 互連。如果一個
Lane
Interconnect Side| Lane |
| :--- |
| Interconnect Side |
高速性能
支援的前向逃逸模式功能
Forward
Direction Escape Mode Features Supported| Forward |
| :--- |
| Direction Escape Mode Features Supported |
支援的反向 Escape 模式功能 ^(1){ }^{1}
Reverse
Direction Escape
Mode Features Supported ^(1)| Reverse |
| :--- |
| Direction Escape |
| Mode Features Supported ${ }^{1}$ |
CIL-
M - 主人 S - 奴隸 X - 無所謂
M - Master
S - Slave
X - Don't Care| M - Master |
| :--- |
| S - Slave |
| X - Don't Care |
F - 僅正向 RR - 反向和正向X - 無所謂 ^(2){ }^{2}
F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)| F - Forward Only |
| :--- |
| $R$ - Reverse and Forward |
| X - Don't Care ${ }^{2}$ |
A - 全部(包括 LPDT) E - 僅限事件觸發器和 ULPS X - 不關心
A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care| A - All (including LPDT) |
| :--- |
| E - events Triggers and ULPS Only X - Don't Care |
A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock
N - 不適用
N - 不適用
Prefix "Lane
Interconnect Side" High-Speed Capabilities "Forward
Direction Escape Mode Features Supported" "Reverse
Direction Escape
Mode Features Supported ^(1)"
CIL- "M - Master
S - Slave
X - Don't Care" "F - Forward Only
R - Reverse and Forward
X - Don't Care ^(2)" "A - All (including LPDT)
E - events Triggers and ULPS Only X - Don't Care" A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care
C-Clock N - Not Applicable N - Not Applicable| Prefix | Lane <br> Interconnect Side | High-Speed Capabilities | Forward <br> Direction Escape Mode Features Supported | Reverse <br> Direction Escape <br> Mode Features Supported ${ }^{1}$ |
| :---: | :---: | :---: | :---: | :---: |
| CIL- | M - Master <br> S - Slave <br> X - Don't Care | F - Forward Only <br> $R$ - Reverse and Forward <br> X - Don't Care ${ }^{2}$ | A - All (including LPDT) <br> E - events Triggers and ULPS Only X - Don't Care | ```A - All (including LPDT) E-events - Triggers and ULPS Only N - None Y - Any (A, E, or A and E) X - Don't Care``` |
| | | C-Clock | N - Not Applicable | N - Not Applicable |
請注意:
「任意 」是一個或多個功能的任意組合。
僅對資料車道有效,表示「F」或「R」。
建議的 PHY 通訊協定介面包含位元組格式的資料輸入(Data-in)和資料輸出(Data-out)、輸入和/或輸出時鐘訊號以及控制訊號。控制信號包括請求、握手、測試設定和初始化。附件 A 中描述了邏輯內部介面的建議。儘管並非必要,但使用建議的 PPI 可能非常有用。對於 IC 的外部使用,實作可以在相同的引腳上多路複用許多訊號。然而,基於電源效率的理由,PPI 通常是在 IC 內。
Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)| Supported Directions for Escape mode including LPDT |
| :--- |
| (Bi-directional, Forward Only or Reverse Only) |
rarr\rightarrow
larr\leftarrow
時脈方向 (依定義從 Master 到 Slave,必須指向與「Clock Only Lane」箭頭相同的方向)
Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)| Clock Direction |
| :--- |
| (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
PPI:PHY-通訊協定介面
This Other Options Meaning
C1CCCCCCC1 https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=93&width=153&top_left_y=1703&top_left_x=792 Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional)
C1[I-][In][IH]1 C1C[I-][I-]1 Clock Lane
longleftrightarrow longrightarrow Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only)
⊮ longrightarrow ⋙≪ "Supported Directions for Escape mode including LPDT
(Bi-directional, Forward Only or Reverse Only)"
rarr larr "Clock Direction
(by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow)"
https://cdn.mathpix.com/cropped/2024_12_07_47a3926ad0b042cab51dg-026.jpg?height=85&width=86&top_left_y=2267&top_left_x=607 PPI: PHY-Protocol Interface| This | Other Options | Meaning |
| :---: | :---: | :---: |
| <smiles>C1CCCCCCC1</smiles> |  | Supported Directions for High-Speed Data Transmission (Bi-directional or Unidirectional) |
| <smiles>C1[I-][In][IH]1</smiles> | <smiles>C1C[I-][I-]1</smiles> | Clock Lane |
| $\longleftrightarrow$ | $\longrightarrow$ | Supported Directions for Escape mode excluding LPDT (Bi-directional or Forward Only) |
| $\nVdash \longrightarrow$ | $\ggg \ll$ | Supported Directions for Escape mode including LPDT <br> (Bi-directional, Forward Only or Reverse Only) |
| $\rightarrow$ | $\leftarrow$ | Clock Direction <br> (by definition from Master to Slave, must point in the same direction as the "Clock Only Lane" arrow) |
|  | | PPI: PHY-Protocol Interface |
圖 5 車道符號巨集與符號圖例
對於多重資料車道,可以有多種不同的配置。圖 6 顯示不同 Lane 類型的符號表示概觀。每個 Lane 種類所提到的縮寫以簡短的方式表示每個模組的功能。這也設定了每個模組內 CIL 功能的需求。
此組態包括一條時鐘通道(Clock Lane)和多條雙向資料通道(Data Lane)。每個單獨的 Lane 都可以正向和反向進行通訊。最大可用頻寬會隨著每個方向的 Lane 數量而增加。PHY 規格並不要求所有資料通道同時啟動,甚至不要求在同一方向上操作。事實上,通訊協定層會個別控制所有資料通道。圖 11 顯示兩個資料通道的配置範例。如果 N 是資料通道的數量,此配置需要 2**(N+1)2 *(\mathrm{~N}+1) 互連線。
傳送器功能透過驅動特定的線路電平來決定 Lane 狀態。在正常操作期間,HS-TX 或 LP-TX 會驅動一個 Lane。HS-TX 始終以差分方式驅動 Lane。兩個 LPTX 則獨立單端驅動一 Lane 的兩條 Line。這導致兩種可能的高速 Lane 狀態和四種可能的低功耗 Lane 狀態。高速 Lane 狀態為 Differential-0 和 Differential-1。低功耗 Lane 狀態的解釋取決於操作模式。LP 接收器應始終將兩個高速差分狀態解釋為 LP-00。
州法
線路電壓等級
高速
低功耗
Dp-Line
Dn-Line
連拍模式
控制模式
逃離模式
HS-0
HS 低
HS 高
差分-0
不適用,註 1
不適用,註 1
HS-1
HS 高
HS 低
差分-1
不適用,註 1
不適用,註 1
LP-00
LP 低
LP 低
不適用
橋樑
空間
LP-01
LP 低
LP 高
不適用
HS-Rqst
Mark-0
LP-10
LP 高
LP 低
不適用
LP-Rqst
Mark-1
LP-11
LP 高
LP 高
不適用
停止
不適用,附註 2
State Code Line Voltage Levels High-Speed Low-Power
Dp-Line Dn-Line Burst Mode Control Mode Escape Mode
HS-0 HS Low HS High Differential-0 N/A, Note 1 N/A, Note 1
HS-1 HS High HS Low Differential-1 N/A, Note 1 N/A, Note 1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Rqst Mark-0
LP-10 LP High LP Low N/A LP-Rqst Mark-1
LP-11 LP High LP High N/A Stop N/A, Note 2| State Code | Line Voltage Levels | | High-Speed | | Low-Power |
| :--- | :--- | :--- | :--- | :--- | :--- |
| | Dp-Line | Dn-Line | Burst Mode | Control Mode | Escape Mode |
| HS-0 | HS Low | HS High | Differential-0 | N/A, Note 1 | N/A, Note 1 |
| HS-1 | HS High | HS Low | Differential-1 | N/A, Note 1 | N/A, Note 1 |
| LP-00 | LP Low | LP Low | N/A | Bridge | Space |
| LP-01 | LP Low | LP High | N/A | HS-Rqst | Mark-0 |
| LP-10 | LP High | LP Low | N/A | LP-Rqst | Mark-1 |
| LP-11 | LP High | LP High | N/A | Stop | N/A, Note 2 |
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
驅動電橋狀態 (LP-00) 的時間 THS-PREPARE
觀察線路從 LP-01 到 LP-00 的轉換,在 TD-TERM-EN 時間後啟用線路終止。
Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN| Observes transition form LP-01 to LP-00 on the |
| :--- |
| Lines, enables Line Termination after time TD-TERM-EN |
Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THS-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
驅動 HS-0 一段時間 THS-ZERO
開始尋找領袖序列
識別到領導序列 'O11101' 時進行同步
Synchronizes upon recognition of Leader Sequence
'O11101'| Synchronizes upon recognition of Leader Sequence |
| :--- |
| 'O11101' |
在時鐘上升沿
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Rqst state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time THS-PREPARE "Observes transition form LP-01 to LP-00 on the
Lines, enables Line Termination after time TD-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously." "Enables HS-RX and waits for timer THS-SETTLE to
expire in order to neglect transition effects"
Drives HS-0 for a time THS-ZERO Starts looking for Leader-Sequence
"Synchronizes upon recognition of Leader Sequence
'O11101'"
on a rising Clock edge | TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time THS-PREPARE | Observes transition form LP-01 to LP-00 on the <br> Lines, enables Line Termination after time TD-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. | Enables HS-RX and waits for timer THS-SETTLE to <br> expire in order to neglect transition effects |
| Drives HS-0 for a time THS-ZERO | Starts looking for Leader-Sequence |
| | Synchronizes upon recognition of Leader Sequence <br> 'O11101' |
| on a rising Clock edge | |
保留所有權利。
6.4.3 傳輸結束
TX 側
RX 側
完成傳輸有效載荷資料
接收有效負載資料
在最後一個有效負載資料位元之後立即切換差動狀態,並將該狀態維持一段時間 THS-TRAIL
Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL| Toggles differential state immediately after last |
| :--- |
| payload data bit and keeps that state for a time |
| THS-TRAIL |
停用 HS-TX,啟用 LP-TX,並驅動停止狀態 (LP-11) 一段時間 THS-EXIT
Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables the LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination| Detects the Lines leaving LP-00 state and entering |
| :--- |
| Stop state (LP-11) and disables Termination |
忽略最後一期 THS-SKIP 的位元,以隱藏轉換效果
Neglect bits of last period THS-SKIP to hide transition
effects| Neglect bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
偵測有效資料的最後一次轉換,決定最後有效的資料位元組,並跳過預告序列
Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence| Detect last transition in valid Data, determine last |
| :--- |
| valid Data byte and skip trailer sequence |
TX Side RX Side
Completes Transmission of payload data Receives payload data
"Toggles differential state immediately after last
payload data bit and keeps that state for a time
THS-TRAIL"
"Disables the HS-TX, enables the LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines leaving LP-00 state and entering
Stop state (LP-11) and disables Termination"
"Neglect bits of last period THS-SKIP to hide transition
effects"
"Detect last transition in valid Data, determine last
valid Data byte and skip trailer sequence"| TX Side | RX Side |
| :--- | :--- |
| Completes Transmission of payload data | Receives payload data |
| Toggles differential state immediately after last <br> payload data bit and keeps that state for a time <br> THS-TRAIL | |
| Disables the HS-TX, enables the LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines leaving LP-00 state and entering <br> Stop state (LP-11) and disables Termination |
| | Neglect bits of last period THS-SKIP to hide transition <br> effects |
| | Detect last transition in valid Data, determine last <br> valid Data byte and skip trailer sequence |
State "Line
Condition/State" Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr End of timed interval TLPX
TX-HS-Prpr Transmit LP-00 TX-HS-Go End of timed interval THS-PREPARE
TX-HS-Go Transmit HS-0 TX-HS-Sync End of timed interval THS-zERO
TX-HS-Sync "Transmit
sequence
HS-00011101" TX-HS-0 After Sync sequence if first payload data bit is 0
TX-HS-1 After Sync sequence if first payload data bit is 1
TX-HS-0 Transmit HS-0 TX-HS-0 Send another HS-0 bit after a HS-0 bit
TX-HS-1 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Transmit HS-1 TX-HS-0 Send a HS-1 bit after a HS-0 bit
TX-HS-1 Send another HS-1 bit after a HS-1
Trail-HS-0 Last payload bit is HS-1, trailer sequence is HS-0
Trail-HS-0 Transmit HS-0 TX-Stop End of timed interval THS-TRAlL
Trail-HS-1 Transmit HS-1 TX-Stop End of timed interval THS-TRAlL
RX-Stop Receive LP-11 RX-HS-Rqst Line transition to LP-01
RX- HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval TLPX |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval THS-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-Sync | End of timed interval THS-zERO |
| TX-HS-Sync | Transmit <br> sequence <br> HS-00011101 | TX-HS-0 | After Sync sequence if first payload data bit is 0 |
| | | TX-HS-1 | After Sync sequence if first payload data bit is 1 |
| TX-HS-0 | Transmit HS-0 | TX-HS-0 | Send another HS-0 bit after a HS-0 bit |
| | | TX-HS-1 | Send a HS-1 bit after a HS-0 bit |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-1 bit after a HS-0 bit |
| | | TX-HS-1 | Send another HS-1 bit after a HS-1 |
| | | Trail-HS-0 | Last payload bit is HS-1, trailer sequence is HS-0 |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval THS-TRAlL |
| Trail-HS-1 | Transmit HS-1 | TX-Stop | End of timed interval THS-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX- HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
國家
線狀態/狀態
Line
Condition/State| Line |
| :---: |
| Condition/State |
Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data.| Proper match found (any single bit error allowed if |
| :--- |
| deskew calibration feature is not used) for Sync |
| sequence in HS stream, the following bits are |
| payload data. |
RX-HS-1
RX-HS-0
接收 HS-0
RX-HS-0
接收有效負載資料位元或拖曳位元
RX-HS-1
RX-HS-1
接收 HS-1
RX-HS-0
接收有效負載資料位元或拖曳位元
RX-HS-1
RX-Stop
線路轉換至 LP-11
State "Line
Condition/State" Exit State Exit Conditions
RX-HS- Prpr Receive LP-00 RX-HS-Term End of timed interval TD-TERM-EN
RX-HS-Term Receive LP-00 RX-HS-Sync End of timed interval THS-SETTLE
RX-HS-Sync "Receive HS
sequence
...00000011101" RX-HS-0 "Proper match found (any single bit error allowed if
deskew calibration feature is not used) for Sync
sequence in HS stream, the following bits are
payload data."
RX-HS-1
RX-HS-0 Receive HS-0 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-HS-1 Receive HS-1 RX-HS-0 Receive payload data bit or trailer bit
RX-HS-1
RX-Stop Line transition to LP-11| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS- Prpr | Receive LP-00 | RX-HS-Term | End of timed interval TD-TERM-EN |
| RX-HS-Term | Receive LP-00 | RX-HS-Sync | End of timed interval THS-SETTLE |
| RX-HS-Sync | Receive HS <br> sequence <br> ...00000011101 | RX-HS-0 | Proper match found (any single bit error allowed if <br> deskew calibration feature is not used) for Sync <br> sequence in HS stream, the following bits are <br> payload data. |
| | | RX-HS-1 | |
| RX-HS-0 | Receive HS-0 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| RX-HS-1 | Receive HS-1 | RX-HS-0 | Receive payload data bit or trailer bit |
| | | RX-HS-1 | |
| | | RX-Stop | Line transition to LP-11 |
Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control.| Observes the transition from LP-10 to Bridge state |
| :--- |
| and waits for a time TAA-SURE. After correct |
| completion of this time-out this side knows it is in |
| control. |
停止驅動線路,並使用 LP-RX 觀察線路狀態,以查看確認。
Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement.| Stops driving the Lines and observes the Line states |
| :--- |
| with its LP-RX in order to see an acknowledgement. |
Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure.| Observes LP-10 on the Lines, interprets this as |
| :--- |
| acknowledge that the other side has indeed taken |
| control. Waits for Stop state to complete Turnaround |
| procedure. |
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Drives Stop state (LP-11) Observes Stop state
Drives LP-Rqst state (LP-10) for a time TLPX Observes transition from LP-11 to LP-10 states
Drives Bridge state (LP-00) for a time T TPX Observes transition from LP-10 to LP-00 states
Drives LP-10 for a time T TPX Observes transition from LP-00 to LP-10 states
Drives Bridge state (LP-00) for a time TTA-GO "Observes the transition from LP-10 to Bridge state
and waits for a time TAA-SURE. After correct
completion of this time-out this side knows it is in
control."
"Stops driving the Lines and observes the Line states
with its LP-RX in order to see an acknowledgement." Drives Bridge state (LP-00) for a period TTA-GET
Drives LP-10 for a period TLPX
"Observes LP-10 on the Lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete Turnaround
procedure." | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives LP-Rqst state (LP-10) for a time TLPX | Observes transition from LP-11 to LP-10 states |
| Drives Bridge state (LP-00) for a time T TPX | Observes transition from LP-10 to LP-00 states |
| Drives LP-10 for a time T TPX | Observes transition from LP-00 to LP-10 states |
| Drives Bridge state (LP-00) for a time TTA-GO | Observes the transition from LP-10 to Bridge state <br> and waits for a time TAA-SURE. After correct <br> completion of this time-out this side knows it is in <br> control. |
| Stops driving the Lines and observes the Line states <br> with its LP-RX in order to see an acknowledgement. | Drives Bridge state (LP-00) for a period TTA-GET |
| | Drives LP-10 for a period TLPX |
| Observes LP-10 on the Lines, interprets this as <br> acknowledge that the other side has indeed taken <br> control. Waits for Stop state to complete Turnaround <br> procedure. | |
初始 TX 端 = 最終 RX 端
初始 RX 端 = 最終 TX 端
觀察轉換至停止狀態 (LP-11) 上的
行,將此解釋為 Turnaround 完成
確認,切換到正常的 LP 接收
模式,並等待其他
旁邊
Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Observes transition to Stop state (LP-11) on the
Lines, interprets this as Turnaround completion
acknowledgement, switches to normal LP receive
mode and waits for further actions from the other
side | Initial TX Side = Final RX Side | Initial RX Side = Final TX Side |
| :--- | :--- |
| Observes transition to Stop state (LP-11) on the | |
| Lines, interprets this as Turnaround completion | |
| acknowledgement, switches to normal LP receive | |
| mode and waits for further actions from the other | |
| side | |
Line
Condition/State| Line |
| :---: |
| Condition/State |
退出狀態
退出條件
任何 RX 狀態
任何收到
RX-Stop
在線上觀察 LP-11
TX 停止
傳輸 LP-11
TX-LP-Rqst
依據《轉彎規約》的要求
TX-LP-Rqst
傳輸 LP-10
TX-LP-Yield
定時間隔結束 TLPX
TX-LP-Yield
傳輸 LP-00
TX-TA-Rqst
定時間隔結束 TLPX
TX-TA-Rqst
傳輸 LP-10
TX-TA-Go
定時間隔結束 TLPX
TX-TA-Go
傳輸 LP-00
RX-TA-Look
計時間結束 TTA-GO
RX-TA-Look
接收 LP-00
RX-TA-Ack
線路轉換至 LP-10
RX-TA-Ack
接收 LP-10
RX-Stop
線路轉換至 LP-11
RX-Stop
接收 LP-11
RX-LP-Rqst
線路轉換至 LP-10
RX-LP-Rqst
接收 LP-10
RX-LP-Yield
線路轉換至 LP-00
RX-LP-Yield
接收 LP-00
RX-TA-Rqst
線路轉換至 LP-10
RX-TA-Rqst
接收 LP-10
RX-TA-Wait
線路轉換至 LP-00
RX-TA-Wait
接收 LP-00
TX-TA-Get
計時間結束 TTA-SURE
TX-TA-Get
傳輸 LP-00
TX-TA-Ack
計時間結束 TTA-GET
TX-TA-Ack
Transit LP-10
TX 停止
定時間隔結束 TLPX
State "Line
Condition/State" Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Turnaround
TX-LP-Rqst Transmit LP-10 TX-LP-Yield End of timed interval TLPX
TX-LP-Yield Transmit LP-00 TX-TA-Rqst End of timed interval TLPX
TX-TA-Rqst Transmit LP-10 TX-TA-Go End of timed interval TLPX
TX-TA-Go Transmit LP-00 RX-TA-Look End of timed interval TTA-GO
RX-TA-Look Receive LP-00 RX-TA-Ack Line transition to LP-10
RX-TA-Ack Receive LP-10 RX-Stop Line transition to LP-11
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-TA-Rqst Line transition to LP-10
RX-TA-Rqst Receive LP-10 RX-TA-Wait Line transition to LP-00
RX-TA-Wait Receive LP-00 TX-TA-Get End of timed interval TTA-SURE
TX-TA-Get Transmit LP-00 TX-TA-Ack End of timed interval TTA-GET
TX-TA-Ack Transit LP-10 TX-Stop End of timed interval TLPX| State | Line <br> Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Turnaround |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | End of timed interval TLPX |
| TX-LP-Yield | Transmit LP-00 | TX-TA-Rqst | End of timed interval TLPX |
| TX-TA-Rqst | Transmit LP-10 | TX-TA-Go | End of timed interval TLPX |
| TX-TA-Go | Transmit LP-00 | RX-TA-Look | End of timed interval TTA-GO |
| RX-TA-Look | Receive LP-00 | RX-TA-Ack | Line transition to LP-10 |
| RX-TA-Ack | Receive LP-10 | RX-Stop | Line transition to LP-11 |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-TA-Rqst | Line transition to LP-10 |
| RX-TA-Rqst | Receive LP-10 | RX-TA-Wait | Line transition to LP-00 |
| RX-TA-Wait | Receive LP-00 | TX-TA-Get | End of timed interval TTA-SURE |
| TX-TA-Get | Transmit LP-00 | TX-TA-Ack | End of timed interval TTA-GET |
| TX-TA-Ack | Transit LP-10 | TX-Stop | End of timed interval TLPX |
Spaced-One-Hot 編碼是指每個 Mark 狀態與 Space 狀態交錯。因此,每個符號由兩部分組成:一個 One-Hot 階段(Mark-0 或 Mark-1)和一個 Space 階段。TX 應發送 Mark-0 之後的 Space 來傳送「零位元」,並應發送 Mark-1 之後的 Space 來傳送「一位元」。沒有跟隨空格的 Mark 不代表一個位元。在以 Stop 狀態離開 Escape 模式之前的最後一個階段應該是 Mark-1 狀態,由於它後面沒有 Space 狀態,所以不屬於通訊位元的一部分。時脈(Clock)可透過一個 exclusive-OR 函數從兩個 Line 訊號 Dp 和 Dn 得到。每個獨立 LP 狀態週期的長度至少應為 T_("LPX,MIN ")\mathrm{T}_{\text {LPX,MIN }} 。
逃生模式動作
指令類型
輸入指令樣式(傳送的第一個位元到傳送的最後一個位元)
Entry Command Pattern (first
bit transmitted to last bit
transmitted)| Entry Command Pattern (first |
| :---: |
| bit transmitted to last bit |
| transmitted) |
低功耗資料傳輸
模式
11100001
超低功耗狀態
模式
00011110
未定義-1
模式
10011111
未定義-2
模式
11011110
重設-觸發器
Reset-Trigger| Reset-Trigger |
| :--- |
觸發器
01100010
HS 測試模式的輸入順序
觸發器
01011101
未知-4
觸發器
00100001
未知-5
觸發器
10100000
Escape Mode Action Command Type "Entry Command Pattern (first
bit transmitted to last bit
transmitted)"
Low-Power Data Transmission mode 11100001
Ultra-Low Power State mode 00011110
Undefined-1 mode 10011111
Undefined-2 mode 11011110
"Reset-Trigger" Trigger 01100010
Entry sequence for HS Test Mode Trigger 01011101
Unknown-4 Trigger 00100001
Unknown-5 Trigger 10100000| Escape Mode Action | Command Type | Entry Command Pattern (first <br> bit transmitted to last bit <br> transmitted) |
| :--- | :--- | :---: |
| Low-Power Data Transmission | mode | 11100001 |
| Ultra-Low Power State | mode | 00011110 |
| Undefined-1 | mode | 10011111 |
| Undefined-2 | mode | 11011110 |
| Reset-Trigger | Trigger | 01100010 |
| Entry sequence for HS Test Mode | Trigger | 01011101 |
| Unknown-4 | Trigger | 00100001 |
| Unknown-5 | Trigger | 10100000 |
如果在 Escape mode Entry 指令之後傳送 Ultra-Low Power State Entry 指令,Lane 應進入 Ultra-Low Power State (ULPS)。此命令應標記到接收端通訊協定。在此狀態期間,線路處於空間狀態 (LP-00)。超低功耗狀態(Ultra-Low Power State)是透過一個長度為 Twakeup 的 Mark-1 狀態(Mark-1 State)退出,接著是一個 Stop 狀態(Stop State)。附件 A 描述了退出程序的範例,以及控制 Mark-1 狀態時間長度的程序。
6.6.4 逃脫模式狀態機
Escape 模式操作的狀態機如圖 20 所示,並在表 9 中描述。
註: 水平對齊的狀態會同時出現。
圖 20 逃脫模式狀態機
表 9 逃脫模式狀態機說明
國家
線狀態/狀態
退出狀態
退出條件
任何 RX 狀態
任何收到
RX-Stop
在線上觀察 LP-11
TX 停止
傳輸 LP-11
TX-LP-Rqst
應 Esc 模式 (PPI) 協定的要求
TX-LP-Rqst
傳輸 LP-10
TX-LP-Yield
經過時間 T_("LPX ")\mathrm{T}_{\text {LPX }} 之後
TX-LP-Yield
傳輸 LP-00
TX-Esc-Rqst
時間 T TPX 之後
TX-Esc-Rqst
傳輸 LP-01
TX-Esc-Go
時間 T LPX^("a ")\mathrm{LPX}^{\text {a }} 之後
TX-Esc-Go
傳輸 LP-00
TX-Esc-Cond
時間 T TPX 之後
TX-Esc-Cmd
傳送 8 位元(16 行狀態)單步進熱編碼輸入指令序列
TX-Triggers
觸發指令之後
TX-ULPS
超低功率指令之後
TX-LPDT
低功率資料傳輸指令之後
After Low-Power Data
Transmission Command| After Low-Power Data |
| :--- |
| Transmission Command |
TX-Triggers
空間狀態或用於產生時鐘的可選虛擬位元組
TX 標記
依據通訊協定 (PPI) 的要求退出觸發狀態
TX-ULPS
傳輸 LP-00
TX 標記
應議定書 (PPI) 的要求結束 ULP 狀態
State Line Condition/State Exit State Exit Conditions
Any RX state Any Received RX-Stop Observe LP-11 at Lines
TX-Stop Transmit LP-11 TX-LP-Rqst On request of Protocol for Esc mode (PPI)
TX-LP-Rqst Transmit LP-10 TX-LP-Yield After time T_("LPX ")
TX-LP-Yield Transmit LP-00 TX-Esc-Rqst After time T TPX
TX-Esc-Rqst Transmit LP-01 TX-Esc-Go After time T LPX^("a ")
TX-Esc-Go Transmit LP-00 TX-Esc-Cond After time T TPX
TX-Esc-Cmd Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command TX-Triggers After a Trigger Command
TX-ULPS After Ultra-Low Power Command
TX-LPDT "After Low-Power Data
Transmission Command"
TX-Triggers Space state or optional dummy bytes for the purpose of generating clocks TX-Mark Exit of the Trigger State on request of Protocol (PPI)
TX-ULPS Transmit LP-00 TX-Mark End of ULP State on request of Protocol (PPI)| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| Any RX state | Any Received | RX-Stop | Observe LP-11 at Lines |
| TX-Stop | Transmit LP-11 | TX-LP-Rqst | On request of Protocol for Esc mode (PPI) |
| TX-LP-Rqst | Transmit LP-10 | TX-LP-Yield | After time $\mathrm{T}_{\text {LPX }}$ |
| TX-LP-Yield | Transmit LP-00 | TX-Esc-Rqst | After time T TPX |
| TX-Esc-Rqst | Transmit LP-01 | TX-Esc-Go | After time T $\mathrm{LPX}^{\text {a }}$ |
| TX-Esc-Go | Transmit LP-00 | TX-Esc-Cond | After time T TPX |
| TX-Esc-Cmd | Transmit sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | TX-Triggers | After a Trigger Command |
| | | TX-ULPS | After Ultra-Low Power Command |
| | | TX-LPDT | After Low-Power Data <br> Transmission Command |
| TX-Triggers | Space state or optional dummy bytes for the purpose of generating clocks | TX-Mark | Exit of the Trigger State on request of Protocol (PPI) |
| TX-ULPS | Transmit LP-00 | TX-Mark | End of ULP State on request of Protocol (PPI) |
State Line Condition/State Exit State Exit Conditions
TX-LPDT Transmit serialized, Spaced-One-Hot encoded payload data After last transmitted data bit
TX-Mark Mark-1 TX-Stop Next driven state after time T_("LPX "), or T_("WAKEUP ") if leaving ULP State
RX-Stop Receive LP-11 RX-LP-Rqst Line transition to LP-10
RX-LP-Rqst Receive LP-10 RX-LP-Yield Line transition to LP-00
RX-LP-Yield Receive LP-00 RX-Esc-Rqst Line transition to LP-01
RX-Esc-Rqst Receive LP-01 RX-Esc-Go Line transition to LP-00
RX-Esc-Go Receive LP-00 RX-Esc-Cmd Line transition out of LP-00
RX-Esc-Cmd Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command RX-Wait After Trigger and Unrecognized Commands
RX-ULPS After Ultra-Low Power Command
RX-LPDT After Low-Power Data Transmission Command
RX-ULPS Receive LP-00 RX-Wait Line transition to LP-10
RX-LPDT Receive serial, Spaced-One-Hot encoded payload data RX-Stop Line transition to LP-11 (Last state should be a Mark-1)
RX-Wait Any, except LP-11 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :---: | :---: | :---: | :---: |
| TX-LPDT | Transmit serialized, Spaced-One-Hot encoded payload data | | After last transmitted data bit |
| TX-Mark | Mark-1 | TX-Stop | Next driven state after time $\mathrm{T}_{\text {LPX }}$, or $\mathrm{T}_{\text {WAKEUP }}$ if leaving ULP State |
| RX-Stop | Receive LP-11 | RX-LP-Rqst | Line transition to LP-10 |
| RX-LP-Rqst | Receive LP-10 | RX-LP-Yield | Line transition to LP-00 |
| RX-LP-Yield | Receive LP-00 | RX-Esc-Rqst | Line transition to LP-01 |
| RX-Esc-Rqst | Receive LP-01 | RX-Esc-Go | Line transition to LP-00 |
| RX-Esc-Go | Receive LP-00 | RX-Esc-Cmd | Line transition out of LP-00 |
| RX-Esc-Cmd | Receive sequence of 8-bit (16-line-states) One-Spaced-Hot encoded Entry Command | RX-Wait | After Trigger and Unrecognized Commands |
| | | RX-ULPS | After Ultra-Low Power Command |
| | | RX-LPDT | After Low-Power Data Transmission Command |
| RX-ULPS | Receive LP-00 | RX-Wait | Line transition to LP-10 |
| RX-LPDT | Receive serial, Spaced-One-Hot encoded payload data | RX-Stop | Line transition to LP-11 (Last state should be a Mark-1) |
| RX-Wait | Any, except LP-11 | RX-Stop | Line transition to LP-11 |
Drives High-Speed Clock signal (Toggling
HS-0/HS-1)| Drives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
接收高速時脈訊號(切換 HS-0/HS-1)。
Receives High-Speed Clock signal (Toggling
HS-0/HS-1)| Receives High-Speed Clock signal (Toggling |
| :--- |
| HS-0/HS-1) |
最後一個資料通道進入低功耗模式
繼續驅動高速時脈信號一段時間 TcLK-Post,並以 HS-0 狀態結束
Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state| Continues to drives High-Speed Clock signal for a |
| :--- |
| period TcLK-Post and ends with HS-0 state |
偵測在 TcLK-MISs 時間內沒有時脈轉換,停用 HS-RX,然後等待轉換至停止狀態
Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state| Detects absence of Clock transitions within a time |
| :--- |
| TcLK-MISs, disables HS-RX then waits for a transition |
| to the Stop state |
驅動 HS-0 一段時間 TcLK-TRAIL
停用 HS-TX,啟用 LP-TX,並驅動停止狀態 (LP-11) 一段時間 THS-EXIT
Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT| Disables the HS-TX, enables LP-TX, and drives |
| :--- |
| Stop state (LP-11) for a time THS-EXIT |
偵測線路轉換至 LP-11,停用 HS 終止,並進入停止狀態
Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state| Detects the Lines transitions to LP-11, disables HS |
| :--- |
| termination, and enters Stop state |
Master Side Slave Side
"Drives High-Speed Clock signal (Toggling
HS-0/HS-1)" "Receives High-Speed Clock signal (Toggling
HS-0/HS-1)"
Last Data Lane goes into Low-Power mode
"Continues to drives High-Speed Clock signal for a
period TcLK-Post and ends with HS-0 state" "Detects absence of Clock transitions within a time
TcLK-MISs, disables HS-RX then waits for a transition
to the Stop state"
Drives HS-0 for a time TcLK-TRAIL
"Disables the HS-TX, enables LP-TX, and drives
Stop state (LP-11) for a time THS-EXIT" "Detects the Lines transitions to LP-11, disables HS
termination, and enters Stop state"
| Master Side | Slave Side |
| :--- | :--- |
| Drives High-Speed Clock signal (Toggling <br> HS-0/HS-1) | Receives High-Speed Clock signal (Toggling <br> HS-0/HS-1) |
| Last Data Lane goes into Low-Power mode | |
| Continues to drives High-Speed Clock signal for a <br> period TcLK-Post and ends with HS-0 state | Detects absence of Clock transitions within a time <br> TcLK-MISs, disables HS-RX then waits for a transition <br> to the Stop state |
| Drives HS-0 for a time TcLK-TRAIL | |
| Disables the HS-TX, enables LP-TX, and drives <br> Stop state (LP-11) for a time THS-EXIT | Detects the Lines transitions to LP-11, disables HS <br> termination, and enters Stop state |
| | |
表 11 啟動高速時脈傳輸的程序
TX 側
RX 側
驅動器停止狀態 (LP-11)
觀察停止狀態
驅動時間 TLPX 的 HS-Req 狀態 (LP-01)
觀察線路從 LP-11 到 LP-01 的過渡情況
Observes transition from LP-11 to LP-01 on the
Lines| Observes transition from LP-11 to LP-01 on the |
| :--- |
| Lines |
Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN| Observes transition from LP-01 to LP-00 on the |
| :--- |
| Lines. Enables Line Termination after time |
| TcLK-TERM-EN |
同時啟用高速驅動器和停用低功耗驅動器。驅動 HS-0 的時間為 TCLK-ZERO。
Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO.| Enables High-Speed driver and disables Low-Power |
| :--- |
| drivers simultaneously. Drives HS-0 for a time |
| TCLK-ZERO. |
啟用 HS-RX,並等待計時器 TcLK-SETTLE 過期,以忽略轉換效應
Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer TcLK-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
接收 HS 訊號
在任何資料通道啟動之前,驅動高速時脈信號一段時間 TcLK-PRE
Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up| Drives the High-Speed Clock signal for time period |
| :--- |
| TcLK-PRE before any Data Lane starts up |
接收高速時脈訊號
TX Side RX Side
Drives Stop state (LP-11) Observes Stop state
Drives HS-Req state (LP-01) for time TLPX "Observes transition from LP-11 to LP-01 on the
Lines"
Drives Bridge state (LP-00) for time TcLK-PREPARE "Observes transition from LP-01 to LP-00 on the
Lines. Enables Line Termination after time
TcLK-TERM-EN"
"Enables High-Speed driver and disables Low-Power
drivers simultaneously. Drives HS-0 for a time
TCLK-ZERO." "Enables HS-RX and waits for timer TcLK-SETTLE to
expire in order to neglect transition effects"
Receives HS-signal
"Drives the High-Speed Clock signal for time period
TcLK-PRE before any Data Lane starts up" Receives High-Speed Clock signal| TX Side | RX Side |
| :--- | :--- |
| Drives Stop state (LP-11) | Observes Stop state |
| Drives HS-Req state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the <br> Lines |
| Drives Bridge state (LP-00) for time TcLK-PREPARE | Observes transition from LP-01 to LP-00 on the <br> Lines. Enables Line Termination after time <br> TcLK-TERM-EN |
| Enables High-Speed driver and disables Low-Power <br> drivers simultaneously. Drives HS-0 for a time <br> TCLK-ZERO. | Enables HS-RX and waits for timer TcLK-SETTLE to <br> expire in order to neglect transition effects |
| | Receives HS-signal |
| Drives the High-Speed Clock signal for time period <br> TcLK-PRE before any Data Lane starts up | Receives High-Speed Clock signal |
Clock Lane 狀態機如圖 22 所示,並在表 12 中說明。
註: 水平對齊的狀態會同時出現。
圖 22 高速時脈傳輸狀態機
表 12 高速時脈傳輸狀態機描述
國家
線狀態/狀態
退出狀態
退出條件
TX 停止
傳輸 LP-11
TX-HS-Rqst
應高速傳輸協定的要求
On request of Protocol
for High-Speed
Transmission| On request of Protocol |
| :--- |
| for High-Speed |
| Transmission |
TX-HS-Rqst
傳輸 LP-01
TX-HS-Prpr
定時間隔結束 TLPx
End of timed interval
TLPx| End of timed interval |
| :--- |
| TLPx |
TX-HS-Prpr
傳輸 LP-00
TX-HS-Go
定時間隔結束 TcLK-PREPARE
End of timed interval
TcLK-PREPARE| End of timed interval |
| :--- |
| TcLK-PREPARE |
TX-HS-Go
傳輸 HS-0
TX-HS-1
定時間隔結束 TcLK-ZERO
End of timed interval
TcLK-ZERO| End of timed interval |
| :--- |
| TcLK-ZERO |
TX-HS-0
傳輸 HS-0
TX-HS-1
在 HS-0 相位後傳送 HS-1 相位:DDR 時脈
Send a HS-1 phase after
a HS-0 phase: DDR
Clock| Send a HS-1 phase after |
| :--- |
| a HS-0 phase: DDR |
| Clock |
TX-HS-1
傳輸 HS-1
TX-HS-0
在 HS-1 相位後傳送 HS-0 相位:DDR 時脈
Send a HS-0 phase after
a HS-1 phase: DDR
Clock| Send a HS-0 phase after |
| :--- |
| a HS-1 phase: DDR |
| Clock |
Trail-HS-0
根據要求將時鐘巷置於低功耗狀態
On request to put Clock
Lane in Low-Power| On request to put Clock |
| :--- |
| Lane in Low-Power |
Trail-HS-0
傳輸 HS-0
TX 停止
定時間隔結束 TcLK-TRAlL
End of timed interval
TcLK-TRAlL| End of timed interval |
| :--- |
| TcLK-TRAlL |
RX-Stop
接收 LP-11
RX-HS-Rqst
線路轉換至 LP-01
Line transition to LP-01| Line transition to LP-01 |
| :--- |
RX-HS-Rqst
接收 LP-01
RX-HS-Prpr
線路轉換至 LP-00
RX-HS-Prpr
接收 LP-00
RX-HS-Term
定時間隔結束 TcLK-TERM-EN
End of timed interval
TcLK-TERM-EN| End of timed interval |
| :--- |
| TcLK-TERM-EN |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-HS-Rqst "On request of Protocol
for High-Speed
Transmission"
TX-HS-Rqst Transmit LP-01 TX-HS-Prpr "End of timed interval
TLPx"
TX-HS-Prpr Transmit LP-00 TX-HS-Go "End of timed interval
TcLK-PREPARE"
TX-HS-Go Transmit HS-0 TX-HS-1 "End of timed interval
TcLK-ZERO"
TX-HS-0 Transmit HS-0 TX-HS-1 "Send a HS-1 phase after
a HS-0 phase: DDR
Clock"
TX-HS-1 Transmit HS-1 TX-HS-0 "Send a HS-0 phase after
a HS-1 phase: DDR
Clock"
Trail-HS-0 "On request to put Clock
Lane in Low-Power"
Trail-HS-0 Transmit HS-0 TX-Stop "End of timed interval
TcLK-TRAlL"
RX-Stop Receive LP-11 RX-HS-Rqst "Line transition to LP-01"
RX-HS-Rqst Receive LP-01 RX-HS-Prpr Line transition to LP-00
RX-HS-Prpr Receive LP-00 RX-HS-Term "End of timed interval
TcLK-TERM-EN"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-HS-Rqst | On request of Protocol <br> for High-Speed <br> Transmission |
| TX-HS-Rqst | Transmit LP-01 | TX-HS-Prpr | End of timed interval <br> TLPx |
| TX-HS-Prpr | Transmit LP-00 | TX-HS-Go | End of timed interval <br> TcLK-PREPARE |
| TX-HS-Go | Transmit HS-0 | TX-HS-1 | End of timed interval <br> TcLK-ZERO |
| TX-HS-0 | Transmit HS-0 | TX-HS-1 | Send a HS-1 phase after <br> a HS-0 phase: DDR <br> Clock |
| TX-HS-1 | Transmit HS-1 | TX-HS-0 | Send a HS-0 phase after <br> a HS-1 phase: DDR <br> Clock |
| | | Trail-HS-0 | On request to put Clock <br> Lane in Low-Power |
| Trail-HS-0 | Transmit HS-0 | TX-Stop | End of timed interval <br> TcLK-TRAlL |
| RX-Stop | Receive LP-11 | RX-HS-Rqst | Line transition to LP-01 |
| RX-HS-Rqst | Receive LP-01 | RX-HS-Prpr | Line transition to LP-00 |
| RX-HS-Prpr | Receive LP-00 | RX-HS-Term | End of timed interval <br> TcLK-TERM-EN |
國家
線狀態/狀態
退出狀態
退出條件
RX-HS-Term
接收 LP-00
RX-HS-Clk
定時間隔結束 TCLK-SETTLE
End of timed interval
TCLK-SETTLE| End of timed interval |
| :--- |
| TCLK-SETTLE |
Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions| Time-out TCLK-MISs on the |
| :--- |
| period on the Clock |
| Lane without Clock |
| signal transitions |
RX-HS-End
接收 HS-0
RX-HS-Stop
線路轉換至 LP-11
State Line Condition/State Exit State Exit Conditions
RX-HS-Term Receive LP-00 RX-HS-Clk "End of timed interval
TCLK-SETTLE"
RX-HS-Clk "Receive DDR-Q Clock
signal" RX-Clk-End "Time-out TCLK-MISs on the
period on the Clock
Lane without Clock
signal transitions"
RX-HS-End Receive HS-0 RX-HS-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| RX-HS-Term | Receive LP-00 | RX-HS-Clk | End of timed interval <br> TCLK-SETTLE |
| RX-HS-Clk | Receive DDR-Q Clock <br> signal | RX-Clk-End | Time-out TCLK-MISs on the <br> period on the Clock <br> Lane without Clock <br> signal transitions |
| RX-HS-End | Receive HS-0 | RX-HS-Stop | Line transition to LP-11 |
請注意:
在高速資料傳輸期間,停止狀態(TX-Stop、RX-Stop)有多個有效的離開狀態。
6.8 時脈通道超低功耗狀態
雖然 Clock Lane 不包含一般 Escape 模式,但 Clock Lane 應支援 Ultra-Low Power State。
Clock Lane(時脈車道)應透過 Clock Lane Ultra-Low Power State Entry(時脈車道超低功耗狀態進入)程序進入 Ultra-Low Power State(超低功耗狀態)。在此程序中,從停止狀態開始,傳輸端應驅動 TX-ULPS-Rqst 狀態 (LP-10),然後驅動 TX-ULPS 狀態 (LP-00)。之後,時脈通道 (Clock Lane) 應進入超低功耗狀態 (Ultra-Low Power State)。如果發生錯誤,且在 TX-ULPS-Rqst 狀態之後立即偵測到 LP-01 或 LP-11,則超低功耗狀態進入程序應中止,接收端應分別等待或返回 Stop 狀態。
On request of Protocol
for Ultra-Low Power
State| On request of Protocol |
| :--- |
| for Ultra-Low Power |
| State |
TX-ULPS-Rqst
傳輸 LP-10
TX-ULPS
定時間隔結束 TLPX
End of timed interval
TLPX| End of timed interval |
| :--- |
| TLPX |
State Line Condition/State Exit State Exit Conditions
TX-Stop Transmit LP-11 TX-ULPS-Rqst "On request of Protocol
for Ultra-Low Power
State"
TX-ULPS-Rqst Transmit LP-10 TX-ULPS "End of timed interval
TLPX"| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-Stop | Transmit LP-11 | TX-ULPS-Rqst | On request of Protocol <br> for Ultra-Low Power <br> State |
| TX-ULPS-Rqst | Transmit LP-10 | TX-ULPS | End of timed interval <br> TLPX |
國家
線狀態/狀態
退出狀態
退出條件
TX-ULPS
傳輸 LP-00
TX-ULPS-Exit
根據協議要求離開超低功耗狀態
On request of Protocol
to leave Ultra-Low
Power State| On request of Protocol |
| :--- |
| to leave Ultra-Low |
| Power State |
TX-ULPS-Exit
傳輸 LP-10
TX 停止
計時間結束 TwakEuP
End of timed interval
TwakEuP| End of timed interval |
| :--- |
| TwakEuP |
RX-Stop
接收 LP-11
RX-ULPS-Rqst
線路轉換至 LP-10
RX-ULPS-Rqst
接收 LP-10
RX-ULPS
線路轉換至 LP-00
RX-ULPS
接收 LP-00
RX-ULPS-Exit
線路轉換至 LP-10
RX-ULPS-Exit
接收 LP-10
RX-Stop
線路轉換至 LP-11
State Line Condition/State Exit State Exit Conditions
TX-ULPS Transmit LP-00 TX-ULPS-Exit "On request of Protocol
to leave Ultra-Low
Power State"
TX-ULPS-Exit Transmit LP-10 TX-Stop "End of timed interval
TwakEuP"
RX-Stop Receive LP-11 RX-ULPS-Rqst Line transition to LP-10
RX-ULPS-Rqst Receive LP-10 RX-ULPS Line transition to LP-00
RX-ULPS Receive LP-00 RX-ULPS-Exit Line transition to LP-10
RX-ULPS-Exit Receive LP-10 RX-Stop Line transition to LP-11| State | Line Condition/State | Exit State | Exit Conditions |
| :--- | :--- | :--- | :--- |
| TX-ULPS | Transmit LP-00 | TX-ULPS-Exit | On request of Protocol <br> to leave Ultra-Low <br> Power State |
| TX-ULPS-Exit | Transmit LP-10 | TX-Stop | End of timed interval <br> TwakEuP |
| RX-Stop | Receive LP-11 | RX-ULPS-Rqst | Line transition to LP-10 |
| RX-ULPS-Rqst | Receive LP-10 | RX-ULPS | Line transition to LP-00 |
| RX-ULPS | Receive LP-00 | RX-ULPS-Exit | Line transition to LP-10 |
| RX-ULPS-Exit | Receive LP-10 | RX-Stop | Line transition to LP-11 |
Parameter Description Min Typ Max Unit Notes
Tclk-miss Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. 60 ns 1,6,8
Tclk-Post Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of T_("HS-trall ") to the beginning of Tclk-trall. 60 ns + 52*UI ns 5
Tclu-pre Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 8 UI 5
Tclk-prepare Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 38 95 ns 5
Tclk-settle Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. 95 300 ns 6, 7
Tclk-term-en Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. "Time for Dn to reach
Vterm-en" 38 ns 6
Tclk-trall Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 60 ns 5
Tclk-Prepare + Tclk-Zero Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. 300 ns 5
Td-TERM-EN Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses V_(IL,MAX). Time for Dn to reach V_("term-en ") 35 ns +4 * U 6
Teot Transmitted time interval from the start of T_("HS-TRAIL ") or T_("CLK-TRALL "), to the start of the LP-11 state following a HS burst. 105 ns + n12UI 3,5
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Tclk-miss | Timeout for receiver to detect absence of Clock transitions and disable the Clock Lane HS-RX. | | | 60 | ns | 1,6,8 |
| Tclk-Post | Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of $T_{\text {HS-trall }}$ to the beginning of Tclk-trall. | 60 ns + 52*UI | | | ns | 5 |
| Tclu-pre | Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. | 8 | | | UI | 5 |
| Tclk-prepare | Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. | 38 | | 95 | ns | 5 |
| Tclk-settle | Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of Tclk-prepare. | 95 | | 300 | ns | 6, 7 |
| Tclk-term-en | Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,max. | Time for Dn to reach <br> Vterm-en | | 38 | ns | 6 |
| Tclk-trall | Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. | 60 | | | ns | 5 |
| Tclk-Prepare + Tclk-Zero | Tclk-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. | 300 | | | ns | 5 |
| Td-TERM-EN | Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses $V_{I L, M A X}$. | Time for Dn to reach $V_{\text {term-en }}$ | | 35 ns +4 * U | | 6 |
| Teot | Transmitted time interval from the start of $\mathrm{T}_{\text {HS-TRAIL }}$ or $\mathrm{T}_{\text {CLK-TRALL }}$, to the start of the LP-11 state following a HS burst. | | | 105 ns + n*12*UI | | 3,5 |
| THS-EXIT | Time that the transmitter drives LP-11 following a HS burst. | 100 | | | ns | 5 |
參數
說明
最小值
類型
最大值
單位
注意事項
準備
傳送器在 HS-0 Line 狀態開始 HS 傳輸前驅動資料通道 LP-00 Line 狀態的時間
40ns+440 \mathrm{~ns}+4 * Ul
85 ns + 6* UI
ns
5
Ths-PRepare + Ths-zero
ThS-PREPARE + 傳送器在傳送 Sync 序列前驅動 HS-0 狀態的時間。
145 ns + 10*UI
ns
5
栓塞
從 ThS-PRepare 開始,HS 接收器忽略任何 Data Lane HS 轉換的時間間隔。HS 接收器應忽略最小值之前的任何資料巷轉換,而 HS 接收器應回應最大值之後的任何資料巷轉換。
Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value.| Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. |
| :--- |
| The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. |
LPX(MASTER) 的比率 ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ")^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}
2/3
3/2
Tta-get
在 Link Turnaround 期間,新傳送器在接受控制後驅動 Bridge 狀態 (LP-00) 的時間。
5*TLPX
ns
5
Tta-go
在 Link Turnaround 期間,傳送器在釋放控制之前驅動 Bridge 狀態 (LP-00) 的時間。
4*TLPX
ns
5
Tta-sure
在 Link Turnaround 期間,新傳送器在 LP-10 狀態之後,等待傳送 Bridge 狀態 (LP-00) 的時間。
TLPX
2*TLPX
ns
5
喚醒
發射器在停止狀態之前驅動 Mark-1 狀態以啟動退出 ULPS 的時間。
1
毫秒
5
Parameter Description Min Typ Max Unit Notes
Ths-Prepare Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission 40ns+4 * Ul 85 ns + 6* UI ns 5
Ths-PRepare + Ths-zero ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns 5
Ths-settle "Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value." 85ns+6 * Ul 145 ns + 10*UI ns 6
THS-SKIP Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 40 55 ns +4 * Ul ns 6
Ths-trall Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst "max(n**8^(**)UI,:}
{: 60(ns)+n^(**)4**UI)" ns 2,3,5
Tinit See Section 6.11. 100 us 5
TLPX Transmitted length of any Low-Power state period 50 ns 4,5
Ratio TLPX Ratio of LPX(MASTER) ^("T "T_("LPX(SLAVE) ")" between Master and Slave side ") 2/3 3/2
Tta-get Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. 5*TLPX ns 5
Tta-go Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. 4*TLPX ns 5
Tta-sure Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. TLPX 2*TLPX ns 5
Twakeup Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. 1 ms 5| Parameter | Description | Min | Typ | Max | Unit | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Ths-Prepare | Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission | $40 \mathrm{~ns}+4$ * Ul | | 85 ns + 6* UI | ns | 5 |
| Ths-PRepare + Ths-zero | ThS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. | 145 ns + 10*UI | | | ns | 5 |
| Ths-settle | Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of ThS-PRepare. <br> The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value. | $85 \mathrm{~ns}+6$ * Ul | | 145 ns + 10*UI | ns | 6 |
| THS-SKIP | Time interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. | 40 | | 55 ns +4 * Ul | ns | 6 |
| Ths-trall | Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst | $\begin{gathered} \max \left(\mathrm{n*} 8^{*} \mathrm{UI},\right. \\ \left.60 \mathrm{~ns}+\mathrm{n}^{*} 4 * \mathrm{UI}\right) \end{gathered}$ | | | ns | 2,3,5 |
| Tinit | See Section 6.11. | 100 | | | us | 5 |
| TLPX | Transmitted length of any Low-Power state period | 50 | | | ns | 4,5 |
| Ratio TLPX | Ratio of LPX(MASTER) $^{\text {T } T_{\text {LPX(SLAVE) }} \text { between Master and Slave side }}$ | 2/3 | | 3/2 | | |
| Tta-get | Time that the new transmitter drives the Bridge state (LP-00) after accepting control during a Link Turnaround. | 5*TLPX | | | ns | 5 |
| Tta-go | Time that the transmitter drives the Bridge state (LP-00) before releasing control during a Link Turnaround. | 4*TLPX | | | ns | 5 |
| Tta-sure | Time that the new transmitter waits after the LP-10 state before transmitting the Bridge state (LP-00) during a Link Turnaround. | TLPX | | 2*TLPX | ns | 5 |
| Twakeup | Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an exit from ULPS. | 1 | | | ms | 5 |
Any LP level
except Stop States
for periods >100us| Any LP level |
| :--- |
| except Stop States |
| for periods >100us |
Master Init
開機或通訊協定請求
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
TX 停止
長於通訊協定所指定的 TinIT,MASTER 的 First Stop 狀態
A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol| A First Stop state |
| :--- |
| for a period longer |
| than TinIT,MASTER as |
| specified by the |
| Protocol |
任何以長初始化停止狀態結束的 LP 訊號序列
Any LP signaling
sequence that
ends with a long
Initialization Stop
state| Any LP signaling |
| :--- |
| sequence that |
| ends with a long |
| Initialization Stop |
| state |
從屬關閉
斷電
任何 LP 國家
開機
任何
從站啟動
開機或通訊協定請求
Power-up or
Protocol request| Power-up or |
| :--- |
| Protocol request |
RX-Stop
觀察輸入端的停止狀態一段時間 TinIT,SLAVE(如協定所規定)。
Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol| Observe Stop state |
| :--- |
| at the inputs for a |
| period TinIT,SLAVE as |
| specified by the |
| Protocol |
以第一個長初始化停止週期結束的任何 LP 訊號序列
Any LP signaling
sequence which
ends with the first
long Initialization
Stop period| Any LP signaling |
| :--- |
| sequence which |
| ends with the first |
| long Initialization |
| Stop period |
State Entry Conditions Exit State Exit Conditions Line Levels
Master Off Power-down Master Initialization Power-up "Any LP level
except Stop States
for periods >100us"
Master Init "Power-up or
Protocol request" TX-Stop "A First Stop state
for a period longer
than TinIT,MASTER as
specified by the
Protocol" "Any LP signaling
sequence that
ends with a long
Initialization Stop
state"
Slave Off Power-down Any LP state Power-up Any
Slave Init "Power-up or
Protocol request" RX-Stop "Observe Stop state
at the inputs for a
period TinIT,SLAVE as
specified by the
Protocol" "Any LP signaling
sequence which
ends with the first
long Initialization
Stop period"| State | Entry Conditions | Exit State | Exit Conditions | Line Levels |
| :--- | :--- | :--- | :--- | :--- |
| Master Off | Power-down | Master Initialization | Power-up | Any LP level <br> except Stop States <br> for periods >100us |
| Master Init | Power-up or <br> Protocol request | TX-Stop | A First Stop state <br> for a period longer <br> than TinIT,MASTER as <br> specified by the <br> Protocol | Any LP signaling <br> sequence that <br> ends with a long <br> Initialization Stop <br> state |
| Slave Off | Power-down | Any LP state | Power-up | Any |
| Slave Init | Power-up or <br> Protocol request | RX-Stop | Observe Stop state <br> at the inputs for a <br> period TinIT,SLAVE as <br> specified by the <br> Protocol | Any LP signaling <br> sequence which <br> ends with the first <br> long Initialization <br> Stop period |
TX Side RX Side
Drives stop state (LP-11) Observes stop state
Drives HS-Rqst state (LP-01) for time TLPX Observes transition from LP-11 to LP-01 on the lines| TX Side | RX Side |
| :--- | :--- |
| Drives stop state (LP-11) | Observes stop state |
| Drives HS-Rqst state (LP-01) for time TLPX | Observes transition from LP-11 to LP-01 on the lines |
Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)| Observes transition from LP-01 to LP-00 on the |
| :--- |
| lines, and enables line termination after time |
| TD-TERMEN $^{\mid}$ |
Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects| Enables HS-RX and waits for timer THs-SETTLE to |
| :--- |
| expire in order to neglect transition effects |
開始尋找領導序列
插入高速同步序列以進行高速偏移校正:'11111111_11111111',從時脈上升沿開始。
Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge| Inserts the high-speed sync sequence for high- |
| :--- |
| speed skew-calibration: '11111111_11111111' |
| beginning on a rising clock edge |
識別到領導序列時進行同步:'1111_1111
Synchronizes upon recognition of leader sequence:
'1111_1111'| Synchronizes upon recognition of leader sequence: |
| :--- |
| '1111_1111' |
接收 '01010101' 資料
Receives '01010101' data| Receives '01010101' data |
| :--- |
繼續傳輸與時鐘通道相同的高速資料:'01010101
Continues to transmit high speed data that is the
same as the clock lane: '01010101'| Continues to transmit high speed data that is the |
| :--- |
| same as the clock lane: '01010101' |
執行時脈與資料通道間的高速偏移校正
Performs high-speed skew-calibration between clock
and data lanes| Performs high-speed skew-calibration between clock |
| :--- |
| and data lanes |
完成時脈與資料通道間的高速偏移校正
Finishes high-speed skew-calibration between clock
and data lanes| Finishes high-speed skew-calibration between clock |
| :--- |
| and data lanes |
TX Side RX Side
Drives bridge state (LP-00) for time THS-PREPARE "Observes transition from LP-01 to LP-00 on the
lines, and enables line termination after time
TD-TERMEN ^(∣)"
"Simultaneously enables high-speed driver and
disables low-power drivers"
Drives HS-0 for a time THS-ZERO "Enables HS-RX and waits for timer THs-SETTLE to
expire in order to neglect transition effects"
Starts looking for leader sequence
"Inserts the high-speed sync sequence for high-
speed skew-calibration: '11111111_11111111'
beginning on a rising clock edge" "Synchronizes upon recognition of leader sequence:
'1111_1111'"
"Receives '01010101' data"
"Continues to transmit high speed data that is the
same as the clock lane: '01010101'" "Performs high-speed skew-calibration between clock
and data lanes"
"Finishes high-speed skew-calibration between clock
and data lanes"
| TX Side | RX Side |
| :--- | :--- |
| Drives bridge state (LP-00) for time THS-PREPARE | Observes transition from LP-01 to LP-00 on the <br> lines, and enables line termination after time <br> TD-TERMEN $^{\mid}$ |
| Simultaneously enables high-speed driver and <br> disables low-power drivers | |
| Drives HS-0 for a time THS-ZERO | Enables HS-RX and waits for timer THs-SETTLE to <br> expire in order to neglect transition effects |
| | Starts looking for leader sequence |
| Inserts the high-speed sync sequence for high- <br> speed skew-calibration: '11111111_11111111' <br> beginning on a rising clock edge | Synchronizes upon recognition of leader sequence: <br> '1111_1111' |
| | Receives '01010101' data |
| Continues to transmit high speed data that is the <br> same as the clock lane: '01010101' | Performs high-speed skew-calibration between clock <br> and data lanes |
| | Finishes high-speed skew-calibration between clock <br> and data lanes |
| | |
Neglects bits of last period THS-SKIP to hide transition
effects| Neglects bits of last period THS-SKIP to hide transition |
| :--- |
| effects |
偵測有效資料的最後一次轉換、決定最後一個有效資料位元組並跳過預告序列
Detects last transition of valid data, determines last
valid data byte and skip trailer sequence| Detects last transition of valid data, determines last |
| :--- |
| valid data byte and skip trailer sequence |
開始尋找領導序列
TX Side RX Side
Completes transmission of '01010101' data Receives '01010101' data
"Toggles differential state immediately after last
payload data bit and holds that state for a time
THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXIT""Detects the lines leaving LP-00 state and entering
the stop state (LP-11), and disables termination"
"Neglects bits of last period THS-SKIP to hide transition
effects"
"Detects last transition of valid data, determines last
valid data byte and skip trailer sequence"
Starts looking for leader sequence| TX Side | RX Side |
| :--- | :--- |
| Completes transmission of '01010101' data | Receives '01010101' data |
| Toggles differential state immediately after last <br> payload data bit and holds that state for a time <br> THS-TRAIL {f03c6eb09-97e3-4aa5-a372-4bbf76546346}the stop state (LP-11) for a time THS-EXITDetects the lines leaving LP-00 state and entering <br> the stop state (LP-11), and disables termination | |
| | Neglects bits of last period THS-SKIP to hide transition <br> effects |
| | Detects last transition of valid data, determines last <br> valid data byte and skip trailer sequence |
| | Starts looking for leader sequence |
Time that the transmitter drives the skew-
calibration sync pattern, FFFFH| Time that the transmitter drives the skew- |
| :--- |
| calibration sync pattern, FFFFH |
16
UI
TSKEWCAL
傳送器在初始偏斜校正模式下驅動偏斜校正模式的時間
Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the initial skew- |
| calibration mode |
100
mus\mu \mathrm{~s}
2^(15)2^{15}
UI
TSKEWCAL
TSKEWCAL| TSKEWCAL |
| :--- |
在週期性偏斜校正模式中,傳送器驅動偏斜校正模式的時間
Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode| Time that the transmitter drives the skew- |
| :--- |
| calibration pattern in the periodic skew- |
| calibration mode |
10
mus\mu \mathrm{~s}
UI
Parameter Description Min Typ Max Unit Notes
TSKEWCAL_SYNC "Time that the transmitter drives the skew-
calibration sync pattern, FFFFH" 16 UI
TSKEWCAL "Time that the transmitter drives the skew-
calibration pattern in the initial skew-
calibration mode" 100 mus
2^(15) UI
"TSKEWCAL" "Time that the transmitter drives the skew-
calibration pattern in the periodic skew-
calibration mode" 10 mus
UI | Parameter | Description | Min | Typ | Max | Unit | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| TSKEWCAL_SYNC | Time that the transmitter drives the skew- <br> calibration sync pattern, FFFFH | | 16 | | UI | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the initial skew- <br> calibration mode | | | 100 | $\mu \mathrm{~s}$ | |
| | $2^{15}$ | | | UI | | |
| TSKEWCAL | Time that the transmitter drives the skew- <br> calibration pattern in the periodic skew- <br> calibration mode | | | 10 | $\mu \mathrm{~s}$ | |
| | | | | UI | | |
Output impedance of LP
transmitter| Output impedance of LP |
| :--- |
| transmitter |
110
Omega\Omega
3,4
Parameter Description Min Nom Max Units Notes
VOH_(OH) Thevenin output high level 1.1 1.2 1.3 V 1
0.95 1.3 V 2
VOL Thevenin output low level -50 50 mV
ZoLP "Output impedance of LP
transmitter" 110 Omega 3,4| Parameter | Description | Min | Nom | Max | Units | Notes |
| :--- | :--- | :---: | :---: | :---: | :---: | :---: |
| $\mathrm{VOH}_{\mathrm{OH}}$ | Thevenin output high level | 1.1 | 1.2 | 1.3 | V | 1 |
| | | 0.95 | | 1.3 | V | 2 |
| VOL | Thevenin output low level | -50 | | 50 | mV | |
| ZoLP | Output impedance of LP <br> transmitter | 110 | | | $\Omega$ | 3,4 |
請注意:
當支援的資料傳輸率 <= 1.5\leq 1.5 Gbps 時適用。
當支援的資料傳輸率 > 1.5>1.5 Gbps 時適用。
請參閱圖 48 和圖 49。
雖然沒有指定 ZoLP 的最大值,但 LP 發送器輸出阻抗應確保符合 T_(RLP)//T_(FLP)T_{R L P} / T_{F L P} 規格。
表 23 LP 變送器 AC 規格
參數
說明
最小值
名稱
最大值
單位
注意事項
TrLP/TfLP
15%-85% 上升時間和下降時間
25
ns
1
特雷奧特
30%-85% 上升時間和下降時間
35
ns
5,6
TLP-PuLSE-TX
LP exclusive-OR 時脈寬度
Pulse width of the LP
exclusive-OR clock| Pulse width of the LP |
| :--- |
| exclusive-OR clock |
Stop 狀態後的第一個 LP exclusive-OR 時脈或 Stop 狀態前的最後一個時脈
First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state| First LP |
| :--- |
| exclusive-OR |
| clock pulse after |
| Stop state or last pulse before Stop state |
40
ns
4
所有其他脈衝
20
ns
4
TLP-PER-TX
LP exclusive-OR 時鐘的週期
90
ns
deltaV// bar(" tsR ")\delta \mathrm{V} / \overline{\text { tsR }}
脈衝速率 @ Cload = 0pF
500
mV/ns
1, 3, 7, 8
脈衝速率 @ Cload = 5pF
300
mV//ns\mathrm{mV/ns}
1, 3, 7, 8
脈衝速率 @ Cload = 20pF
250
mV//ns\mathrm{mV/ns}
1, 3, 7, 8
脈衝速率 @ ClOAd = 70pF
150
mV//ns\mathrm{mV} / \mathrm{ns}
1, 3, 7, 8
擺動速率 @ Cload =0=0 至 70pF(僅限下降沿)
30
mV//ns\mathrm{mV/ns}
1, 2, 3, 12
25
mV/ns
1, 3, 13, 16
Parameter Description Min Nom Max Units Notes
TrLP/TfLP 15%-85% rise time and fall time 25 ns 1
Treot 30%-85% rise time and fall time 35 ns 5,6
TLP-PuLSE-TX "Pulse width of the LP
exclusive-OR clock" "First LP
exclusive-OR
clock pulse after
Stop state or last pulse before Stop state" 40 ns 4
All other pulses 20 ns 4
TLP-PER-TX Period of the LP exclusive-OR clock 90 ns
deltaV// bar(" tsR ") Slew rate @ Cload = 0pF 500 mV/ns 1, 3, 7, 8
Slew rate @ Cload = 5pF 300 mV//ns 1, 3, 7, 8
Slew rate @ Cload = 20pF 250 mV//ns 1, 3, 7, 8
Slew rate @ ClOAd = 70pF 150 mV//ns 1, 3, 7, 8
Slew rate @ Cload =0 to 70pF (Falling Edge Only) 30 mV//ns 1, 2, 3, 12
25 mV/ns 1, 3, 13, 16| Parameter | Description | | Min | Nom | Max | Units | Notes |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| TrLP/TfLP | 15%-85% rise time and fall time | | | | 25 | ns | 1 |
| Treot | 30%-85% rise time and fall time | | | | 35 | ns | 5,6 |
| TLP-PuLSE-TX | Pulse width of the LP <br> exclusive-OR clock | First LP <br> exclusive-OR <br> clock pulse after <br> Stop state or last pulse before Stop state | 40 | | | ns | 4 |
| | | All other pulses | 20 | | | ns | 4 |
| TLP-PER-TX | Period of the LP exclusive-OR clock | | 90 | | | ns | |
| $\delta \mathrm{V} / \overline{\text { tsR }}$ | Slew rate @ Cload = 0pF | | | | 500 | mV/ns | 1, 3, 7, 8 |
| | Slew rate @ Cload = 5pF | | | | 300 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload = 20pF | | | | 250 | $\mathrm{mV/ns}$ | 1, 3, 7, 8 |
| | Slew rate @ ClOAd = 70pF | | | | 150 | $\mathrm{mV} / \mathrm{ns}$ | 1, 3, 7, 8 |
| | Slew rate @ Cload $=0$ to 70pF (Falling Edge Only) | | 30 | | | $\mathrm{mV/ns}$ | 1, 2, 3, 12 |
| | | | 25 | | | mV/ns | 1, 3, 13, 16 |
通訊協定和 D-PHY 會根據表 38 所述,選擇最適合操作的資料路徑寬度。匯流排寬度選擇基於邏輯二進位輸入,如 TxDataWidthHS[1:0] 和 RxDataWidthHS[1:0] 所說明。匯流排寬度可以在目前的序列完成後,根據操作需求修改。一個 IC 中傳送功能的 PPI 資料路徑寬度不一定要與另一個 IC 中接收功能的 PPI 資料路徑寬度一致。無論 PPI Tx 和 Rx 資料路徑的寬度為何,D-PHY 都能傳送和接收任何大於零的整數字。每組透過 PPI 傳輸的資料都附有一組資料驗證訊號,以顯示哪些字包含要傳輸的有效資料,或哪些字包含實際從通道接收的資料。
本節中的所有時序圖都是指一個位元組匯流排寬度的情況。
表 38 PPI 訊號
符號
總監
類別
說明
高速傳輸訊號
TxDDRCIkHS-I
1
MXXX
MCNN
MXXX
MCNN| MXXX |
| :--- |
| MCNN |
資料列高速傳輸 DDR 時脈。此訊號用於透過 Lane 互連傳輸高速資料位元。所有資料巷使用相同的 TxDDRCIkHS-I(同相)時脈訊號。
Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal.| Data Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
TxDDRCIkHS-Q
I
MCNN
Clock Lane High-Speed Transmit DDR Clock(時脈通道高速傳輸 DDR 時脈)。此訊號用於產生 Lane Interconnect 的高速時脈訊號。TxDDRCIkHS-Q (正交) 時鐘信號與 TxDDRCIkHS-I 時鐘信號相移。
Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal.| Clock Lane High-Speed Transmit DDR Clock. |
| :--- |
| This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate.| High-Speed Transmit Word Clock. |
| :--- |
| This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: |
| - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. |
| - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. |
| - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Transmit Data bus Width Select. |
| :--- |
| Selects the bus width of TxDataHS: |
| - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. |
| - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] |
| - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] |
| - TxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit.| High-Speed Transmit Data bus width. |
| :--- |
| High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: |
| - 8-bit width - TxDataHS[7:0] |
| - 16-bit width - TxDataHS[15:0] |
| - 32-bit width - TxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
Symbol Dir Categories Description
High-Speed Transmit Signals
TxDDRCIkHS-I 1 "MXXX
MCNN" "Data Lane High-Speed Transmit DDR Clock.
This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal."
TxDDRCIkHS-Q I MCNN "Clock Lane High-Speed Transmit DDR Clock.
This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal."
TxWordCIkHS 0 "MXXX
SRXX" "High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows:
- 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly 1//8 the high-speed data rate.
- 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly 1//16 the high-speed data rate.
- 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly 1//32 the high-speed data rate."
TxDataWidthHS[1:0] I " MXXX
SRXX " "High-Speed Transmit Data bus Width Select.
Selects the bus width of TxDataHS:
- TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0].
- TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0]
- TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0]
- TxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] I "MXXX
SRXX" "High-Speed Transmit Data bus width.
High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path:
- 8-bit width - TxDataHS[7:0]
- 16-bit width - TxDataHS[15:0]
- 32-bit width - TxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| High-Speed Transmit Signals | | | |
| TxDDRCIkHS-I | 1 | MXXX <br> MCNN | Data Lane High-Speed Transmit DDR Clock. <br> This signal is used to transmit High-Speed data bits over the Lane Interconnect. All Data Lanes use the same TxDDRCIkHS-I (in-phase) clock signal. |
| TxDDRCIkHS-Q | I | MCNN | Clock Lane High-Speed Transmit DDR Clock. <br> This signal is used to generate the High-Speed clock signal for the Lane Interconnect. The TxDDRCIkHS-Q (quadrature) clock signal is phase shifted from the TxDDRCIkHS-I clock signal. |
| TxWordCIkHS | 0 | MXXX <br> SRXX | High-Speed Transmit Word Clock. <br> This is used to synchronize PPI signals in the high-speed transmit clock domain. It is recommended that all transmitting lane modules share one TxWordCIkHS signal. The frequency of TxWordCIkHS is dependent upon the width of the High-Speed Transmit Data, as follows: <br> - 8-bit width, TxDataHS[7:0], the High-Speed Transmit Word Clock is exactly $1 / 8$ the high-speed data rate. <br> - 16-bit width, TxDataHS[15:0], the High-Speed Transmit Word Clock is exactly $1 / 16$ the high-speed data rate. <br> - 32-bit width, TxDataHS[31:0], the High-Speed Transmit data Clock is exactly $1 / 32$ the high-speed data rate. |
| TxDataWidthHS[1:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SRXX } \end{aligned}$ | High-Speed Transmit Data bus Width Select. <br> Selects the bus width of TxDataHS: <br> - TxDataWidthHS[1:0] = 00: 8-bit, TxDataHS[7:0]. <br> - TxDataWidthHS[1:0] = 01: 16-bit, TxDataHS[15:0] <br> - TxDataWidthHS[1:0] = 10: 32-bit, TxDataHS[31:0] <br> - TxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| TxDataHS[7:0], or TxDataHS[15:0], or TxDataHS[31:0] | I | MXXX <br> SRXX | High-Speed Transmit Data bus width. <br> High-speed data to be transmitted. If the TxWordValidHS signals indicate that more than 8 bits are to be transmitted, then the byte transmission order over the physical interface is TxDataHS[7:0] followed by TxDataHS[15:8] followed by TxDataHS[23:16] followed by TxDataHS[31:24]. Data is captured on rising edges of TxWordCIkHS. The following signals are defined for the High-Speed Transmit Data bus based on the width of the transmit data path: <br> - 8-bit width - TxDataHS[7:0] <br> - 16-bit width - TxDataHS[15:0] <br> - 32-bit width - TxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be transmitted as the first bit and the MSB will be transmitted as the last bit. |
High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted.| High-Speed Transmit Word Data Valid. |
| :--- |
| When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: |
| - 8-bit width - TxWordValidHS[0] |
| - 16-bit width - TxWordValidHS[1:0] |
| - 32-bit width - TxWordValidHS[3:0] |
| The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: |
| - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted |
| - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted |
| - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted |
| - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low.| High-Speed Transmit Request and Data Valid. |
| :--- |
| A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. |
| For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. |
| For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. |
| TxRequestHS is only asserted while TxRequestEsc is low. |
TxReadyHS
O
MXXX
SRXX
MXXX
SRXX| MXXX |
| :--- |
| SRXX |
高速傳輸就緒。此高動態信號表示 TxDataHS 已經被 Lane 模組接受,可以進行序列傳輸。TxReadyHS 在 TxWordCIkHS 的上升緣有效。TxReadyHS 可選擇在偏移校準期間使用,以指示 SoT 已結束,資料通道正在傳輸偏移突波 (時脈模式)。
High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern).| High-Speed Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. |
| Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
Symbol Dir Categories Description
"TxWordValidHS[0],
or
TxWordValidHS[1:0],
or
TxWordValidHS[3:0]" I "MXXX
SRXX" "High-Speed Transmit Word Data Valid.
When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path:
- 8-bit width - TxWordValidHS[0]
- 16-bit width - TxWordValidHS[1:0]
- 32-bit width - TxWordValidHS[3:0]
The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows:
- TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted
- TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted
- TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted
- TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted."
TxEqActiveHS I MXXX This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled.
TxEqLevelHS I MXXX This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( 3.5dB+//-1dB ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( 7dB+//-1dB ) is active.
TxRequestHS I "MXXX
SRXX
MCNN" "High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence.
For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock.
For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is low."
TxReadyHS O "MXXX
SRXX" "High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS.
Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern)."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxWordValidHS[0], <br> or <br> TxWordValidHS[1:0], <br> or <br> TxWordValidHS[3:0] | I | MXXX <br> SRXX | High-Speed Transmit Word Data Valid. <br> When the High-Speed Transmit Data width is greater than 8 bits it is necessary to indicate which 8 -bit segments contain valid transmit data to be able to transmit any number of words. The following Transmit Sync Word signals are defined based on the width of the transmit data path: <br> - 8-bit width - TxWordValidHS[0] <br> - 16-bit width - TxWordValidHS[1:0] <br> - 32-bit width - TxWordValidHS[3:0] <br> The following Transmit Word Data Valid signals indicate which bits of the TxDataHS data bus contain valid data to transmit as follows: <br> - TxWordValidHS[0] - TxDataHS[7:0] contains valid data to be transmitted <br> - TxWordValidHS[1] - TxDataHS[15:8] contains valid data to be transmitted <br> - TxWordValidHS[2] - TxDataHS[23:16] contains valid data to be transmitted <br> - TxWordValidHS[3] - TxDataHS[31:24] contains valid data to be transmitted. |
| TxEqActiveHS | I | MXXX | This is a level sensitive flag indicating the equalization active state. When this flag is high, it indicates the equalization is enabled. When this flag is low, it indicates the equalization is disabled. |
| TxEqLevelHS | I | MXXX | This is a level sensitive flag indicating the equalization level. When this flag is low (i.e., zero), it indicates a low level of equalization ( $3.5 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. When this flag is high (i.e., one), it indicates a high level of equalization ( $7 \mathrm{~dB}+/-1 \mathrm{~dB}$ ) is active. |
| TxRequestHS | I | MXXX <br> SRXX <br> MCNN | High-Speed Transmit Request and Data Valid. <br> A low-to-high transition on TxRequestHS causes the Lane Module to initiate a Start-of-Transmission sequence. A high-tolow transition on TxRequest causes the Lane Module to initiate an End-of-Transmission sequence. <br> For Clock Lanes, this active high signal causes the Lane Module to begin transmitting a High-Speed clock. <br> For Data Lanes, this active high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted. The Lane Module accepts the data when both TxRequestHS and TxReadyHS are active on the same rising TxWordCIkHS clock edge. The protocol always provides valid transmit data when TxRequestHS is active. Once asserted, TxRequestHS remains high until the data has been accepted, as indicated by TxReadyHS. <br> TxRequestHS is only asserted while TxRequestEsc is low. |
| TxReadyHS | O | MXXX <br> SRXX | High-Speed Transmit Ready. <br> This active high signal indicates that TxDataHS is accepted by the Lane Module to be serially transmitted. TxReadyHS is valid on rising edges of TxWordCIkHS. <br> Optionally, TxReadyHS can be used during deskew calibration to indicate that SoT has ended and data lanes are transmitting deskew burst (clock pattern). |
High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence.| High-Speed Transmit Skew Calibration. |
| :--- |
| This is an optional pin to initiate the periodic deskew burst at the transmitter. |
| A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. |
| A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate.| High-Speed Receive Word Clock. |
| :--- |
| This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: |
| - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. |
| - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. |
| - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above.| High-Speed Receive Data Width Select. |
| :--- |
| Selects the bus width of RxDataHS: |
| - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] |
| - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] |
| - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] |
| - RxDataWidthHS[1:0] = 11: not used, reserved. |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit.| High-Speed Receive Data. |
| :--- |
| High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: |
| - 8-bit width - RxDataHS[7:0] |
| - 16-bit width - RxDataHS[15:0] |
| - 32-bit width - RxDataHS[31:0] |
| An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
Symbol Dir Categories Description
TxSkewCalHS I MXXX "High-Speed Transmit Skew Calibration.
This is an optional pin to initiate the periodic deskew burst at the transmitter.
A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration.
A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence."
High-Speed Receive Signals
RxWordCIkHS 0 "MRXX
SXXX" "High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows:
- 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly 1//8 the high-speed received data rate.
- 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly 1//16 the high-speed received data rate.
- 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly 1//32 the high-speed received data rate."
RxDataWidthHS[1:0] I "MRXX
SXXX" "High-Speed Receive Data Width Select.
Selects the bus width of RxDataHS:
- RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0]
- RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0]
- RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0]
- RxDataWidthHS[1:0] = 11: not used, reserved.
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above."
RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] 0 "MRXX
SXXX" "High-Speed Receive Data.
High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path:
- 8-bit width - RxDataHS[7:0]
- 16-bit width - RxDataHS[15:0]
- 32-bit width - RxDataHS[31:0]
An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxSkewCalHS | I | MXXX | High-Speed Transmit Skew Calibration. <br> This is an optional pin to initiate the periodic deskew burst at the transmitter. <br> A low-to-high transition on TxSkewCalHS causes the PHY to initiate a deskew calibration. <br> A high-to-low transition on TxSkewCalHS causes the PHY to stop deskew pattern transmission and initiate an end-oftransmission sequence. |
| High-Speed Receive Signals | | | |
| RxWordCIkHS | 0 | MRXX <br> SXXX | High-Speed Receive Word Clock. <br> This is used to synchronize signals in the high-speed receive clock domain. The RxWordCIkHS is generated by dividing the recovered high-speed clock. The frequency of RxWordCIkHS is dependent upon the width of the High-Speed Receive Data, as follows: <br> - 8-bit width, RxDataHS[7:0], the High-Speed Receive Word Clock is exactly $1 / 8$ the high-speed received data rate. <br> - 16-bit width, RxDataHS[15:0], the High-Speed Receive Word Clock is exactly $1 / 16$ the high-speed received data rate. <br> - 32-bit width, RxDataHS[31:0], the High-Speed Receive Word Clock is exactly $1 / 32$ the high-speed received data rate. |
| RxDataWidthHS[1:0] | I | MRXX <br> SXXX | High-Speed Receive Data Width Select. <br> Selects the bus width of RxDataHS: <br> - RxDataWidthHS[1:0] = 00: 8-bit, RxDataHS[7:0] <br> - RxDataWidthHS[1:0] = 01: 16-bit, RxDataHS[15:0] <br> - RxDataWidthHS[1:0] = 10: 32-bit, RxDataHS[31:0] <br> - RxDataWidthHS[1:0] = 11: not used, reserved. <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. |
| RxDataHS[7:0], or RxDataHS[15:0], or RxDataHS[31:0] | 0 | MRXX <br> SXXX | High-Speed Receive Data. <br> High-speed data received by the lane module. If the RxValidHS signals indicate that more than 8 bits were received, then the byte reception order over the physical interface is RxDataHS[7:0] followed by RxDataHS[15:8] followed by RxDataHS[23:16] followed by RxDataHS[31:24]. Data is transferred on rising edges of RxWordClkHS. The following signals are defined for the High-Speed Receive Data based on the width of the receive data path: <br> - 8-bit width - RxDataHS[7:0] <br> - 16-bit width - RxDataHS[15:0] <br> - 32-bit width - RxDataHS[31:0] <br> An implementation may support any data width - one fixed width, or subset of widths or all widths defined above. The LSB will be received as the first bit and the MSB will be received as the last bit. |
High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel.| High-Speed Receive Data Valid. |
| :--- |
| This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. |
| The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: |
| - 8-bit width - RxValidHS[0] |
| - 16-bit width - RxValidHS[1:0] |
| - 32-bit width - RxValidHS[3:0] |
| The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: |
| - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel |
| - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel |
| - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel |
| - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
RxActiveHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
High-Speed Reception Active(高速接收有效)。此高動態信號表示 Lane 模組正積極接收來自 Lane 互連的高速傳輸。
High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect.| High-Speed Reception Active. |
| :--- |
| This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
RxSyncHS
0
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
Receiver Synchronization Observed(接收器同步觀察)。此高動態信號表示 Lane 模組看到適當的同步化事件。在典型的高速傳輸中,當 RxActiveHS 首次被斷定時,RxSyncHS 在高速傳輸開始時的 RxWordClkHS 的一個週期內為高電平。
Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted.| Receiver Synchronization Observed. |
| :--- |
| This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
RxCIkActiveHS
0
SCNN
接收器時脈有效。此異步高電位有效訊號表示時脈通道正在接收 DDR 時脈訊號。
Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal.| Receiver Clock Active. |
| :--- |
| This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low.| Receiver DDR Clock. |
| :--- |
| This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State.| High-Speed Receive Skew Calibration. |
| :--- |
| This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
Symbol Dir Categories Description
RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] O "MRXX
SXXX" "High-Speed Receive Data Valid.
This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data.
The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path:
- 8-bit width - RxValidHS[0]
- 16-bit width - RxValidHS[1:0]
- 32-bit width - RxValidHS[3:0]
The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows:
- RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel
- RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel
- RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel
- RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel."
RxActiveHS O "MRXX
SXXX" "High-Speed Reception Active.
This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect."
RxSyncHS 0 "MRXX
SXXX" "Receiver Synchronization Observed.
This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted."
RxCIkActiveHS 0 SCNN "Receiver Clock Active.
This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal."
RxDDRCIkHS 0 SCNN "Receiver DDR Clock.
This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low."
RxSkewCalHS 0 SXXX "High-Speed Receive Skew Calibration.
This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxValidHS[0], or RxValidHS[1:0], or RxValidHS[3:0] | O | MRXX <br> SXXX | High-Speed Receive Data Valid. <br> This active high signal indicates that the lane module is driving data to the protocol layer on the RxDataHS output. There is no "RxReadyHS" signal, and the protocol layer is expected to capture RxDataHS on every rising edge of RxWordCIkHS where any RxValidHS bit is asserted. There is no provision for the protocol layer to slow down ("throttle") the receive data. <br> The following High-Speed Receive Data Valid signals are defined based on the width of the receive data path: <br> - 8-bit width - RxValidHS[0] <br> - 16-bit width - RxValidHS[1:0] <br> - 32-bit width - RxValidHS[3:0] <br> The following High-Speed Receive Data Valid signals indicate which bits of the RxDataHS data bus contain valid data as follows: <br> - RxValidHS[0] - RxDataHS[7:0] contains valid data that was received from the channel <br> - RxValidHS[1] - RxDataHS[15:8] contains valid data that was received from the channel <br> - RxValidHS[2] - RxDataHS[23:16] contains valid data that was received from the channel <br> - RxValidHS[3] - RxDataHS[31:24] contains valid data that was received from the channel. |
| RxActiveHS | O | MRXX <br> SXXX | High-Speed Reception Active. <br> This active high signal indicates that the Lane Module is actively receiving a High-Speed transmission from the Lane interconnect. |
| RxSyncHS | 0 | MRXX <br> SXXX | Receiver Synchronization Observed. <br> This active high signal indicates that the Lane Module has seen an appropriate synchronization event. In a typical High-Speed transmission, RxSyncHS is high for one cycle of RxWordClkHS at the beginning of a High-Speed transmission when RxActiveHS is first asserted. |
| RxCIkActiveHS | 0 | SCNN | Receiver Clock Active. <br> This asynchronous, active high signal indicates that a Clock Lane is receiving a DDR clock signal. |
| RxDDRCIkHS | 0 | SCNN | Receiver DDR Clock. <br> This is the received DDR clock - it may be used by the protocol if required. This signal is low whenever RxClkActiveHS is low. |
| RxSkewCalHS | 0 | SXXX | High-Speed Receive Skew Calibration. <br> This optional active high signal indicates that the high speed deskew burst is being received. RxSkewCalHS is set to the active state when the all-ones sync pattern is received, and is cleared to the inactive state when Dp and Dn transition back to the LP-11 Stop State. |
Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode.| Escape mode Transmit Clock. |
| :--- |
| This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
TxRequestEsc
I
{:[MXXX],[SXXY]:}\begin{aligned} & M X X X \\ & S X X Y \end{aligned}
Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low.| Escape mode Transmit Request. |
| :--- |
| This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted.| Escape mode Transmit Low-Power Data. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. |
| TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State.| Transmit ULP Exit Sequence. |
| :--- |
| This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. |
| The PHY later drives the Stop state (LP-11) when |
| TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. |
| This signal is ignored when the Lane is not in the ULP State. |
TxUlpsEsc
I
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
Escape mode(逃離模式) Transmit Ultra-Low Power State(傳輸超低功率狀態)。此高動態信號與 TxRequestEsc 一起斷定,使 Lane 模組進入超低功耗狀態。Lane 模組會一直維持在此模式,直到 TxRequestEsc 被解除。當 TxUlpsEsc 斷定時,TxLpdtEsc 和 TxTriggerEsc 的所有位元都為低。
Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted.| Escape mode Transmit Ultra-Low Power State. |
| :--- |
| This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. |
| TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
Symbol Dir Categories Description
Escape Mode Transmit Signals
TxClkEsc I " MXXX
SXXY " "Escape mode Transmit Clock.
This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode."
TxRequestEsc I "MXXX
SXXY" "Escape mode Transmit Request.
This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low."
TxLpdtEsc I "MXAX
SXXA" "Escape mode Transmit Low-Power Data.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted."
TxUlpsExit I "MXXX
SXXY
MCNN" "Transmit ULP Exit Sequence.
This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted.
The PHY later drives the Stop state (LP-11) when
TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP State."
TxUlpsEsc I "MXXX
SXXY" "Escape mode Transmit Ultra-Low Power State.
This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Escape Mode Transmit Signals | | | |
| TxClkEsc | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Clock. <br> This clock is directly used to generate escape sequences. The period of this clock determines the phase times for Low-Power signals as defined in Section 6.6.2. It is therefore constrained by the normative part of the D-PHY specification. See Section 9. Note that this clock is used to synchronize TurnRequest and is included for any module that supports bi-directional High-Speed operation, even if that module does not support transmit or bidirectional escape mode. |
| TxRequestEsc | I | $\begin{aligned} & M X X X \\ & S X X Y \end{aligned}$ | Escape mode Transmit Request. <br> This active high signal, asserted together with exactly one of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is used to request entry into escape mode. Once in escape mode, the Lane stays in escape mode until TxRequestEsc is de-asserted. TxRequestEsc is only asserted by the protocol while TxRequestHS is low. |
| TxLpdtEsc | I | MXAX <br> SXXA | Escape mode Transmit Low-Power Data. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter Low-Power data transmission mode. The Lane Module remains in this mode until TxRequestEsc is de-asserted. <br> TxUlpsEsc and all bits of TxTriggerEsc are low when TxLpdtEsc is asserted. |
| TxUlpsExit | I | MXXX <br> SXXY <br> MCNN | Transmit ULP Exit Sequence. <br> This active high signal is asserted when ULP state is active and the protocol is ready to leave ULP state. The PHY leaves ULP state and begins driving Mark-1 after TxUlpsExit is asserted. <br> The PHY later drives the Stop state (LP-11) when <br> TxRequestEsc is deasserted. TxUlpsExit is synchronous to TxClkEsc. <br> This signal is ignored when the Lane is not in the ULP State. |
| TxUlpsEsc | I | MXXX <br> SXXY | Escape mode Transmit Ultra-Low Power State. <br> This active high signal is asserted with TxRequestEsc to cause the Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxRequestEsc is deasserted. <br> TxLpdtEsc and all bits of TxTriggerEsc are low when TxUlpsEsc is asserted. |
Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Transmit Trigger 0-3. |
| :--- |
| One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. |
| Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. |
| TxTriggerEsc[0] corresponds to Reset-Trigger. |
| TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| TxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc.| Escape mode Transmit Data. |
| :--- |
| This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge.| Escape mode Transmit Data Valid. |
| :--- |
| This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
TxReadyEsc
O
MXAX
SXXA
MXAX
SXXA| MXAX |
| :--- |
| SXXA |
逃逸模式傳輸就緒。此高動態信號表示 TxDataEsc 已經被 Lane 模組接受,可以進行序列傳輸。TxReadyEsc 在 TxClkEsc 上升沿有效。
Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc.| Escape mode Transmit Ready. |
| :--- |
| This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
逃生模式接收訊號
RxCIkEsc
O
MXXY SXXX
逃逸模式接收時脈。此訊號用於在逃逸模式期間將接收到的資料傳輸至通訊協定。此「時脈」由 Lane 互連中的兩個低功率信號產生。由於逃逸模式資料傳輸的非同步性質,此「時脈」可能不是週期性的。
Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic.| Escape mode Receive Clock. |
| :--- |
| This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
RxLpdtEsc
O
MXXA SXAX
Escape 低功率資料接收模式。這個高電位有效信號被斷定,表示 Lane 模組處於低功率資料接收模式。在此模式下,當 RxValidEsc 啟動時,接收到的資料位元組會驅動到 RxDataEsc 輸出。當 RxLpdtEsc 斷言時,Lane 模組會維持在此模式,直到偵測到 Lane 互連的停止狀態為止。
Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Low-Power Data Receive mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
RxUlpsEsc
O
MXXY
SXXX
MXXY
SXXX| MXXY |
| :--- |
| SXXX |
Escape Ultra-Low Power(接收)模式。此高動態信號被斷言,表示 Lane 模組已進入超低功耗狀態。在 RxUlpsEsc 斷言時,Lane 模組會維持在此模式,直到偵測到 Lane 互連的停止狀態為止。
Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect.| Escape Ultra-Low Power (Receive) mode. |
| :--- |
| This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
Symbol Dir Categories Description
TxTriggerEsc[3:0] I " MXXX
SXXY " "Escape mode Transmit Trigger 0-3.
One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low.
TxTriggerEsc[0] corresponds to Reset-Trigger.
TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
TxTriggerEsc[2] corresponds to Unknown-4 Trigger.
TxTriggerEsc[3] corresponds to Unknown-5 Trigger."
TxDataEsc[7:0] I "MXAX
SXXA" "Escape mode Transmit Data.
This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc."
TxValidEsc I "MXAX
SXXA" "Escape mode Transmit Data Valid.
This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge."
TxReadyEsc O "MXAX
SXXA" "Escape mode Transmit Ready.
This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc."
Escape Mode Receive Signals
RxCIkEsc O MXXY SXXX "Escape mode Receive Clock.
This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic."
RxLpdtEsc O MXXA SXAX "Escape Low-Power Data Receive mode.
This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect."
RxUlpsEsc O "MXXY
SXXX" "Escape Ultra-Low Power (Receive) mode.
This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| TxTriggerEsc[3:0] | I | $\begin{aligned} & \text { MXXX } \\ & \text { SXXY } \end{aligned}$ | Escape mode Transmit Trigger 0-3. <br> One of these active high signals is asserted with TxRequestEsc to cause the associated Trigger to be sent across the Lane interconnect. In the receiving Lane Module, the same bit of Rx TriggerEsc is then asserted and remains asserted until the Lane interconnect returns to Stop state, which happens when TxRequestEsc is de-asserted at the transmitter. <br> Only one bit of TxTriggerEsc is asserted at any given time, and only when TxLpdtEsc and TxUlpsEsc are both low. <br> TxTriggerEsc[0] corresponds to Reset-Trigger. <br> TxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> TxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> TxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| TxDataEsc[7:0] | I | MXAX <br> SXXA | Escape mode Transmit Data. <br> This is the eight bit escape mode data to be transmitted in LowPower data transmission mode. The signal connected to TxDataEsc[0] is transmitted first. Data is captured on rising edges of TxCIkEsc. |
| TxValidEsc | I | MXAX <br> SXXA | Escape mode Transmit Data Valid. <br> This active high signal indicates that the protocol is driving valid data on TxDataEsc to be transmitted. The Lane Module accepts the data when TxRequestEsc, TxValidEsc and TxReadyEsc are all active on the same rising TxClkEsc clock edge. |
| TxReadyEsc | O | MXAX <br> SXXA | Escape mode Transmit Ready. <br> This active high signal indicates that TxDataEsc is accepted by the Lane Module to be serially transmitted. TxReadyEsc is valid on rising edges of TxClkEsc. |
| Escape Mode Receive Signals | | | |
| RxCIkEsc | O | MXXY SXXX | Escape mode Receive Clock. <br> This signal is used to transfer received data to the protocol during escape mode. This "clock" is generated from the two Low-Power signals in the Lane interconnect. Because of the asynchronous nature of Escape mode data transmission, this "clock" may not be periodic. |
| RxLpdtEsc | O | MXXA SXAX | Escape Low-Power Data Receive mode. <br> This active high signal is asserted to indicate that the Lane Module is in Low-Power data receive mode. While in this mode, received data bytes are driven onto the RxDataEsc output when RxValidEsc is active. The Lane Module remains in this mode with RxLpdtEsc asserted until a Stop state is detected on the Lane interconnect. |
| RxUlpsEsc | O | MXXY <br> SXXX | Escape Ultra-Low Power (Receive) mode. <br> This active high signal is asserted to indicate that the Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the Lane interconnect. |
Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger.| Escape mode Receive Trigger 0-3. |
| :--- |
| These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. |
| RxTriggerEsc[0] corresponds to Reset-Trigger. |
| RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. |
| RxTriggerEsc[2] corresponds to Unknown-4 Trigger. |
| RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
RxDataEsc[7:0]
O
MXXA
SXAX
MXXA
SXAX| MXXA |
| :--- |
| SXAX |
逃逸模式接收資料。這是 Lane 模組接收到的八位元逃逸模式低功耗資料。先接收連接至 RxDataEsc[0] 的訊號。資料在 RxCIkEsc 的上升緣傳輸。
Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc.| Escape mode Receive Data. |
| :--- |
| This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data.| Escape mode Receive Data Valid. |
| :--- |
| This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
控制信號
轉彎要求
I
XRXX
XFXY
XRXX
XFXY| XRXX |
| :--- |
| XFXY |
掉頭請求。這個高電位有效信號用來表示通訊協定希望將 Lane 轉向,允許對方開始傳輸。TurnRequest 在 TxClkEsc 上升沿有效。TurnRequest 僅對目前為傳送器 (Direction=0) 的 Lane 模組有效。如果 Lane 模組處於接收模式 (Direction=1),則會忽略此訊號。
Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored.| Turn Around Request. |
| :--- |
| This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input).| Transmit/Receive Direction. |
| :--- |
| This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
Disable Turn-around(停用轉換)。此訊號用來防止 (雙向) Lane 進入傳輸模式 - 即使它在 Lane 互連上觀察到 Turn-around 請求。當單向 Lane 模組連接到雙向 Lane 模組時,此功能可防止潛在的「鎖定」情況。
Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module.| Disable Turn-around. |
| :--- |
| This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer.| Force Lane Module Into Receive mode / Wait for Stop state. |
| :--- |
| This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
Symbol Dir Categories Description
RxTriggerEsc[3:0] O "MXXY
SXXX" "Escape mode Receive Trigger 0-3.
These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[0] corresponds to Reset-Trigger.
RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger.
RxTriggerEsc[2] corresponds to Unknown-4 Trigger.
RxTriggerEsc[3] corresponds to Unknown-5 Trigger."
RxDataEsc[7:0] O "MXXA
SXAX" "Escape mode Receive Data.
This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc."
RxValidEsc O "MXXA
SXAX" "Escape mode Receive Data Valid.
This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data."
Control Signals
TurnRequest I "XRXX
XFXY" "Turn Around Request.
This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored."
Direction 0 " XRXX
XFXY " "Transmit/Receive Direction.
This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( 0= Output). When Direction=1, the Lane is in receive mode (1=Input)."
TurnDisable I " XRXX
XFXY " "Disable Turn-around.
This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module."
ForceRxmode I "MRXX
MXXY
SXXX" "Force Lane Module Into Receive mode / Wait for Stop state.
This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| RxTriggerEsc[3:0] | O | MXXY <br> SXXX | Escape mode Receive Trigger 0-3. <br> These active high signals indicate that a trigger event has been received. The asserted RxTriggerEsc signal remains active until a Stop state is detected on the Lane interconnect. <br> RxTriggerEsc[0] corresponds to Reset-Trigger. <br> RxTriggerEsc[1] corresponds to Entry sequence for HS Test Mode Trigger. <br> RxTriggerEsc[2] corresponds to Unknown-4 Trigger. <br> RxTriggerEsc[3] corresponds to Unknown-5 Trigger. |
| RxDataEsc[7:0] | O | MXXA <br> SXAX | Escape mode Receive Data. <br> This is the eight-bit escape mode Low-Power data received by the Lane Module. The signal connected to RxDataEsc[0] was received first. Data is transferred on rising edges of RxCIkEsc. |
| RxValidEsc | O | MXXA <br> SXAX | Escape mode Receive Data Valid. <br> This active high signal indicates that the Lane Module is driving valid data to the protocol on the RxDataEsc output. There is no "RxReadyEsc" signal, and the protocol is expected to capture RxDataEsc on every rising edge of RxClkEsc where RxValidEsc is asserted. There is no provision for the protocol to slow down ("throttle") the receive data. |
| Control Signals | | | |
| TurnRequest | I | XRXX <br> XFXY | Turn Around Request. <br> This active high signal is used to indicate that the protocol desires to turn the Lane around, allowing the other side to begin transmission. TurnRequest is valid on rising edges of TxClkEsc. TurnRequest is only meaningful for a Lane Module that is currently the transmitter (Direction=0). If the Lane Module is in receive mode (Direction=1), this signal is ignored. |
| Direction | 0 | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Transmit/Receive Direction. <br> This signal is used to indicate the current direction of the Lane interconnect. When Direction=0, the Lane is in transmit mode ( $0=$ Output). When Direction=1, the Lane is in receive mode (1=Input). |
| TurnDisable | I | $\begin{aligned} & \text { XRXX } \\ & \text { XFXY } \end{aligned}$ | Disable Turn-around. <br> This signal is used to prevent a (bi-directional) Lane from going into transmit mode - even if it observes a turn-around request on the Lane interconnect. This is useful to prevent a potential "lock-up" situation when a unidirectional Lane Module is connected to a bi-directional Lane Module. |
| ForceRxmode | I | MRXX <br> MXXY <br> SXXX | Force Lane Module Into Receive mode / Wait for Stop state. <br> This signal allows the protocol to initialize a Lane Module, or force a bi-directional Lane Module, into receive mode. This signal is used during initialization or to resolve a contention situation. When this signal is high, the Lane Module immediately transitions into receive control mode and waits for a Stop state to appear on the Lane interconnect. When used for initialization, this signal should be released, i.e. driven low, only when the Dp & Dn inputs are in Stop state for a time Tinit, or longer. |
符號
總監
類別
說明
ForceTxStopmode
I
MXXX
SRXX
SXXY
MXXX
SRXX
SXXY| MXXX |
| :--- |
| SRXX |
| SXXY |
Force Lane Module Into Transmit mode(強制車道模組進入傳輸模式)/ Generate Stop state(產生停止狀態)。此訊號允許通訊協定在初始化或發生錯誤(例如超時)後,強制 Lane Module 進入傳輸模式和 Stop 狀態。當此信號為高電平時,Lane Module 會立即轉換為傳輸模式,且模組狀態機會被強制進入 Stop 狀態。
停止狀態
O
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
Lane is in Stop(車道處於停止狀態)。此高動態信號表示 Lane 模組(無論 Lane 模組是傳送器或接收器)目前處於 Stop(停止)狀態。請注意,此訊號與 PPI 介面中的任何時脈都是異步的。此外,協定可能會使用此訊號來間接判斷 PHY 線路電平是否處於 LP-11 狀態。
Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state.| Lane is in Stop state. |
| :--- |
| This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
啟用
I
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
啟用車道模組。這個高電位有效信號會強制 Lane Module 離開「關機」狀態。當 Enable 為低電位時,所有的線路驅動器、接收器、終結器和爭用偵測器都會關閉。此外,當 Enable 為低時,所有其他 PPI 輸入都會被忽略,而所有 PPI 輸出都會驅動至預設的非作用狀態。Enable 是電平敏感信號,不依任何時鐘而定。
Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock.| Enable Lane Module. |
| :--- |
| This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
TxUlpsClk
I
MCNN
Clock Lane 上的 Transmit Ultra-Low Power State(傳輸超低功耗狀態)。這個高電位有效信號被斷定,會導致時鐘 Lane 模組進入 Ultra-Low Power 狀態。在 TxUlpsClk 被去斷之前,該 Lane 模組會維持在此模式。
Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted.| Transmit Ultra-Low Power State on Clock Lane. |
| :--- |
| This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
RxUlpsClkNot
0
SCNN
Clock Lane 接收超低功耗狀態。此低動態信號被斷言,表示時脈通道模組已進入超低功耗狀態。Lane 模組在 RxUlpsClkNot 斷言時保持此模式,直到在 Lane 互連上偵測到 Stop 狀態為止。
Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect.| Receive Ultra-Low Power State on Clock Lane. |
| :--- |
| This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
UlpsActiveNot
O
XXXX
XCNN
XXXX
XCNN| XXXX |
| :--- |
| XCNN |
ULP 狀態(非)有效。此低電位有效信號被斷言,表示 Lane 處於 ULP 狀態。對於傳送器而言,此信號在 TxUlpsEsc 和 TxRequestEsc(時脈 Lane 的 TxUlpsClk)被確認之後一段時間才會被確認。傳輸 PHY 會持續提供 TxClkEsc,直到 UlpsActiveNot 被斷言。為了離開 ULP 狀態,傳送器會先將 TxUlpsExit 驅動為高電平,然後等 UlpsActive Not 變為高電平 (非作用中)。此時,傳輸 PHY 已處於活動狀態,並開始在 Lines 上傳輸 Mark-1。協定等待時間 Twakeup,然後將 TxRequestEsc (TxUlpsCIk) 驅動為非活動,讓 Lane 回到 Stop 狀態。對於接收器而言,此訊號表示 Lane 處於 ULP 狀態。在 ULP 狀態開始時,UlpsActiveNot 會與 RxUlpsEsc 一起被斷言,或對於 Clock Lane 而言,RxUlpsCIkNot 被斷言。在 ULP 狀態結束時,此信號變為非活動,表示 Mark-1 狀態已被觀察到。之後,經過一段時間的 Twakeup 之後,RxUlpsEsc(或 RxUlpsClkNot)訊號會被去斷。
ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted.| ULP State (not) Active. |
| :--- |
| This active low signal is asserted to indicate that the Lane is in ULP state. |
| For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. |
| For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
Symbol Dir Categories Description
ForceTxStopmode I "MXXX
SRXX
SXXY" Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state.
Stopstate O "XXXX
XCNN" "Lane is in Stop state.
This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state."
Enable I "XXXX
XCNN" "Enable Lane Module.
This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock."
TxUlpsClk I MCNN "Transmit Ultra-Low Power State on Clock Lane.
This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted."
RxUlpsClkNot 0 SCNN "Receive Ultra-Low Power State on Clock Lane.
This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect."
UlpsActiveNot O "XXXX
XCNN" "ULP State (not) Active.
This active low signal is asserted to indicate that the Lane is in ULP state.
For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| ForceTxStopmode | I | MXXX <br> SRXX <br> SXXY | Force Lane Module Into Transmit mode / Generate Stop state. This signal allows the protocol to force a Lane Module into transmit mode and Stop state during initialization or following an error situation, e.g. expired time out. When this signal is high, the Lane Module immediately transitions into transmit mode and the module state machine is forced into the Stop state. |
| Stopstate | O | XXXX <br> XCNN | Lane is in Stop state. <br> This active high signal indicates that the Lane Module, regardless of whether the Lane Module is a transmitter or a receiver, is currently in Stop state. Note that this signal is asynchronous to any clock in the PPI interface. Also, the protocol may use this signal to indirectly determine if the PHY line levels are in the LP-11 state. |
| Enable | I | XXXX <br> XCNN | Enable Lane Module. <br> This active high signal forces the Lane Module out of "shutdown". All line drivers, receivers, terminators, and contention detectors are turned off when Enable is low. Furthermore, while Enable is low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is a level sensitive signal and does not depend on any clock. |
| TxUlpsClk | I | MCNN | Transmit Ultra-Low Power State on Clock Lane. <br> This active high signal is asserted to cause a Clock Lane Module to enter the Ultra-Low Power State. The Lane Module remains in this mode until TxUlpsClk is de-asserted. |
| RxUlpsClkNot | 0 | SCNN | Receive Ultra-Low Power State on Clock Lane. <br> This active low signal is asserted to indicate that the Clock Lane Module has entered the Ultra-Low Power State. The Lane Module remains in this mode with RxUlpsClkNot asserted until a Stop state is detected on the Lane Interconnect. |
| UlpsActiveNot | O | XXXX <br> XCNN | ULP State (not) Active. <br> This active low signal is asserted to indicate that the Lane is in ULP state. <br> For a transmitter, this signal is asserted some time after TxUlpsEsc and TxRequestEsc (TxUlpsClk for a Clock Lane) are asserted. The transmitting PHY continues to supply TxClkEsc until UlpsActiveNot is asserted. In order to leave ULP state, the transmitter first drives TxUlpsExit high, then waits for UlpsActive Not to become high (inactive). At that point, the transmitting PHY is active and has started transmitting a Mark-1 on the Lines. The protocol waits for a time Twakeup and then drives TxRequestEsc (TxUlpsCIk) inactive to return the Lane to Stop state. <br> For a receiver, this signal indicates that the Lane is in ULP state. At the beginning of ULP state, UlpsActiveNot is asserted together with RxUlpsEsc, or RxUlpsCIkNot for a Clock Lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time Twakeup, the RxUlpsEsc (or RxUlpsClkNot) signal is deasserted. |
符號
總監
類別
說明
錯誤訊號
ErrSotHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
傳輸開始 (SoT) 錯誤。如果高速 SoT 領先序列被損毀,但仍能達到適當的同步,則此高電位有效信號會在 RxWordCIkHS 的一個週期內被斷言。這會被視為領先序列中的「軟錯誤」,並降低對有效負載資料的信心。
Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced.| Start-of-Transmission (SoT) Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
ErrSotSyncHS
O
MRXX
SXXX
MRXX
SXXX| MRXX |
| :--- |
| SXXX |
Start-of-Transmission Synchronization Error(傳輸開始同步錯誤)。如果高速 SoT 領先序列被破壞,以致無法預期適當的同步,則此高動態信號會在 RxWordCIkHS 的一個週期內斷言。
Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS.| Start-of-Transmission Synchronization Error. |
| :--- |
| If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state.| Escape Entry Error. |
| :--- |
| If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state.| Low-Power Data Transmission Synchronization Error. |
| :--- |
| If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state.| Control Error. |
| :--- |
| This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low.| LPO Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
ErrContentionLP1
O
MXXX
SXXY
MXXX
SXXY| MXXX |
| :--- |
| SXXY |
LP1 Contention Error(爭用錯誤)。當 Lane 模組在嘗試將線路驅動為高電平時,偵測到線路上出現爭用情況,即斷言此高動態信號。
LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high.| LP1 Contention Error. |
| :--- |
| This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Symbol Dir Categories Description
Error Signals
ErrSotHS O "MRXX
SXXX" "Start-of-Transmission (SoT) Error.
If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced."
ErrSotSyncHS O "MRXX
SXXX" "Start-of-Transmission Synchronization Error.
If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS."
ErrEsc O "MXXY
SXXX" "Escape Entry Error.
If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state."
ErrSyncEsc O "MXXA
SXAX" "Low-Power Data Transmission Synchronization Error.
If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state."
ErrControl O "MXXY
SXXX" "Control Error.
This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state."
ErrContentionLPO O "MXXX
SXXY" "LPO Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low."
ErrContentionLP1 O "MXXX
SXXY" "LP1 Contention Error.
This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high."| Symbol | Dir | Categories | Description |
| :---: | :---: | :---: | :---: |
| Error Signals | | | |
| ErrSotHS | O | MRXX <br> SXXX | Start-of-Transmission (SoT) Error. <br> If the High-Speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active high signal is asserted for one cycle of RxWordCIkHS. This is considered to be a "soft error" in the leader sequence and confidence in the payload data is reduced. |
| ErrSotSyncHS | O | MRXX <br> SXXX | Start-of-Transmission Synchronization Error. <br> If the High-Speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active high signal is asserted for one cycle of RxWordCIkHS. |
| ErrEsc | O | MXXY <br> SXXX | Escape Entry Error. <br> If an unrecognized escape entry command is received, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrSyncEsc | O | MXXA <br> SXAX | Low-Power Data Transmission Synchronization Error. <br> If the number of bits received during a Low-Power data transmission is not a multiple of eight when the transmission ends, this active high signal is asserted and remains asserted until the next change in line state. |
| ErrControl | O | MXXY <br> SXXX | Control Error. <br> This active high signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state. |
| ErrContentionLPO | O | MXXX <br> SXXY | LPO Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line low. |
| ErrContentionLP1 | O | MXXX <br> SXXY | LP1 Contention Error. <br> This active high signal is asserted when the Lane Module detects a contention situation on a line while trying to drive the line high. |
Parameter Description Min Units
TWAIT-OPTICAL Additional wait time for synchronization of the optical link 150,000 UI (lane data bit)| Parameter | Description | Min | Units |
| :---: | :---: | :---: | :---: |
| TWAIT-OPTICAL | Additional wait time for synchronization of the optical link | 150,000 | UI (lane data bit) |
附件 B 互連設計指引 (資料性)
本附錄包含設計指引,以符合第 8 節規定的互連要求。
B.1 實際距離
最大 Lane 飛行時間定義為兩納秒。假設每個 RX-TX 模組內的佈線延遲小於 100ps,則可使用外部互連橋接的物理距離約為 54cm//sqrtepsi54 \mathrm{~cm} / \sqrt{\varepsilon} 。對於大多數實用的 PCB 和柔性材料而言,這相當於約 25-30 cm 的最大距離。
B.2 RF 頻帶:干擾
在 Lane 的一側有 RF 干擾頻率,會干擾 Lane 的訊號。最有可能的主要干擾是無線互連標準的傳輸頻段頻率。另一邊則是由 Lane 所產生 EMI 應盡可能低的頻率,因為無線 IC 必須接收這些頻段中非常微弱的訊號。一些重要的頻段包括 傳輸頻帶
Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| LPDT. |
| Active HIGH signal |
TxProMarkerHS
I
MXXX
(SRXX)
MXXX
(SRXX)| MXXX |
| :--- |
| (SRXX) |
功能句柄,用於在 HS 傳輸的序列串流中插入通訊協定標記符號。高動態信號
Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal| Functional handle to insert a Protocol-marker symbol in the serial stream for |
| :--- |
| HS transmission. |
| Active HIGH signal |
Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal| Functional handle for the protocol to hold on providing data to the PHY |
| :--- |
| without ending the HS transmission. In the case of a continued transmission |
| request without Valid data, the PHY coding layer inserts Idle symbols. |
| Active HIGH signal |
Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)| Flag to indicate that a Comma code has been observed in the LPDT stream |
| :--- |
| that was not aligned with the assumed word boundary. |
| Active HIGH signal (optional) |
Symbol Dir Categories Description
TxProMarkerEsc I "MXAX
(SXXA)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
LPDT.
Active HIGH signal"
TxProMarkerHS I "MXXX
(SRXX)" "Functional handle to insert a Protocol-marker symbol in the serial stream for
HS transmission.
Active HIGH signal"
TxValidHS I "MXXX
(SRXX)" "Functional handle for the protocol to hold on providing data to the PHY
without ending the HS transmission. In the case of a continued transmission
request without Valid data, the PHY coding layer inserts Idle symbols.
Active HIGH signal"
RxAlignErrorEsc O "SXAX
(MXXA)" "Flag to indicate that a Comma code has been observed in the LPDT stream
that was not aligned with the assumed word boundary.
Active HIGH signal (optional)"| Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| TxProMarkerEsc | I | MXAX <br> (SXXA) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> LPDT. <br> Active HIGH signal |
| TxProMarkerHS | I | MXXX <br> (SRXX) | Functional handle to insert a Protocol-marker symbol in the serial stream for <br> HS transmission. <br> Active HIGH signal |
| TxValidHS | I | MXXX <br> (SRXX) | Functional handle for the protocol to hold on providing data to the PHY <br> without ending the HS transmission. In the case of a continued transmission <br> request without Valid data, the PHY coding layer inserts Idle symbols. <br> Active HIGH signal |
| RxAlignErrorEsc | O | SXAX <br> (MXXA) | Flag to indicate that a Comma code has been observed in the LPDT stream <br> that was not aligned with the assumed word boundary. <br> Active HIGH signal (optional) |
{:[" Flag to indicate that a Comma code has been observed during HS reception "],[" that was not aligned with the assumed word boundary. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received using LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that a non-existing symbol was received in HS mode. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has "],[" been detected without being preceded by an EoT-marker symbol. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}
{:[" Indication flag that Idle patterns are observed at the Lines during LPDT. "],[" Active HIGH signal (optional) "]:}\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}
(MRXX)
Symbol Dir Categories Description
RxAlignErrorHS O " SXXX
(MRXX) " " Flag to indicate that a Comma code has been observed during HS reception
that was not aligned with the assumed word boundary.
Active HIGH signal (optional) "
RxBadSymbolEsc O " SXAX
(MXXA) " " Flag to indicate that a non-existing symbol was received using LPDT.
Active HIGH signal (optional) "
RxBadSymbolHS O " SXXX
(MRXX) " " Flag to indicate that a non-existing symbol was received in HS mode.
Active HIGH signal (optional) "
RxEoTErrorEsc O " SXAX
(MXXA) " " Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleEsc O " SXXX
(MRXX) " " Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has
been detected without being preceded by an EoT-marker symbol.
Active HIGH signal (optional) "
RxIdleHS O " SXAX
(MXXA) " " Indication flag that Idle patterns are observed at the Lines during LPDT.
Active HIGH signal (optional) "
(MRXX) | Symbol | Dir | Categories | Description |
| :--- | :---: | :--- | :--- |
| RxAlignErrorHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a Comma code has been observed during HS reception } \\ \text { that was not aligned with the assumed word boundary. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received using LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxBadSymbolHS | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that a non-existing symbol was received in HS mode. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxEoTErrorEsc | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after LP transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleEsc | O | $\begin{array}{l}\text { SXXX } \\ \text { (MRXX) }\end{array}$ | $\begin{array}{l}\text { Flag to indicate that at EoT, after HS transmission, a transition to LP-11 has } \\ \text { been detected without being preceded by an EoT-marker symbol. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| RxIdleHS | O | $\begin{array}{l}\text { SXAX } \\ \text { (MXXA) }\end{array}$ | $\begin{array}{l}\text { Indication flag that Idle patterns are observed at the Lines during LPDT. } \\ \text { Active HIGH signal (optional) }\end{array}$ |
| (MRXX) | | | |