Excellent Synaptic Characteristics and Half-bias selectivity in Vertical Short-channel ECRAM and selector-free 4k Cross-point Array Demonstration
在垂直短通道 ECRAM 和无选择器的 4k 交叉点阵列演示中具有出色的突触特性和半偏倚选择性

In the field of artificial intelligence (AI), there is a growing demand for high-performance hardware with highspeed memory technologies such as high-bandwidth memory (HBM) gaining significant attention [1]. A variety of emerging non-volatile memory devices have been studied as a cross-point element in novel analog resistive cross-point array-based architectures to accelerate AI computations. In particular, a three-terminal metal-oxide based ECRAM has demonstrated superior device performance and complementary metal-oxide semiconductor (CMOS) compatibility [2]. However, conventional planar threeterminal metal-oxide based ECRAM arrays face limitations in scalability and update selectivity stemming from their 3terminal structure [3]. To address these issues, various types of ECRAM RPU and update scheme has been proposed [4-7]. However, there are still challenges to develop novel structural device with remarkable synaptic characteristics, which can overcome both limitations. The vertical ECRAM cross-point $\left(4{\mathrm{F}}^2\right)$$\left(4{\mathrm{F}}^2\right)$(4F^(2))\left(4 \mathrm{~F}^{2}\right) array can reduce the dimensions by half compared to the conventional planar cross-point array $\left(8{\mathrm{F}}^2\right)$$\left(8{\mathrm{F}}^2\right)$(8F^(2))\left(8 \mathrm{~F}^{2}\right) (Fig. 1, Table. 1).
在人工智能 （AI） 领域，对高性能硬件的需求不断增长，高速内存技术（如高带宽内存 （HBM））受到了极大的关注 [1]。已经研究了各种新兴的非易失性存储器件，作为基于新型模拟电阻交叉点阵列架构的交叉点元件，以加速 AI 计算。特别是，基于三端子金属氧化物的 ECRAM 已表现出卓越的器件性能和互补金属氧化物半导体 （CMOS） 兼容性 [2]。然而，传统的基于平面三端子金属氧化物的 ECRAM 阵列因其 3 端子结构而面临可扩展性和更新选择性的限制 [3]。为了解决这些问题，已经提出了各种类型的 ECRAM RPU 和更新方案 [4-7]。然而，开发具有显着突触特性的新型结构装置仍然存在挑战，它可以克服这两个限制。与传统的平面交叉点阵列 $\left(8{\mathrm{F}}^2\right)$$\left(8{\mathrm{F}}^2\right)$(8F^(2))\left(8 \mathrm{~F}^{2}\right) 相比，垂直 ECRAM 交叉点 $\left(4{\mathrm{F}}^2\right)$$\left(4{\mathrm{F}}^2\right)$(4F^(2))\left(4 \mathrm{~F}^{2}\right) 阵列可以将尺寸减少一半（图 1，表 1）。

In this study, we fabricated the CMOS-compatible and short channel vertical metal-oxide based ECRAM (VECRAM) devices and 4 k arrays in a symmetrical stack configuration. We validated the superior synaptic
在这项研究中，我们制造了 CMOS 兼容和短通道基于垂直金属氧化物的 ECRAM （VECRAM） 器件和对称堆栈配置的 4 k 阵列。我们验证了上突触
characteristics including update linearity, on/off ratio, switching speed, and endurance of single V-ECRAM devices due to the channel scaling effect (Table. 1). For 64 connected devices within the 4 k V-ECRAM cross-point array, a $100\mathrm{\%}$$100\mathrm{\%}$100%100 \% yield was achieved. Also, The V-ECRAM cross-point array exhibits ultra-low cycle-to-cycle (c-to-c) and device-todevice (d-to-d) variations, and vector matrix multiplication (VMM) error. Furthermore, the selective update using the half-bias (HB) scheme was more effective on vertical arrays compared to planar arrays, leading to successful training in novel hardware-aware algorithms. Lastly, we experimentally demonstrated that a 4 k V-ECRAM cross-point array with 88.8 % yield. Our results suggest that the V-ECRAM crosspoint array is a promising candidate for AI accelerators, offering substantial improvements in scalability, reliability, and computational accuracy.
特性包括由于通道缩放效应而导致的单个 V-ECRAM 器件的更新线性度、开/关比、开关速度和耐用性（表 1）。对于 4 k V-ECRAM 交叉点阵列中的 64 个连接器件，实现了良 $100\mathrm{\%}$$100\mathrm{\%}$100%100 \% 率。此外，V-ECRAM 交叉点阵列表现出超低的周期间 （c-to-c） 和器件间 （d-to-d） 变化，以及矢量矩阵乘法 （VMM） 误差。此外，与平面阵列相比，使用半偏置 （HB） 方案的选择性更新在垂直阵列上更有效，从而在新颖的硬件感知算法中成功训练。最后，我们实验证明，4 k V-ECRAM 交叉点阵列的产率为 88.8%。我们的结果表明，V-ECRAM 交叉点阵列是 AI 加速器的一个有前途的候选者，在可扩展性、可靠性和计算精度方面提供了实质性的改进。

To implement a 4 k cross-point array based on V-ECRAM, the fabrication process is illustrated in Fig. 2. First, two $\mathrm{Ti}/\mathrm{TiN}/\mathrm{W}/\mathrm{SiN}$$\mathrm{Ti}/\mathrm{TiN}/\mathrm{W}/\mathrm{SiN}$Ti//TiN//W//SiN\mathrm{Ti} / \mathrm{TiN} / \mathrm{W} / \mathrm{SiN} layers are deposited on a ${\mathrm{SiO}}_2$${\mathrm{SiO}}_2$SiO_(2)\mathrm{SiO}_{2} substrate using the plasma enhanced chemical vapor deposition (PECVD) process. These layers play the role of drain and gate lines in the cross-point array. Second, a layer for the source line is deposited using the same method. Subsequently, holes with various size from 300 nm to $10\mu \mathrm{m}$$10\mu \mathrm{m}$10 mum10 \mu \mathrm{~m} are etched at the crosspoints of the drain and source lines. Then, CMOS-compatible metal oxides stacks ( ${\mathrm{WO}}_{\mathrm{x}}/{\mathrm{HfO}}_{\mathrm{x}}/{\mathrm{WO}}_{\mathrm{x}}$${\mathrm{WO}}_{\mathrm{x}}/{\mathrm{HfO}}_{\mathrm{x}}/{\mathrm{WO}}_{\mathrm{x}}$WO_(x)//HfO_(x)//WO_(x)\mathrm{WO}_{\mathrm{x}} / \mathrm{HfO}_{\mathrm{x}} / \mathrm{WO}_{\mathrm{x}} ) are sequentially deposited in the etched via-holes to form the V-ECRAM. Finally, the gate electrode metal is deposited to connect to the gate metal line. The cross-sectional TEM and EDS elemental mapping of the V-ECRAM images show the vertical structure with short channel length of 80 nm (Fig. 3).
为了实现基于 V-ECRAM 的 4 k 交叉点阵列，制造过程如图 2 所示。首先，使用等离子体增强化学气相沉积 （PECVD） 工艺将两 $\mathrm{Ti}/\mathrm{TiN}/\mathrm{W}/\mathrm{SiN}$$\mathrm{Ti}/\mathrm{TiN}/\mathrm{W}/\mathrm{SiN}$Ti//TiN//W//SiN\mathrm{Ti} / \mathrm{TiN} / \mathrm{W} / \mathrm{SiN} 层沉积在 ${\mathrm{SiO}}_2$${\mathrm{SiO}}_2$SiO_(2)\mathrm{SiO}_{2} 衬底上。这些层在交叉点阵列中扮演 drain 线和 gate 线的角色。其次，使用相同的方法存放源行的层。随后，在漏极线和源极线的交叉点蚀刻从 300 nm $10\mu \mathrm{m}$$10\mu \mathrm{m}$10 mum10 \mu \mathrm{~m} 到各种尺寸的孔。然后，兼容 CMOS 的金属氧化物堆栈 （ ${\mathrm{WO}}_{\mathrm{x}}/{\mathrm{HfO}}_{\mathrm{x}}/{\mathrm{WO}}_{\mathrm{x}}$${\mathrm{WO}}_{\mathrm{x}}/{\mathrm{HfO}}_{\mathrm{x}}/{\mathrm{WO}}_{\mathrm{x}}$WO_(x)//HfO_(x)//WO_(x)\mathrm{WO}_{\mathrm{x}} / \mathrm{HfO}_{\mathrm{x}} / \mathrm{WO}_{\mathrm{x}} ） 依次沉积在蚀刻的通孔中，形成 V-ECRAM。最后，沉积栅极金属以连接到栅极金属线。V-ECRAM 图像的横截面 TEM 和 EDS 元素映射显示了具有 80 nm 短通道长度的垂直结构（图 3）。

For 700 nm diameter V-ECRAM, Fig. 4 shows the conductance curves of the V-ECRAM at various sweep voltage from 1 to 2 V with ${\mathrm{V}}_{\mathrm{ds}}$${\mathrm{V}}_{\mathrm{ds}}$V_(ds)\mathrm{V}_{\mathrm{ds}} of 0.1 V . Anticlockwise hysteresis indicates nonvolatile potentiation and depression in positive and negative bias, respectively. Fig. 5 shows the conductance range of the V-ECRAM can be modulated with different number of up/down pulse with good switching reproducibility. Fig. 6 (a, b) show conductance update behaviors under various pulse width with fixed gate bias of $+5/-4\mathrm{V}$$+5/-4\mathrm{V}$+5//-4V+5 /-4 \mathrm{~V} and various gate bias conditions with fixed pulse width of 300 ms . Fig. 7 (a) presents the linear relationship of
对于直径为 700 nm 的 V-ECRAM，图 4 显示了 V-ECRAM 在 1 至 2 V 和 0.1 V ${\mathrm{V}}_{\mathrm{ds}}$${\mathrm{V}}_{\mathrm{ds}}$V_(ds)\mathrm{V}_{\mathrm{ds}} 的各种扫描电压下的电导曲线。逆时针磁滞分别表示正偏置和负偏置的非易失性增强和抑制。图 5 显示了 V-ECRAM 的电导范围可以用不同数量的上/下脉冲进行调制，具有良好的开关重现性。图 6 （a， b） 显示了在固定栅极偏置 $+5/-4\mathrm{V}$$+5/-4\mathrm{V}$+5//-4V+5 /-4 \mathrm{~V} 和固定脉冲宽度为 300 ms 的各种栅极偏置条件下的电导更新行为。图 7 （a） 显示了
$\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} with ${\mathrm{t}}_{\text{pulse}}$${\mathrm{t}}_{\text{pulse }}$t_("pulse ")\mathrm{t}_{\text {pulse }}. Also, $\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} exhibits an exponential trend according to the gate voltage, as shown in Fig. 7 (b). Therefore, selector-less synapse array operation is enabled using the HB scheme. For 500 nm diameter V-ECRAM, highly symmetric and linear conductance modulation is demonstrated at 50 up/down update pulses with $+2/-1.5\mathrm{V}$$+2/-1.5\mathrm{V}$+2//-1.5V+2 /-1.5 \mathrm{~V} and 100 ms (Fig. 8). The V-ECRAM device shows a wide dynamic range of the channel conductance over 17,000 by applying voltage pulses of +5 V at various pulse widths from 1 to 300 ms (Fig. 9). Retention characteristics of V-ECRAM further confirmed the stability of 15 programmed analog states within the dynamic range during 1000 s (Fig. 10). Also, strong endurance characteristics is demonstrated by repeatedly switching the device for over 10 million pulses with $+3.5/-2.5$$+3.5/-2.5$+3.5//-2.5+3.5 /-2.5 V, 1 ms (Fig. 11). High-speed conductance switching of 500 ns was verified at ${\mathrm{V}}_{\mathrm{g}}=+12/-10\mathrm{V}$${\mathrm{V}}_{\mathrm{g}}=+12/-10\mathrm{V}$V_(g)=+12//-10V\mathrm{V}_{\mathrm{g}}=+12 /-10 \mathrm{~V} (Fig. 12). In addition, we evaluated the effect of device scaling on synaptic properties (Fig. 13). V-ECRAM shows on/off ratio over 50 times higher than that of planar metal-oxide based ECRAM (P-ECRAM) (Fig. 14).
$\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} 与 ${\mathrm{t}}_{\text{pulse}}$${\mathrm{t}}_{\text{pulse }}$t_("pulse ")\mathrm{t}_{\text {pulse }} .此外， $\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} 根据栅极电压呈现指数趋势，如图 7 （b） 所示。因此，使用 HB 方案启用无选择者的突触阵列操作。对于直径为 500 nm 的 V-ECRAM，在 50 个上/下更新脉冲 $+2/-1.5\mathrm{V}$$+2/-1.5\mathrm{V}$+2//-1.5V+2 /-1.5 \mathrm{~V} 和 100 ms 下表现出高度对称和线性的电导调制（图 8）。V-ECRAM 器件通过在 1 至 300 ms 的各种脉冲宽度下施加 +5 V 的电压脉冲，显示出超过 17,000 的宽通道电导动态范围（图 9）。V-ECRAM 的保留特性进一步证实了 1000 s 内动态范围内 15 种编程模拟状态的稳定性（图 10）。此外，通过 $+3.5/-2.5$$+3.5/-2.5$+3.5//-2.5+3.5 /-2.5 V、1 ms 的反复切换设备超过 1000 万个脉冲，证明了强大的耐久性特性（图 11）。验证了 500 ns 的高速电导开关 ${\mathrm{V}}_{\mathrm{g}}=+12/-10\mathrm{V}$${\mathrm{V}}_{\mathrm{g}}=+12/-10\mathrm{V}$V_(g)=+12//-10V\mathrm{V}_{\mathrm{g}}=+12 /-10 \mathrm{~V} （图 12）。此外，我们还评估了装置缩放对突触特性的影响（图 13）。V-ECRAM 的开/关比比平面金属氧化物基 ECRAM （P-ECRAM） 高 50 倍以上（图 14）。

Next, we demonstrated the 4 k V-ECRAM cross-point array operation. Fig. 15 shows the optical microscope image of large-scale 4 k array. Our 4 k array shows the highest density with a $0.41{\mathrm{mm}}^2$$0.41{\mathrm{mm}}^2$0.41mm^(2)0.41 \mathrm{~mm}^{2} area and $4{\mathrm{F}}^2$$4{\mathrm{F}}^2$4F^(2)4 \mathrm{~F}^{2} layout compared to previously reported ECRAM arrays [3, 6]. Fig. 16 (a, b) compare the update selectivity of P-ECRAM and V-ECRAM cross-point array. In V-ECRAM, the nonlinearity factor ( $\mathrm{k}=$$\mathrm{k}=$k=\mathrm{k}= $\mathrm{\Delta }\mathrm{G}\left(0.5{\mathrm{V}}_{\text{prog}}\right)/\mathrm{\Delta }\mathrm{G}\left({\mathrm{V}}_{\text{prog}}\right))$$\left.\mathrm{\Delta }\mathrm{G}\left(0.5{\mathrm{V}}_{\text{prog }}\right)/\mathrm{\Delta }\mathrm{G}\left({\mathrm{V}}_{\text{prog }}\right)\right)${: DeltaG(0.5V_("prog "))//DeltaG(V_("prog ")))\left.\Delta \mathrm{G}\left(0.5 \mathrm{~V}_{\text {prog }}\right) / \Delta \mathrm{G}\left(\mathrm{V}_{\text {prog }}\right)\right) was calculated as 0.03 , which is 6 times lower than P-ECRAM attributed to the increased effective update region caused by the channel scaling effect. To verify the capability of selective update in the HB scheme, we experimentally demonstrated the training of single-parameter linear regression using novel hardware-aware algorithms (Tiki-Taka version $1\mathrm{\&}2$$1\mathrm{\&}2$1&21 \& 2 (TTv1 & 2)) using the V-ECRAM cross-point array (Fig. 17). Furthermore, we evaluated the performance of 64 connected devices within a 4 k V-ECRAM array. Fig. 18 (a, b) shows conductance switching of 64 accessible devices within a specially designed 4 k array at 50 up/down pulses with $+2/-1.4\mathrm{V}$$+2/-1.4\mathrm{V}$+2//-1.4V+2 /-1.4 \mathrm{~V} and 300 ms showing $100\mathrm{\%}$$100\mathrm{\%}$100%100 \% yield. Moreover, a remarkably low c-to-c variation of 0.023 for 20 cycles and d-to-d variation of 0.0985 were observed across the 64 devices within a 4 k array (Fig. 19 (a, b)). To accelerate the AI computation, parallel VMM operation must be performed in the analog cross-point array. Fig. 20 shows an I-V characteristics of 64 devices within a 4 k array. The good I-V linearity demonstrates that the V-ECRAM accurately follows the Ohm’s law. Experimental VMM of 64 devices in an 4 k array was also evaluated. Since the output values correspond to the expected value, the Kirchhoff’s current raw is verified in the V-ECRAM cross-point array (Fig. 21). Fig. 22 exhibits the histogram plot of VMM error. Significantly low average error of $-0.18\mathrm{\%}$$-0.18\mathrm{\%}$-0.18%-0.18 \% and standard deviation of $0.55\mathrm{\%}$$0.55\mathrm{\%}$0.55%0.55 \% were obtained. Fig. 23 shows experimental programming of target image patterns using the HB scheme within a 4 k V-ECRAM cross-point array. It was
接下来，我们演示了 4 k V-ECRAM 交叉点阵列操作。图 15 显示了大规模 4 k 阵列的光学显微镜图像。与以前报道的 ECRAM 数组相比，我们的 4 k 数组在 $0.41{\mathrm{mm}}^2$$0.41{\mathrm{mm}}^2$0.41mm^(2)0.41 \mathrm{~mm}^{2} 面积和 $4{\mathrm{F}}^2$$4{\mathrm{F}}^2$4F^(2)4 \mathrm{~F}^{2} 布局方面显示出最高的密度 [3， 6]。图 16 （a， b） 比较了 P-ECRAM 和 V-ECRAM 交叉点阵列的更新选择性。在 V-ECRAM 中，非线性因子 （ $\mathrm{k}=$$\mathrm{k}=$k=\mathrm{k}= $\mathrm{\Delta }\mathrm{G}\left(0.5{\mathrm{V}}_{\text{prog}}\right)/\mathrm{\Delta }\mathrm{G}\left({\mathrm{V}}_{\text{prog}}\right))$$\left.\mathrm{\Delta }\mathrm{G}\left(0.5{\mathrm{V}}_{\text{prog }}\right)/\mathrm{\Delta }\mathrm{G}\left({\mathrm{V}}_{\text{prog }}\right)\right)${: DeltaG(0.5V_("prog "))//DeltaG(V_("prog ")))\left.\Delta \mathrm{G}\left(0.5 \mathrm{~V}_{\text {prog }}\right) / \Delta \mathrm{G}\left(\mathrm{V}_{\text {prog }}\right)\right) 计算为 0.03 ，比 P-ECRAM 低 6 倍，这归因于通道缩放效应导致有效更新区域增加。为了验证HB方案中选择性更新的能力，我们实验演示了使用新型硬件感知算法（Tiki-Taka版本 $1\mathrm{\&}2$$1\mathrm{\&}2$1&21 \& 2 （TTv1 & 2））使用V-ECRAM交叉点阵列（图17）进行单参数线性回归的训练。此外，我们还评估了 4 k V-ECRAM 阵列中 64 个连接设备的性能。图 18 （a， b） 显示了专门设计的 4 k 阵列中 64 个可访问器件的电导切换，频率为 50 个上/下脉冲， $+2/-1.4\mathrm{V}$$+2/-1.4\mathrm{V}$+2//-1.4V+2 /-1.4 \mathrm{~V} 其中 300 ms 显示 $100\mathrm{\%}$$100\mathrm{\%}$100%100 \% 良率。此外，在 4 k 阵列内的 64 个器件中观察到 20 个循环的 c-to-c 变化非常低，为 0.023，d-to-d 变化为 0.0985（图 19 （a， b））。为了加速 AI 计算，必须在模拟交叉点阵列中执行并行 VMM 操作。图 20 显示了 4 k 阵列中 64 个器件的 I-V 特性。良好的 I-V 线性度表明 V-ECRAM 准确遵循欧姆定律。还评估了 4 k 阵列中 64 个器件的实验 VMM。由于输出值与预期值相对应，因此在 V-ECRAM 交叉点数组中验证了 Kirchhoff 的电流原始值（图 21）。无花果。 图 22 显示了 VMM 误差的直方图。获得了显着较低的平均误差 $-0.18\mathrm{\%}$$-0.18\mathrm{\%}$-0.18%-0.18 \% 和标准差 $0.55\mathrm{\%}$$0.55\mathrm{\%}$0.55%0.55 \% 。图 23 显示了在 4 k V-ECRAM 交叉点阵列中使用 HB 方案对目标图像图形进行实验编程。它是
confirmed that only targeted devices were updated while others are not, enabled by the excellent selectivity of the VECRAM. Based on the synaptic characteristics of the VECRAM, we perform the MNIST training simulation using the IBM AIHWKIT tool [9]. In multi-layer perceptron (MLP)-based and LeNet-5 neural network, our V-ECRAM shows high training accuracy of $97\mathrm{\%}$$97\mathrm{\%}$97%97 \% close to the ideal device (Fig. 24).
确认只有目标设备被更新，而其他设备没有更新，这得益于 VECRAM 的出色选择性。基于 VECRAM 的突触特性，我们使用 IBM AIHWKIT 工具 [9] 执行 MNIST 训练模拟。在基于多层感知器 （MLP） 和 LeNet-5 神经网络中，我们的 V-ECRAM 显示出 $97\mathrm{\%}$$97\mathrm{\%}$97%97 \% 接近理想器件的高训练精度（图 24）。

Lastly, we successfully conducted parallel conductance modulation of 4 k V-ECRAM cross-point array. Fig. 25 is the measurement setup for testing a 4 k V-ECRAM cross-point array. The peripheral circuit PCB manages the program/read input pulses through the activation module and processes outputs via matrix processing unit [10]. The external FPGA communicates with the host PC and regulates the signals entering to the peripheral circuit PCB. Fig. 26 represents full yield heatmap and four representative conductance switching characteristics of vertical 4 k cross-point array. Grey-colored pixels depict all devices with conductance updates, achieving $88.8\mathrm{\%}$$88.8\mathrm{\%}$88.8%88.8 \% yield. The readout noise found in the weight update characteristics is originated from the mismatch between matrix processing unit and ADC in peripheral circuit PCB , not from device itself [10]. Programming pulses of $+2.5\mathrm{V},1$$+2.5\mathrm{V},1$+2.5V,1+2.5 \mathrm{~V}, 1 s for up and $-2.5\mathrm{V},0.8\mathrm{s}$$-2.5\mathrm{V},0.8\mathrm{s}$-2.5V,0.8s-2.5 \mathrm{~V}, 0.8 \mathrm{~s} for down were applied using the HB scheme and read pulses of $+0.5\mathrm{V},7\mathrm{ms}$$+0.5\mathrm{V},7\mathrm{ms}$+0.5V,7ms+0.5 \mathrm{~V}, 7 \mathrm{~ms} were applied to each drain line. In comparison to previously reported vertical ECRAMs, our proposed V-ECRAM offer excellent device characteristics and largest array demonstration (Table. 2).
最后，我们成功地进行了 4 k V-ECRAM 交叉点阵列的并联电导调制。图 25 是测试 4 k V-ECRAM 交叉点阵列的测量设置。外围电路 PCB 通过激活模块管理编程/读取输入脉冲，并通过矩阵处理单元 [10] 处理输出。外部 FPGA 与主机 PC 通信并调节进入外围电路 PCB 的信号。图 26 表示垂直 4 k 交叉点阵列的全良率热图和四个代表性的电导切换特性。灰色像素描绘了所有具有电导更新的器件，从而实现了 $88.8\mathrm{\%}$$88.8\mathrm{\%}$88.8%88.8 \% 良率。在权重更新特性中发现的读出噪声来自外围电路 PCB 中矩阵处理单元和 ADC 之间的不匹配，而不是来自器件本身 [10]。使用 HB 方案应用向上和 $-2.5\mathrm{V},0.8\mathrm{s}$$-2.5\mathrm{V},0.8\mathrm{s}$-2.5V,0.8s-2.5 \mathrm{~V}, 0.8 \mathrm{~s} 向下的 $+2.5\mathrm{V},1$$+2.5\mathrm{V},1$+2.5V,1+2.5 \mathrm{~V}, 1 s 编程脉冲，并将读取脉冲 $+0.5\mathrm{V},7\mathrm{ms}$$+0.5\mathrm{V},7\mathrm{ms}$+0.5V,7ms+0.5 \mathrm{~V}, 7 \mathrm{~ms} 应用于每条漏极线。与之前报道的垂直 ECRAM 相比，我们提出的 V-ECRAM 提供了出色的器件特性和最大的阵列演示（表 2）。

In conclusion, we experimentally demonstrated the 4 k CMOS-compatible short channel V-ECRAM cross-point array. Superior synaptic characteristics including linearity, on/off ratio, switching speed, and endurance were achieved attributed to the scaled down channel of the V-ECRAM. Furthermore, selectivity of weight updates in the HB scheme was advanced in V-ECRAM compared to P-ECRAM. We validated the hardware-aware training algorithms within the V-ECRAM cross-point array. We also confirm that VECRAM cross-point array exhibits remarkably uniform characteristics. Finally, we experimentally demonstrate a 4 k V-ECRAM cross-point array with 88.8 % yield for the first time. The V-ECRAM presented in this study can be a promising RPU candidate for AI accelerators.
总之，我们实验演示了 4 k CMOS 兼容的短通道 V-ECRAM 交叉点阵列。由于 V-ECRAM 的缩小通道，实现了卓越的突触特性，包括线性度、开/关比、开关速度和耐久性。此外，与 P-ECRAM 相比，V-ECRAM 中 HB 方案中权重更新的选择性更高。我们验证了 V-ECRAM 交叉点阵列中的硬件感知训练算法。我们还证实 VECRAM 交叉点阵列表现出非常均匀的特性。最后，我们首次通过实验证明了 4 k V-ECRAM 交叉点阵列，产率为 88.8%。本研究中提出的 V-ECRAM 可以成为 AI 加速器的有前途的 RPU 候选者。

This work was supported by the MOTIE (Ministry of Trade, Industry & Energy) (1415187361) and KSRC (Korea Semiconductor Research Consortium) (RS-2023-00236568) support program for the development of the future semiconductor device. This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT(RS-2024-00405960). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
这项工作得到了MOTIE（贸易、工业和能源部）（1415187361）和KSRC（韩国半导体研究联盟）（RS-2023-00236568）支持计划的支持，以开发未来的半导体设备。这项研究得到了韩国科学和信息通信技术部资助的国家研究基金会 （NRF） 的国家研发计划 （RS-2024-00405960） 的支持。EDA 工具得到了韩国 IC 设计教育中心 （IDEC） 的支持。

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[1] Y. Kwon 等人，ISSCC （2021）。[2] S. Kim 等人，IEDM （2019）。[3] K. Noh 等人，科学进展 （2024）。[4] S. Kim 等人，Adv. Electron.母公司。（2023）. [5] C. Lee 等人，VLSI （2021）。[6] H. Lee 等人，Adv. Electron.母公司。（2022）. [7] H. Kim 等人，科学报告 （2023）。[8] T. Gokmen 等人，Front。神经科学。（2016）. [9] MJ Rasch 等人，AICAS （2021）。[10] M. Um 等人，BioCAS （2023）

Fig. 1. Illustration of vertical metal-oxide based ECRAM (V-ECRAM) cross-point array for analog AI accelerator. The 3terminal ECRAM stack is comprised of channel, electrolyte and reservoir.
图 1.用于模拟 AI 加速器的基于垂直金属氧化物的 ECRAM （V-ECRAM） 交叉点阵列的图示。3 端子 ECRAM 堆栈由通道、电解液和储液罐组成。

Fig. 2. The fabrication process of V-ECRAM cross-point array including (a) drain, gate and middle source metal line (Ti/TiN/W/SiN-PECVD) formation, (b) via-hole etching of various sizes, © ECRAM stack formation, and (d) gate electrode metal deposition (W), which is connected to the gate metal line.
图 2.V-ECRAM 交叉点阵列的制造工艺包括 （a） 漏极、栅极和中间源极金属线 （Ti/TiN/W/SiN-PECVD） 形成，（b） 各种尺寸的通孔蚀刻，© ECRAM 堆栈形成，以及 （d） 连接到栅极金属线的栅极金属沉积 （W）。

Fig. 3. Cross-sectional TEM image and EDS elemental mapping of the V ECRAM. Vertical structure with short channel length of 80 nm is confirmed.
图 3.V ECRAM 的横截面 TEM 图像和 EDS 元素映射。确认了具有 80 nm 短通道长度的垂直结构。
(a)  （一）

Fig. 7. $\mathrm{\Delta }$$\mathrm{\Delta }$Delta\Delta G distribution per update pulse as a function of the (a) pulse width and (b) gate voltage. Selective update in the half-bias scheme can be successfully performed because $\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} follows the exponential trend according to ${\mathrm{V}}_{\mathrm{g}}$${\mathrm{V}}_{\mathrm{g}}$V_(g)\mathrm{V}_{\mathrm{g}}.
图 7. $\mathrm{\Delta }$$\mathrm{\Delta }$Delta\Delta 每个更新脉冲的 G 分布与 （a） 脉冲宽度和 （b） 栅极电压的关系。半偏置方案中的选择性更新可以成功执行，因为 $\mathrm{\Delta }\mathrm{G}$$\mathrm{\Delta }\mathrm{G}$DeltaG\Delta \mathrm{G} 根据 ${\mathrm{V}}_{\mathrm{g}}$${\mathrm{V}}_{\mathrm{g}}$V_(g)\mathrm{V}_{\mathrm{g}} 遵循指数趋势。

Fig. 4. Conductance curves of the VECRAM at various sweep voltages with ${\mathrm{V}}_{\mathrm{ds}}$${\mathrm{V}}_{\mathrm{ds}}$V_(ds)\mathrm{V}_{\mathrm{ds}} of 0.1 V . Anticlockwise hysteresis indicates nonvolatile potentiation and depression in positive and negative bias, respectively. (Hole diameter: 700 nm )
图 4.VECRAM 在 0.1 V 的各种扫描电压 ${\mathrm{V}}_{\mathrm{ds}}$${\mathrm{V}}_{\mathrm{ds}}$V_(ds)\mathrm{V}_{\mathrm{ds}} 下的电导曲线。逆时针磁滞分别表示正偏置和负偏置的非易失性增强和抑制。（孔径：700 nm ）

Fig. 8. Linear switching characteristics of V-ECRAM under 100 up/down update pulses with $+2/-1.5\mathrm{V},100\mathrm{ms}$$+2/-1.5\mathrm{V},100\mathrm{ms}$+2//-1.5V,100ms+2 /-1.5 \mathrm{~V}, 100 \mathrm{~ms}. The linearity of potentiation ( ${\alpha }_p$${\alpha }_p$alpha_(p)\alpha_{p} ) and depression $\left({\alpha }_D\right)$$\left({\alpha }_D\right)$(alpha_(D))\left(\alpha_{D}\right) was 0.296 and 1.318 , respectively. (Hole diameter: 500 nm )
图 8.V-ECRAM 在 100 个上/下更新脉冲下的线性开关特性。 $+2/-1.5\mathrm{V},100\mathrm{ms}$$+2/-1.5\mathrm{V},100\mathrm{ms}$+2//-1.5V,100ms+2 /-1.5 \mathrm{~V}, 100 \mathrm{~ms} 增强 （ ${\alpha }_p$${\alpha }_p$alpha_(p)\alpha_{p} ） 和抑制 $\left({\alpha }_D\right)$$\left({\alpha }_D\right)$(alpha_(D))\left(\alpha_{D}\right) 的线性度分别为 0.296 和 1.318。（孔径：500 nm ）

Fig. 11. Demonstration of endurance for ${10}^7$${10}^7$10^(7)10^{7} update pulses on a V-ECRAM. A cycle of $10,000\mathrm{up}/$$10,000\mathrm{up}/$10,000up//10,000 \mathrm{up} / down update pulses with $+3.5/-2.5\mathrm{V},1\mathrm{ms}$$+3.5/-2.5\mathrm{V},1\mathrm{ms}$+3.5//-2.5V,1ms+3.5 /-2.5 \mathrm{~V}, 1 \mathrm{~ms} is repeated 503 times.
图 11.V-ECRAM 上 ${10}^7$${10}^7$10^(7)10^{7} 更新脉冲的耐久性演示。 $10,000\mathrm{up}/$$10,000\mathrm{up}/$10,000up//10,000 \mathrm{up} / 一个 down update 脉冲周期 $+3.5/-2.5\mathrm{V},1\mathrm{ms}$$+3.5/-2.5\mathrm{V},1\mathrm{ms}$+3.5//-2.5V,1ms+3.5 /-2.5 \mathrm{~V}, 1 \mathrm{~ms} 重复 503 次。

Fig. 12. High-speed switching characteristics of a V-ECRAM is verified under $250\mathrm{up}/$$250\mathrm{up}/$250up//250 \mathrm{up} / down update pulses with $+12/-10\mathrm{V},500\mathrm{ns}$$+12/-10\mathrm{V},500\mathrm{ns}$+12//-10V,500ns+12 /-10 \mathrm{~V}, 500 \mathrm{~ns}.
图 12.V-ECRAM 的高速开关特性在下行更新脉冲 $+12/-10\mathrm{V},500\mathrm{ns}$$+12/-10\mathrm{V},500\mathrm{ns}$+12//-10V,500ns+12 /-10 \mathrm{~V}, 500 \mathrm{~ns} 下 $250\mathrm{up}/$$250\mathrm{up}/$250up//250 \mathrm{up} / 验证。

Fig. 5. Conductance switching of the V-ECRAM by applying successive up/down pulsing cycles with different pulse numbers of $30,50,100$$30,50,100$30,50,10030,50,100, and 250. ${\mathrm{V}}_{\mathrm{g}}$${\mathrm{V}}_{\mathrm{g}}$V_(g)\mathrm{V}_{\mathrm{g}} and pulse width are $+2/-1.7\mathrm{V}$$+2/-1.7\mathrm{V}$+2//-1.7V+2 /-1.7 \mathrm{~V} and 300 ms , respectively.
图 5.V-ECRAM 的电导开关，通过应用具有不同脉冲数 $30,50,100$$30,50,100$30,50,10030,50,100 和 250 的连续上/下脉冲周期来实现。 ${\mathrm{V}}_{\mathrm{g}}$${\mathrm{V}}_{\mathrm{g}}$V_(g)\mathrm{V}_{\mathrm{g}} 和脉冲宽度分别为 $+2/-1.7\mathrm{V}$$+2/-1.7\mathrm{V}$+2//-1.7V+2 /-1.7 \mathrm{~V} 和 300 ms 。

Fig. 9. Confirmation of dynamic range of V-ECRAM by applying voltage pulses of +5 V at various pulse widths from 1 ms to 300 ms . Maximum on/off ratio of 17,000 was obtained.
图 9.通过在 1 ms 至 300 ms 的各种脉冲宽度下施加 +5 V 的电压脉冲来确认 V-ECRAM 的动态范围。获得的最大开/关比为 17,000。

Fig. 13. Conductance switching behavior under various hole diameters of (a) 700 nm , (b) $1.5\mu \mathrm{m}$$1.5\mu \mathrm{m}$1.5 mum1.5 \mu \mathrm{~m} © $3\mu \mathrm{m}$$3\mu \mathrm{m}$3mum3 \mu \mathrm{~m}, and (d) $5\mu \mathrm{m}$$5\mu \mathrm{m}$5mum5 \mu \mathrm{~m}. Consistent and symmetric switching characteristics are obtained, independent of hole size.
图 13.（a） 700 nm、（b） $1.5\mu \mathrm{m}$$1.5\mu \mathrm{m}$1.5 mum1.5 \mu \mathrm{~m} © $3\mu \mathrm{m}$$3\mu \mathrm{m}$3mum3 \mu \mathrm{~m} 和 （d） $5\mu \mathrm{m}$$5\mu \mathrm{m}$5mum5 \mu \mathrm{~m} 各种孔径下的电导切换行为。获得一致且对称的开关特性，与孔尺寸无关。

Fig. 6. Conductance switching properties when voltage pulses given at gate (a) with various pulse widths with a fixed gate bias of $+5/-4\mathrm{V}$$+5/-4\mathrm{V}$+5//-4V+5 /-4 \mathrm{~V} and (b) with various pulse amplitudes with a pulse width of 300 ms .
图 6.在栅极 （a） 处给出电压脉冲时，具有固定栅极偏置的各种脉冲宽度 $+5/-4\mathrm{V}$$+5/-4\mathrm{V}$+5//-4V+5 /-4 \mathrm{~V} ，以及 （b） 具有脉冲宽度为 300 ms 的各种脉冲振幅时的电导开关特性。

Fig. 10. Retention characteristics of VECRAM within the dynamic range. Retention of 1000 s was observed for 15 conductance states between the high and low resistance state (HRS and LRS) .
图 10.VECRAM 在动态范围内的保留特性。在高电阻状态和低电阻状态 （HRS 和 LRS） 之间的 15 种电导状态中观察到 1000 秒的保留时间。

Fig. 14. On/off ratio in different gate area. The on/off ratios of V-ECRAM have increased by more than 50 times compared to P-ECRAM due to the scaling effect.
图 14.不同浇口区域的开/关比。由于缩放效应，V-ECRAM 的开/关比 P-ECRAM 增加了 50 倍以上。